[PATCH v2 0/6] SM6115/SM6125 MDSS core reset

[PATCH v2 0/6] SM6115/SM6125 MDSS core reset

[Val Packett]

v2: Collect R-b/T-b, expand commit messages to describe the issue everywhere
v1: https://lore.kernel.org/all/20260216233600.13098-2-val@packett.cool/

Val Packett (6):
  dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets
  dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets
  clk: qcom: dispcc-sm6115: Add missing MDSS resets
  clk: qcom: dispcc-sm6125: Add missing MDSS resets
  arm64: dts: qcom: sm6115: Add missing MDSS core reset
  arm64: dts: qcom: sm6125: Add missing MDSS core reset

 arch/arm64/boot/dts/qcom/sm6115.dtsi           | 2 ++
 arch/arm64/boot/dts/qcom/sm6125.dtsi           | 3 +++
 drivers/clk/qcom/dispcc-sm6115.c               | 7 +++++++
 drivers/clk/qcom/dispcc-sm6125.c               | 7 +++++++
 include/dt-bindings/clock/qcom,dispcc-sm6125.h | 6 +++++-
 include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 +++++--
 6 files changed, 29 insertions(+), 3 deletions(-)

-- 
2.52.0

[PATCH v2 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

[Val Packett]

Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bindings")
Signed-off-by: Val Packett <val@packett.cool>
---
 include/dt-bindings/clock/qcom,sm6115-dispcc.h | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/include/dt-bindings/clock/qcom,sm6115-dispcc.h b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
index d1a6c45b5029..ab8d312ade37 100644
--- a/include/dt-bindings/clock/qcom,sm6115-dispcc.h
+++ b/include/dt-bindings/clock/qcom,sm6115-dispcc.h
@@ -6,7 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6115_H
 
-/* DISP_CC clocks */
+/* Clocks */
 #define DISP_CC_PLL0			0
 #define DISP_CC_PLL0_OUT_MAIN		1
 #define DISP_CC_MDSS_AHB_CLK		2
@@ -30,7 +30,10 @@
 #define DISP_CC_SLEEP_CLK		20
 #define DISP_CC_SLEEP_CLK_SRC		21
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+
+/* GDSCs */
 #define MDSS_GDSC			0
 
 #endif
-- 
2.52.0

Re: [PATCH v2 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

[Krzysztof Kozlowski]

On Sat, Feb 28, 2026 at 05:41:27PM -0300, Val Packett wrote:
> Add the missing defines for MDSS resets, which are necessary to reset
> the display subsystem in order to avoid issues caused by state left over
> from the bootloader.
> 
> While here, align comment style with other SoCs.
> 
> Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bindings")

IMO this is still not fix. Missing feature in original posting is not a
bug, it's just incomplete posting which is in general accepted.

Your commit msg tries to explain the bug and I see nothing relevant to
this binding. From that explanation I see nothing wrong in mentioned
fixed commit.

Please drop fixes.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

[Dmitry Baryshkov]

On Sun, Mar 01, 2026 at 12:52:57PM +0100, Krzysztof Kozlowski wrote:
> On Sat, Feb 28, 2026 at 05:41:27PM -0300, Val Packett wrote:
> > Add the missing defines for MDSS resets, which are necessary to reset
> > the display subsystem in order to avoid issues caused by state left over
> > from the bootloader.
> > 
> > While here, align comment style with other SoCs.
> > 
> > Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bindings")
> 
> IMO this is still not fix. Missing feature in original posting is not a
> bug, it's just incomplete posting which is in general accepted.
> 
> Your commit msg tries to explain the bug and I see nothing relevant to
> this binding. From that explanation I see nothing wrong in mentioned
> fixed commit.
> 
> Please drop fixes.

Here we have an interesting situation. Patches for the bindings and for
the clock driver are not fixes. The DT patch is a fix, because MDSS /
DPU can misbehave when switching from the bootloader configuration to
the running system.

> 
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> 
> Best regards,
> Krzysztof
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/6] dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

[Krzysztof Kozlowski]

On 01/03/2026 14:14, Dmitry Baryshkov wrote:
> On Sun, Mar 01, 2026 at 12:52:57PM +0100, Krzysztof Kozlowski wrote:
>> On Sat, Feb 28, 2026 at 05:41:27PM -0300, Val Packett wrote:
>>> Add the missing defines for MDSS resets, which are necessary to reset
>>> the display subsystem in order to avoid issues caused by state left over
>>> from the bootloader.
>>>
>>> While here, align comment style with other SoCs.
>>>
>>> Fixes: 38557c6fc077 ("dt-bindings: clock: add QCOM SM6115 display clock bindings")
>>
>> IMO this is still not fix. Missing feature in original posting is not a
>> bug, it's just incomplete posting which is in general accepted.
>>
>> Your commit msg tries to explain the bug and I see nothing relevant to
>> this binding. From that explanation I see nothing wrong in mentioned
>> fixed commit.
>>
>> Please drop fixes.
> 
> Here we have an interesting situation. Patches for the bindings and for
> the clock driver are not fixes. The DT patch is a fix, because MDSS /
> DPU can misbehave when switching from the bootloader configuration to
> the running system.

If these are not fixes, then they should not carry a tag claiming they
are fixes.

Best regards,
Krzysztof

[PATCH v2 2/6] dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets

[Val Packett]

Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings")
Signed-off-by: Val Packett <val@packett.cool>
---
 include/dt-bindings/clock/qcom,dispcc-sm6125.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/qcom,dispcc-sm6125.h b/include/dt-bindings/clock/qcom,dispcc-sm6125.h
index 4ff974f4fcc3..f58b85d2c814 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm6125.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm6125.h
@@ -6,6 +6,7 @@
 #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
 #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM6125_H
 
+/* Clocks */
 #define DISP_CC_PLL0			0
 #define DISP_CC_MDSS_AHB_CLK		1
 #define DISP_CC_MDSS_AHB_CLK_SRC	2
@@ -35,7 +36,10 @@
 #define DISP_CC_MDSS_VSYNC_CLK_SRC	26
 #define DISP_CC_XO_CLK			27
 
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR			0
+
+/* GDSCs */
 #define MDSS_GDSC			0
 
 #endif
-- 
2.52.0

Re: [PATCH v2 2/6] dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets

[Krzysztof Kozlowski]

On Sat, Feb 28, 2026 at 05:41:28PM -0300, Val Packett wrote:
> Add the missing defines for MDSS resets, which are necessary to reset
> the display subsystem in order to avoid issues caused by state left over
> from the bootloader.
> 
> While here, align comment style with other SoCs.
> 
> Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings")

Same comment, nothing wrong was in above commit and posting bindings
without reset part is not a bug.

With fixes dropped:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v2 3/6] clk: qcom: dispcc-sm6115: Add missing MDSS resets

[Val Packett]

The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Fixes: 9b518788631c ("clk: qcom: Add display clock controller driver for SM6115")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
---
 drivers/clk/qcom/dispcc-sm6115.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/dispcc-sm6115.c b/drivers/clk/qcom/dispcc-sm6115.c
index 8ae25d51db94..75bd57213079 100644
--- a/drivers/clk/qcom/dispcc-sm6115.c
+++ b/drivers/clk/qcom/dispcc-sm6115.c
@@ -22,6 +22,7 @@
 #include "clk-regmap-divider.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
 	DT_BI_TCXO,
@@ -511,6 +512,10 @@ static struct clk_branch disp_cc_sleep_clk = {
 	},
 };
 
+static const struct qcom_reset_map disp_cc_sm6115_resets[] = {
+	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
+};
+
 static struct gdsc mdss_gdsc = {
 	.gdscr = 0x3000,
 	.pd = {
@@ -561,6 +566,8 @@ static const struct qcom_cc_desc disp_cc_sm6115_desc = {
 	.config = &disp_cc_sm6115_regmap_config,
 	.clks = disp_cc_sm6115_clocks,
 	.num_clks = ARRAY_SIZE(disp_cc_sm6115_clocks),
+	.resets = disp_cc_sm6115_resets,
+	.num_resets = ARRAY_SIZE(disp_cc_sm6115_resets),
 	.gdscs = disp_cc_sm6115_gdscs,
 	.num_gdscs = ARRAY_SIZE(disp_cc_sm6115_gdscs),
 };
-- 
2.52.0

Re: [PATCH v2 3/6] clk: qcom: dispcc-sm6115: Add missing MDSS resets

[Krzysztof Kozlowski]

On Sat, Feb 28, 2026 at 05:41:29PM -0300, Val Packett wrote:
> The MDSS resets were left undescribed. Add them to allow resetting the
> display subsystem, which is necessary to avoid issues caused by state
> left over from the bootloader on various platforms.
> 
> Fixes: 9b518788631c ("clk: qcom: Add display clock controller driver for SM6115")

Not a bug being fixed here.

Best regards,
Krzysztof

[PATCH v2 4/6] clk: qcom: dispcc-sm6125: Add missing MDSS resets

[Val Packett]

The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Fixes: 6e87c8f07407 ("clk: qcom: Add display clock controller driver for SM6125")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
---
 drivers/clk/qcom/dispcc-sm6125.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/dispcc-sm6125.c b/drivers/clk/qcom/dispcc-sm6125.c
index 851d38a487d3..2c67abcfef12 100644
--- a/drivers/clk/qcom/dispcc-sm6125.c
+++ b/drivers/clk/qcom/dispcc-sm6125.c
@@ -17,6 +17,7 @@
 #include "clk-regmap.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
 	P_BI_TCXO,
@@ -607,6 +608,10 @@ static struct clk_branch disp_cc_xo_clk = {
 	},
 };
 
+static const struct qcom_reset_map disp_cc_sm6125_resets[] = {
+	[DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
+};
+
 static struct gdsc mdss_gdsc = {
 	.gdscr = 0x3000,
 	.pd = {
@@ -663,6 +668,8 @@ static const struct qcom_cc_desc disp_cc_sm6125_desc = {
 	.config = &disp_cc_sm6125_regmap_config,
 	.clks = disp_cc_sm6125_clocks,
 	.num_clks = ARRAY_SIZE(disp_cc_sm6125_clocks),
+	.resets = disp_cc_sm6125_resets,
+	.num_resets = ARRAY_SIZE(disp_cc_sm6125_resets),
 	.gdscs = disp_cc_sm6125_gdscs,
 	.num_gdscs = ARRAY_SIZE(disp_cc_sm6125_gdscs),
 };
-- 
2.52.0