From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
"kernel@esmil.dk" <kernel@esmil.dk>,
"conor@kernel.org" <conor@kernel.org>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"krzysztof.kozlowski+dt@linaro.org"
<krzysztof.kozlowski+dt@linaro.org>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"Hal Feng" <hal.feng@starfivetech.com>,
Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
Leyfoon Tan <leyfoon.tan@starfivetech.com>
Subject: RE: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
Date: Tue, 12 Dec 2023 01:07:59 +0000 [thread overview]
Message-ID: <38f6f61b9928460abd5d426a84adbb06@EXMBX066.cuchost.com> (raw)
In-Reply-To: <CAJM55Z9bik1QttBeFUCfM3N98HWURge7mgV7ohFBq+AsuvtROg@mail.gmail.com>
> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Sent: Saturday, December 9, 2023 12:40 AM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; conor@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; emil.renner.berthing@canonical.com; Hal Feng
> <hal.feng@starfivetech.com>; Xingyu Wu <xingyu.wu@starfivetech.com>
> Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Leyfoon Tan
> <leyfoon.tan@starfivetech.com>
> Subject: Re: [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes
>
> Sia Jee Heng wrote:
> > Add SYSCRG/SYSCRG-NE/SYSCRG-NW/SYSCRG-SW/AONCRG clock and reset
> > nodes for JH8100 RISC-V SoC.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > ---
> > arch/riscv/boot/dts/starfive/jh8100-clk.dtsi | 180 +++++++++++++++++++
> > arch/riscv/boot/dts/starfive/jh8100.dtsi | 115 ++++++++++++
>
> Why the split here? I mean why can't the clocks just be in the jh8100.dtsi?
The reason is that the number of fixed clocks increases when more and more
domain clocks are added. So, that is why we split out the clock file.
>
> > 2 files changed, 295 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > new file mode 100644
> > index 000000000000..27ba249f523e
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh8100-clk.dtsi
> > @@ -0,0 +1,180 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + */
> > +
> > +/ {
> > + clk_osc: clk_osc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + clk_i2srx_bclk_ext: clk_i2srx_bclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12288000>;
> > + };
> > +
> > + clk_i2srx_lrck_ext: clk_i2srx_lrck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <192000>;
> > + };
> > +
> > + clk_mclk_ext: clk_mclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <49152000>;
> > + };
> > + /* sys-ne */
> > + clk_usb3_tap_tck_ext: clk_usb3_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_glb_ext_clk: clk_glb_ext_clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <30000000>;
> > + };
> > +
> > + clk_usb1_tap_tck_ext: clk_usb1_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_usb2_tap_tck_ext: clk_usb2_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_i2s_tscko: clk_i2s_tscko {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12800000>;
> > + };
> > +
> > + clk_typec_tap_tck_ext: clk_typec_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in0_ext: clk_spi_in0_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in1_ext: clk_spi_in1_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_spi_in2_ext: clk_spi_in2_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_i2stx_bclk_ext: clk_i2stx_bclk_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12288000>;
> > + };
> > +
> > + clk_i2stx_lrck_ext: clk_i2stx_lrck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <192000>;
> > + };
> > + /* sys-nw */
> > + clk_dvp_ext: clk_dvp_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <150000000>;
> > + };
> > +
> > + clk_isp_dphy_tap_tck_ext: clk_isp_dphy_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_vout_mipi_dphy_tap_tck_ext: clk_vout_mipi_dphy_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_vout_edp_tap_tck_ext: clk_vout_edp_tap_tck_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + clk_rtc: clk_rtc {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32768>;
> > + };
> > + /* aon */
> > + clk_gmac0_rmii_func: clk_gmac0_rmii_func {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + clk_gmac0_rgmii_func: clk_gmac0_rgmii_func {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <125000000>;
> > + };
> > +
> > + clk_aon50: clk_aon50 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + clk_aon125: clk_aon125 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <125000000>;
> > + };
> > +
> > + clk_aon2000: clk_aon2000 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <2000000000>;
> > + };
> > +
> > + clk_aon200: clk_aon200 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <200000000>;
> > + };
> > +
> > + clk_aon667: clk_isp_aon667 {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <667000000>;
> > + };
> > +
> > + clk_i3c_ext: clk_i3c_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <12500000>;
> > + };
> > +
> > + clk_espi_ext: clk_espi_ext {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <60000000>;
> > + };
> > +};
> > diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > index f26aff5c1ddf..9863c61324a0 100644
> > --- a/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi
> > @@ -4,6 +4,9 @@
> > */
> >
> > /dts-v1/;
> > +#include <dt-bindings/clock/starfive,jh8100-crg.h>
> > +#include <dt-bindings/reset/starfive,jh8100-crg.h>
> > +#include "jh8100-clk.dtsi"
> >
> > / {
> > compatible = "starfive,jh8100";
> > @@ -357,6 +360,104 @@ uart4: serial@121a0000 {
> > status = "disabled";
> > };
> >
> > + syscrg_ne: syscrg_ne@12320000 {
> > + compatible = "starfive,jh8100-syscrg-ne";
> > + reg = <0x0 0x12320000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_AXI_400>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_480>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_625>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_240>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_60>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_156P25>,
> > + <&syscrg SYSCRG_CLK_USB_WRAP_312P5>,
> > + <&syscrg SYSCRG_CLK_USB_125M>,
> > + <&syscrg_nw SYSCRG_NW_CLK_GPIO_100>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT>, <&syscrg SYSCRG_CLK_MCLK>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&syscrg SYSCRG_CLK_AHB0>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER1>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER2>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER3>,
> > + <&syscrg SYSCRG_CLK_APB_BUS_PER5>,
> > + <&syscrg SYSCRG_CLK_VENC_ROOT>,
> > + <&syscrg SYSCRG_CLK_SPI_CORE_100>,
> > + <&clk_glb_ext_clk>, <&clk_usb3_tap_tck_ext>,
> > + <&clk_usb1_tap_tck_ext>, <&clk_usb2_tap_tck_ext>,
> > + <&clk_typec_tap_tck_ext>, <&clk_spi_in0_ext>,
> > + <&clk_spi_in1_ext>, <&clk_i2stx_bclk_ext>, <&clk_i2stx_lrck_ext>;
> > + clock-names = "clk_osc", "sys_clk_axi_400",
> > + "sys_clk_vout_root0", "sys_clk_vout_root1",
> > + "sys_clk_usb_wrap_480", "sys_clk_usb_wrap_625",
> > + "sys_clk_usb_wrap_240", "sys_clk_usb_wrap_60",
> > + "sys_clk_usb_wrap_156p25", "sys_clk_usb_wrap_312p5",
> > + "sys_clk_usb_125m", "sys_nw_clk_gpio_100",
> > + "sys_clk_perh_root", "sys_clk_mclk",
> > + "sys_clk_perh_root_preosc", "sys_clk_ahb0",
> > + "sys_clk_apb_bus_per1", "sys_clk_apb_bus_per2",
> > + "sys_clk_apb_bus_per3", "sys_clk_apb_bus_per5",
> > + "sys_clk_venc_root", "sys_clk_spi_core_100",
> > + "clk_glb_ext_clk", "clk_usb3_tap_tck_ext",
> > + "clk_usb1_tap_tck_ext", "clk_usb2_tap_tck_ext",
> > + "clk_typec_tap_tck_ext", "clk_spi_in0_ext",
> > + "clk_spi_in1_ext", "clk_i2stx_bclk_ext",
> > + "clk_i2stx_lrck_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg_nw: syscrg_nw@123c0000 {
> > + compatible = "starfive,jh8100-syscrg-nw";
> > + reg = <0x0 0x123c0000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_ISP_2X>, <&syscrg SYSCRG_CLK_ISP_AXI>,
> > + <&syscrg SYSCRG_CLK_VOUT_ROOT0>, <&syscrg SYSCRG_CLK_VOUT_ROOT1>,
> > + <&syscrg SYSCRG_CLK_VOUT_SCAN_ATS>,
> > + <&syscrg SYSCRG_CLK_VOUT_DC_CORE>, <&syscrg SYSCRG_CLK_VOUT_AXI>,
> > + <&syscrg SYSCRG_CLK_AXI_400>, <&syscrg SYSCRG_CLK_AXI_200>,
> > + <&syscrg SYSCRG_CLK_PERH_ROOT_PREOSC>,
> > + <&clk_dvp_ext>, <&clk_isp_dphy_tap_tck_ext>,
> > + <&clk_glb_ext_clk>, <&clk_i2s_tscko>,
> > + <&clk_vout_mipi_dphy_tap_tck_ext>, <&clk_vout_edp_tap_tck_ext>,
> > + <&clk_spi_in2_ext>;
> > + clock-names = "clk_osc", "sys_clk_apb_bus",
> > + "sys_clk_isp_2x", "sys_clk_isp_axi",
> > + "sys_clk_vout_root0", "sys_clk_vout_root1",
> > + "sys_clk_vout_scan_ats", "sys_clk_vout_dc_core",
> > + "sys_clk_vout_axi", "sys_clk_axi_400",
> > + "sys_clk_axi_200", "sys_clk_perh_root_preosc", "clk_dvp_ext",
> > + "clk_isp_dphy_tap_tck_ext", "clk_glb_ext_clk",
> > + "clk_i2s_tscko", "clk_vout_mipi_dphy_tap_tck_ext",
> > + "clk_vout_edp_tap_tck_ext", "clk_spi_in2_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg: syscrg@126d0000 {
> > + compatible = "starfive,jh8100-syscrg";
> > + reg = <0x0 0x126d0000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&clk_i2srx_bclk_ext>,
> > + <&clk_i2srx_lrck_ext>, <&clk_mclk_ext>;
> > + clock-names = "clk_osc", "clk_i2srx_bclk_ext",
> > + "clk_i2srx_lrck_ext", "clk_mclk_ext";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + syscrg_sw: syscrg_sw@12720000 {
> > + compatible = "starfive,jh8100-syscrg-sw";
> > + reg = <0x0 0x12720000 0x0 0x10000>;
> > + clocks = <&syscrg SYSCRG_CLK_APB_BUS>,
> > + <&syscrg SYSCRG_CLK_VDEC_ROOT>,
> > + <&syscrg SYSCRG_CLK_FLEXNOC1>;
> > + clock-names = "sys_clk_apb_bus",
> > + "sys_clk_vdec_root",
> > + "sys_clk_flexnoc1";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > uart5: serial@127d0000 {
> > compatible = "starfive,jh8100-uart", "cdns,uart-r1p8";
> > reg = <0x0 0x127d0000 0x0 0x10000>;
> > @@ -374,5 +475,19 @@ uart6: serial@127e0000 {
> > interrupts = <73>;
> > status = "disabled";
> > };
> > +
> > + aoncrg: aoncrg@1f310000 {
> > + compatible = "starfive,jh8100-aoncrg";
> > + reg = <0x0 0x1f310000 0x0 0x10000>;
> > + clocks = <&clk_osc>, <&clk_gmac0_rmii_func>,
> > + <&clk_gmac0_rgmii_func>, <&clk_aon125>,
> > + <&clk_aon2000>, <&clk_aon200>,
> > + <&clk_aon667>, <&clk_rtc>;
> > + clock-names = "clk_osc", "clk_gmac0_rmii_func", "clk_gmac0_rgmii_func",
> > + "clk_aon125", "clk_aon2000", "clk_aon200",
> > + "clk_aon667", "clk_rtc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > };
> > };
> > --
> > 2.34.1
> >
next prev parent reply other threads:[~2023-12-12 1:08 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 11:49 [PATCH v1 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 01/16] reset: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-08 13:12 ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-08 13:15 ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 03/16] clk: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-08 13:16 ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-08 13:24 ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Sia Jee Heng
2023-12-08 17:52 ` Krzysztof Kozlowski
2023-12-12 2:47 ` JeeHeng Sia
2023-12-12 8:43 ` Krzysztof Kozlowski
2023-12-12 10:04 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver Sia Jee Heng
2023-12-08 16:25 ` Emil Renner Berthing
2023-12-12 0:46 ` JeeHeng Sia
2023-12-13 11:56 ` Emil Renner Berthing
2023-12-19 3:02 ` JeeHeng Sia
2023-12-19 17:39 ` Emil Renner Berthing
2023-12-20 1:35 ` JeeHeng Sia
2023-12-20 1:39 ` JeeHeng Sia
2023-12-20 13:07 ` Emil Renner Berthing
2023-12-21 0:45 ` JeeHeng Sia
2023-12-13 4:20 ` JeeHeng Sia
2023-12-13 12:05 ` Emil Renner Berthing
2023-12-20 1:34 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator Sia Jee Heng
2023-12-08 16:37 ` Emil Renner Berthing
2023-12-12 1:01 ` JeeHeng Sia
2023-12-13 12:00 ` Emil Renner Berthing
2023-12-08 17:53 ` Krzysztof Kozlowski
2023-12-12 2:48 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 08/16] clk: starfive: Add JH8100 System-North-West clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 09/16] dt-bindings: clock: Add StarFive JH8100 System-North-East clock and reset generator Sia Jee Heng
2023-12-08 17:54 ` Krzysztof Kozlowski
2023-12-12 2:49 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 10/16] clk: starfive: Add JH8100 System-North-East clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 11/16] dt-bindings: clock: Add StarFive JH8100 System-South-West clock and reset generator Sia Jee Heng
2023-12-08 17:54 ` Krzysztof Kozlowski
2023-12-12 2:49 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 12/16] clk: starfive: Add JH8100 System-South-West clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Sia Jee Heng
2023-12-08 17:55 ` Krzysztof Kozlowski
2023-12-12 2:49 ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 14/16] clk: starfive: Add JH8100 Always-On clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 15/16] reset: starfive: Add StarFive JH8100 reset driver Sia Jee Heng
2023-12-06 11:50 ` [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes Sia Jee Heng
2023-12-08 16:39 ` Emil Renner Berthing
2023-12-08 17:57 ` Krzysztof Kozlowski
2023-12-12 2:51 ` JeeHeng Sia
2023-12-12 1:07 ` JeeHeng Sia [this message]
2023-12-08 17:57 ` Krzysztof Kozlowski
2023-12-12 2:58 ` JeeHeng Sia
2023-12-12 8:43 ` Krzysztof Kozlowski
2023-12-12 10:03 ` JeeHeng Sia
2023-12-08 16:52 ` [PATCH v1 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Emil Renner Berthing
2023-12-12 1:09 ` JeeHeng Sia
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