Linux clock framework development
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From: JeeHeng Sia <jeeheng.sia@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
	"kernel@esmil.dk" <kernel@esmil.dk>,
	"conor@kernel.org" <conor@kernel.org>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org"
	<krzysztof.kozlowski+dt@linaro.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
	"Hal Feng" <hal.feng@starfivetech.com>,
	Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	Leyfoon Tan <leyfoon.tan@starfivetech.com>
Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
Date: Wed, 13 Dec 2023 04:20:01 +0000	[thread overview]
Message-ID: <a554a163793e4513b25766c21ddc3f02@EXMBX066.cuchost.com> (raw)
In-Reply-To: <CAJM55Z_VgBGvCPuvwmQahMcMfuWKnOKpZ9bBbbhei_Teu5Apeg@mail.gmail.com>



> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Sent: Saturday, December 9, 2023 12:25 AM
> To: JeeHeng Sia <jeeheng.sia@starfivetech.com>; kernel@esmil.dk; conor@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; paul.walmsley@sifive.com; palmer@dabbelt.com; aou@eecs.berkeley.edu;
> mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; emil.renner.berthing@canonical.com; Hal Feng
> <hal.feng@starfivetech.com>; Xingyu Wu <xingyu.wu@starfivetech.com>
> Cc: linux-riscv@lists.infradead.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org; Leyfoon Tan
> <leyfoon.tan@starfivetech.com>
> Subject: Re: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> 
> Sia Jee Heng wrote:
> > Add support for JH8100 System clock generator.
> >
> > Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > Reviewed-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > ---
> >  MAINTAINERS                                   |   8 +
> >  drivers/clk/starfive/Kconfig                  |   9 +
> >  drivers/clk/starfive/Makefile                 |   1 +
> >  drivers/clk/starfive/clk-starfive-common.h    |   9 +-
> >  drivers/clk/starfive/jh8100/Makefile          |   3 +
> >  .../clk/starfive/jh8100/clk-starfive-jh8100.h |  11 +
> >  drivers/clk/starfive/jh8100/clk-sys.c         | 455 ++++++++++++++++++
> >  7 files changed, 495 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/starfive/jh8100/Makefile
> >  create mode 100644 drivers/clk/starfive/jh8100/clk-starfive-jh8100.h
> >  create mode 100644 drivers/clk/starfive/jh8100/clk-sys.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 788be9ab5b73..87bcb25becc1 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -20763,6 +20763,14 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> >  F:	drivers/phy/starfive/phy-jh7110-pcie.c
> >  F:	drivers/phy/starfive/phy-jh7110-usb.c
> >
> > +STARFIVE JH8100 CLOCK DRIVERS
> > +M:	Sia Jee Heng <jeeheng.sia@starfivetech.com>
> > +M:	Ley Foon Tan <leyfoon.tan@starfivetech.com>
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/clock/starfive,jh81*.yaml
> > +F:	drivers/clk/starfive/jh8100
> > +F:	include/dt-bindings/clock/starfive?jh81*.h
> > +
> >  STATIC BRANCH/CALL
> >  M:	Peter Zijlstra <peterz@infradead.org>
> >  M:	Josh Poimboeuf <jpoimboe@kernel.org>
> > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> > index ff8eace36e64..d8c7b9bb3895 100644
> > --- a/drivers/clk/starfive/Kconfig
> > +++ b/drivers/clk/starfive/Kconfig
> > @@ -72,3 +72,12 @@ config CLK_STARFIVE_JH7110_VOUT
> >  	help
> >  	  Say yes here to support the Video-Output clock controller
> >  	  on the StarFive JH7110 SoC.
[...]
> > diff --git a/drivers/clk/starfive/jh8100/Makefile b/drivers/clk/starfive/jh8100/Makefile
> > new file mode 100644
> > index 000000000000..af6a09e220d3
> > --- /dev/null
> > +++ b/drivers/clk/starfive/jh8100/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +# StarFive JH8100 Clock
> > +obj-$(CONFIG_CLK_STARFIVE_JH8100_SYS)		+= clk-sys.o
> 
> This will name the module clk-sys, which is way too generic. Please name this
> clk-starfive-jh8100-sys similar to the JH7110 drivers.
Just realized that I haven't reply to this comment.
I can't give it a longer name otherwise compiler will throw warning.
That’s why ends up to use a shorter name and keep it under jh8100 folder.
> 
[...]

  parent reply	other threads:[~2023-12-13  4:20 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-06 11:49 [PATCH v1 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 01/16] reset: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-08 13:12   ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-08 13:15   ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 03/16] clk: starfive: Rename file name "jh71x0" to "common" Sia Jee Heng
2023-12-08 13:16   ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Sia Jee Heng
2023-12-08 13:24   ` Emil Renner Berthing
2023-12-06 11:49 ` [PATCH v1 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Sia Jee Heng
2023-12-08 17:52   ` Krzysztof Kozlowski
2023-12-12  2:47     ` JeeHeng Sia
2023-12-12  8:43       ` Krzysztof Kozlowski
2023-12-12 10:04         ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver Sia Jee Heng
2023-12-08 16:25   ` Emil Renner Berthing
2023-12-12  0:46     ` JeeHeng Sia
2023-12-13 11:56       ` Emil Renner Berthing
2023-12-19  3:02         ` JeeHeng Sia
2023-12-19 17:39           ` Emil Renner Berthing
2023-12-20  1:35             ` JeeHeng Sia
2023-12-20  1:39         ` JeeHeng Sia
2023-12-20 13:07           ` Emil Renner Berthing
2023-12-21  0:45             ` JeeHeng Sia
2023-12-13  4:20     ` JeeHeng Sia [this message]
2023-12-13 12:05       ` Emil Renner Berthing
2023-12-20  1:34         ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 07/16] dt-bindings: clock: Add StarFive JH8100 System-North-West clock and reset generator Sia Jee Heng
2023-12-08 16:37   ` Emil Renner Berthing
2023-12-12  1:01     ` JeeHeng Sia
2023-12-13 12:00       ` Emil Renner Berthing
2023-12-08 17:53   ` Krzysztof Kozlowski
2023-12-12  2:48     ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 08/16] clk: starfive: Add JH8100 System-North-West clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 09/16] dt-bindings: clock: Add StarFive JH8100 System-North-East clock and reset generator Sia Jee Heng
2023-12-08 17:54   ` Krzysztof Kozlowski
2023-12-12  2:49     ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 10/16] clk: starfive: Add JH8100 System-North-East clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 11/16] dt-bindings: clock: Add StarFive JH8100 System-South-West clock and reset generator Sia Jee Heng
2023-12-08 17:54   ` Krzysztof Kozlowski
2023-12-12  2:49     ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 12/16] clk: starfive: Add JH8100 System-South-West clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Sia Jee Heng
2023-12-08 17:55   ` Krzysztof Kozlowski
2023-12-12  2:49     ` JeeHeng Sia
2023-12-06 11:49 ` [PATCH v1 14/16] clk: starfive: Add JH8100 Always-On clock generator driver Sia Jee Heng
2023-12-06 11:49 ` [PATCH v1 15/16] reset: starfive: Add StarFive JH8100 reset driver Sia Jee Heng
2023-12-06 11:50 ` [PATCH v1 16/16] riscv: dts: starfive: jh8100: Add clocks and resets nodes Sia Jee Heng
2023-12-08 16:39   ` Emil Renner Berthing
2023-12-08 17:57     ` Krzysztof Kozlowski
2023-12-12  2:51       ` JeeHeng Sia
2023-12-12  1:07     ` JeeHeng Sia
2023-12-08 17:57   ` Krzysztof Kozlowski
2023-12-12  2:58     ` JeeHeng Sia
2023-12-12  8:43       ` Krzysztof Kozlowski
2023-12-12 10:03         ` JeeHeng Sia
2023-12-08 16:52 ` [PATCH v1 00/16] Basic clock and reset support for StarFive JH8100 RISC-V SoC Emil Renner Berthing
2023-12-12  1:09   ` JeeHeng Sia

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