From: Jie Luo <jie.luo@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Luo Jie <quic_luoj@quicinc.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, quic_pavir@quicinc.com,
quic_suruchia@quicinc.com
Subject: Re: [PATCH 4/5] arm64: dts: ipq5332: Add CMN PLL node for networking hardware
Date: Thu, 4 Dec 2025 15:46:16 +0800 [thread overview]
Message-ID: <5095de61-69e8-4ef9-9604-702db46caee5@oss.qualcomm.com> (raw)
In-Reply-To: <11056c3c-452c-444e-84f2-318f9dec6831@oss.qualcomm.com>
On 12/1/2025 9:52 PM, Konrad Dybcio wrote:
> On 11/28/25 9:40 AM, Luo Jie wrote:
>> Add the CMN PLL node required for networking hardware operation on IPQ5332.
>> The CMN PLL core runs at 6 GHz on this platform, differing from others like
>> IPQ9574.
>>
>> Configure the reference clock path where XO (48 MHz or 96 MHz) routes
>> through the WiFi block's multiplier/divider to provide a stable 48 MHz
>> reference to the CMN PLL.
>> .XO (48 MHZ or 96 MHZ)-->WiFi (multiplier/divider)--> 48 MHZ to CMN PLL.
>>
>> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
>> ---
>
> [...]
>
>> + cmn_pll: clock-controller@9b000 {
>> + compatible = "qcom,ipq5332-cmn-pll";
>> + reg = <0x0009b000 0x800>;
>> + clocks = <&ref_48mhz_clk>,
>> + <&gcc GCC_CMN_12GPLL_AHB_CLK>,
>> + <&gcc GCC_CMN_12GPLL_SYS_CLK>;
>> + clock-names = "ref", "ahb", "sys";
>
> 1 a line, please
OK, Will update, thanks.>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
next prev parent reply other threads:[~2025-12-04 7:46 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-28 8:40 [PATCH 0/5] Add CMN PLL clock controller support for IPQ5332 Luo Jie
2025-11-28 8:40 ` [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider Luo Jie
2025-11-28 11:38 ` Konrad Dybcio
2025-11-28 14:29 ` Jie Luo
2025-12-01 13:42 ` Konrad Dybcio
2025-12-04 7:44 ` Jie Luo
2025-12-04 10:16 ` Konrad Dybcio
2025-11-28 8:40 ` [PATCH 2/5] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5332 SoC Luo Jie
2025-11-28 9:18 ` Rob Herring (Arm)
2025-11-28 9:39 ` Krzysztof Kozlowski
2025-11-28 8:40 ` [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support Luo Jie
2025-12-01 13:52 ` Konrad Dybcio
2025-12-04 8:09 ` Jie Luo
2025-12-04 13:48 ` Konrad Dybcio
2025-12-05 12:11 ` Jie Luo
2025-11-28 8:40 ` [PATCH 4/5] arm64: dts: ipq5332: Add CMN PLL node for networking hardware Luo Jie
2025-12-01 13:52 ` Konrad Dybcio
2025-12-04 7:46 ` Jie Luo [this message]
2025-11-28 8:40 ` [PATCH 5/5] arm64: dts: qcom: Represent xo_board as fixed-factor clock on IPQ5332 Luo Jie
2025-12-01 13:53 ` Konrad Dybcio
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