From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Luo Jie <jie.luo@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Luo Jie <quic_luoj@quicinc.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, quic_pavir@quicinc.com,
quic_suruchia@quicinc.com
Subject: Re: [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support
Date: Mon, 1 Dec 2025 14:52:06 +0100 [thread overview]
Message-ID: <6e12f446-7792-44da-9e06-99729c3b066d@oss.qualcomm.com> (raw)
In-Reply-To: <20251128-qcom_ipq5332_cmnpll-v1-3-55127ba85613@oss.qualcomm.com>
On 11/28/25 9:40 AM, Luo Jie wrote:
> The CMN PLL in IPQ5332 SoC produces different output clocks when compared
> to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch
> (50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different.
>
> Add IPQ5332-specific clock definitions and of_device_id entry.
>
> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
> ---
[...]
> +static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = {
> + CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
> + CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
> + CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
> + CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
> + CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL),
> + CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
I can't really find the source for most of these, but I see that there's both
a 200 and a 300 MHz output to NSS
Konrad
next prev parent reply other threads:[~2025-12-01 13:52 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-28 8:40 [PATCH 0/5] Add CMN PLL clock controller support for IPQ5332 Luo Jie
2025-11-28 8:40 ` [PATCH 1/5] clk: qcom: cmnpll: Account for reference clock divider Luo Jie
2025-11-28 11:38 ` Konrad Dybcio
2025-11-28 14:29 ` Jie Luo
2025-12-01 13:42 ` Konrad Dybcio
2025-12-04 7:44 ` Jie Luo
2025-12-04 10:16 ` Konrad Dybcio
2025-11-28 8:40 ` [PATCH 2/5] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5332 SoC Luo Jie
2025-11-28 9:18 ` Rob Herring (Arm)
2025-11-28 9:39 ` Krzysztof Kozlowski
2025-11-28 8:40 ` [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support Luo Jie
2025-12-01 13:52 ` Konrad Dybcio [this message]
2025-12-04 8:09 ` Jie Luo
2025-12-04 13:48 ` Konrad Dybcio
2025-12-05 12:11 ` Jie Luo
2025-11-28 8:40 ` [PATCH 4/5] arm64: dts: ipq5332: Add CMN PLL node for networking hardware Luo Jie
2025-12-01 13:52 ` Konrad Dybcio
2025-12-04 7:46 ` Jie Luo
2025-11-28 8:40 ` [PATCH 5/5] arm64: dts: qcom: Represent xo_board as fixed-factor clock on IPQ5332 Luo Jie
2025-12-01 13:53 ` Konrad Dybcio
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