Re: [PATCH 3/5] clk: qcom: cmnpll: Add IPQ5332 SoC support

[Jie Luo <jie.luo@oss.qualcomm.com>]

On 12/1/2025 9:52 PM, Konrad Dybcio wrote:
> On 11/28/25 9:40 AM, Luo Jie wrote:
>> The CMN PLL in IPQ5332 SoC produces different output clocks when compared
>> to IPQ9574. While most clock outputs match IPQ9574, the ethernet PHY/switch
>> (50 Mhz) and PPE clocks (200 Mhz) in IPQ5332 are different.
>>
>> Add IPQ5332-specific clock definitions and of_device_id entry.
>>
>> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> +static const struct cmn_pll_fixed_output_clk ipq5332_output_clks[] = {
>> +	CLK_PLL_OUTPUT(IPQ5332_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
>> +	CLK_PLL_OUTPUT(IPQ5332_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
>> +	CLK_PLL_OUTPUT(IPQ5332_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
>> +	CLK_PLL_OUTPUT(IPQ5332_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
>> +	CLK_PLL_OUTPUT(IPQ5332_PPE_200MHZ_CLK, "ppe-200mhz", 200000000UL),
>> +	CLK_PLL_OUTPUT(IPQ5332_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
> 
> I can't really find the source for most of these, but I see that there's both
> a 200 and a 300 MHz output to NSS
> 
> Konrad

Both IPQ5332_XO_24MHZ_CLK and IPQ5332_SLEEP_32KHZ_CLK are intended to be
used as the input clocks to the GCC block. IPQ5332_PCS_31P25MHZ_CLK
provides the reference clock for the Ethernet PCS, and
IPQ5332_ETH_50MHZ_CLK is the source clock for the PCS PLL on IPQ5332.
On this platform the Ethernet clocking path is:
CMN PLL ETH 50 MHz output → PCS PLL (divider + gate) → attached PHY or
switch.