Re: (subset) [PATCH v5 00/18] clk: qcom: Add support to attach multiple power domains in cc probe

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 12/06/2025 12:03, Jagadeesh Kona wrote:
> 
> 
> On 6/12/2025 9:30 AM, Bjorn Andersson wrote:
>>
>> On Fri, 30 May 2025 18:50:45 +0530, Jagadeesh Kona wrote:
>>> In recent QCOM chipsets, PLLs require more than one power domain to be
>>> kept ON to configure the PLL. But the current code doesn't enable all
>>> the required power domains while configuring the PLLs, this leads to
>>> functional issues due to suboptimal settings of PLLs.
>>>
>>> To address this, add support for handling runtime power management,
>>> configuring plls and enabling critical clocks from qcom_cc_really_probe.
>>> The clock controller can specify PLLs, critical clocks, and runtime PM
>>> requirements using the descriptor data. The code in qcom_cc_really_probe()
>>> ensures all necessary power domains are enabled before configuring PLLs
>>> or critical clocks.
>>>
>>> [...]
>>
>> Applied, thanks!
>>
>> [01/18] dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
>>         commit: 1a42f4d4bb92ea961c58599bac837fb8b377a296
>> [02/18] dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
>>         commit: a02a8f8cb7f6f54b077a6f9eb74ccd840b472416
>> [03/18] dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
>>         commit: 842fa748291553d2f56410034991d0eb36b70900
>> [04/18] clk: qcom: clk-alpha-pll: Add support for common PLL configuration function
>>         commit: 0f698c16358ef300ed28a608368b89a4f6a8623a
>> [05/18] clk: qcom: common: Handle runtime power management in qcom_cc_really_probe
>>         commit: c0b6627369bcfec151ccbd091f9ff1cadb1d40c1
>> [06/18] clk: qcom: common: Add support to configure clk regs in qcom_cc_really_probe
>>         commit: 452ae64997dd1db1fe9bec2e7bd65b33338e7a6b
>> [07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe
>>         commit: 512af5bf312efe09698de0870e99c0cec4d13e21
>> [08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe
>>         commit: a9dc2cc7279a1967f37192a2f954e7111bfa61b7
>> [09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe
>>         commit: eb65d754eb5eaeab7db87ce7e64dab27b7d156d8
>> [10/18] clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
>>         commit: adb50c762f3a513a363d91722dbd8d1b4afc5f10
>> [11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe
>>         commit: 3f8dd231e60b706fc9395edbf0186b7a0756f45d
>> [12/18] clk: qcom: camcc-x1e80100: Move PLL & clk configuration to really probe
>>         commit: d7eddaf0ed07e79ffdfd20acb2f6f2ca53e7851b
>>
>> Best regards,
> 
> 
> Hi Bjorn,
> 
> Thanks for picking these patches. However, the dt-bindings patches are closely linked with
> the DT patches in this series and needs to be picked together. The dt-bindings changes adds

DT bindings are the DT patches. What do you mean by DT? DTS? If so, then
you introduce regressions without explaining this at all in cover letter
or patches.

> multiple power domains support for clock controllers, and without the corresponding DT
> patches, dtbs_check will give warnings.
> 
> Can you please help to pick DT patches as well?

Please read soc maintainer profile explaining how DTS is being organized.


Best regards,
Krzysztof