Re: [PATCH v5 08/18] clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe

[Bryan O'Donoghue <bod.linux@nxsw.ie>]

On 30/05/2025 14:20, Jagadeesh Kona wrote:
> Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON
> to configure the PLLs properly. Hence move runtime power management, PLL
> configuration and enable critical clocks to qcom_cc_really_probe() which
> ensures all required power domains are in enabled state before configuring
> the PLLs or enabling the clocks.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
> ---
>   drivers/clk/qcom/videocc-sm8550.c | 66 +++++++++++++++++++--------------------
>   1 file changed, 33 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/clk/qcom/videocc-sm8550.c b/drivers/clk/qcom/videocc-sm8550.c
> index fcfe0cade6d0a95e749aabbc2af1174e5a70f0db..3e5891b43ee404edc6c99bbf8f2583cb44df9e37 100644
> --- a/drivers/clk/qcom/videocc-sm8550.c
> +++ b/drivers/clk/qcom/videocc-sm8550.c
> @@ -7,7 +7,6 @@
>   #include <linux/mod_devicetable.h>
>   #include <linux/module.h>
>   #include <linux/platform_device.h>
> -#include <linux/pm_runtime.h>
>   #include <linux/regmap.h>
> 
>   #include <dt-bindings/clock/qcom,sm8650-videocc.h>
> @@ -51,6 +50,7 @@ static struct alpha_pll_config video_cc_pll0_config = {
> 
>   static struct clk_alpha_pll video_cc_pll0 = {
>   	.offset = 0x0,
> +	.config = &video_cc_pll0_config,
>   	.vco_table = lucid_ole_vco,
>   	.num_vco = ARRAY_SIZE(lucid_ole_vco),
>   	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -82,6 +82,7 @@ static struct alpha_pll_config video_cc_pll1_config = {
> 
>   static struct clk_alpha_pll video_cc_pll1 = {
>   	.offset = 0x1000,
> +	.config = &video_cc_pll1_config,
>   	.vco_table = lucid_ole_vco,
>   	.num_vco = ARRAY_SIZE(lucid_ole_vco),
>   	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
> @@ -511,6 +512,23 @@ static const struct qcom_reset_map video_cc_sm8550_resets[] = {
>   	[VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 },
>   };
> 
> +static struct clk_alpha_pll *video_cc_sm8550_plls[] = {
> +	&video_cc_pll0,
> +	&video_cc_pll1,
> +};
> +
> +static u32 video_cc_sm8550_critical_cbcrs[] = {
> +	0x80f4, /* VIDEO_CC_AHB_CLK */
> +	0x8124, /* VIDEO_CC_XO_CLK */
> +	0x8140, /* VIDEO_CC_SLEEP_CLK */
> +};
> +
> +static u32 video_cc_sm8650_critical_cbcrs[] = {
> +	0x80f4, /* VIDEO_CC_AHB_CLK */
> +	0x8124, /* VIDEO_CC_XO_CLK */
> +	0x8150, /* VIDEO_CC_SLEEP_CLK */
> +};
> +
>   static const struct regmap_config video_cc_sm8550_regmap_config = {
>   	.reg_bits = 32,
>   	.reg_stride = 4,
> @@ -519,6 +537,13 @@ static const struct regmap_config video_cc_sm8550_regmap_config = {
>   	.fast_io = true,
>   };
> 
> +static struct qcom_cc_driver_data video_cc_sm8550_driver_data = {
> +	.alpha_plls = video_cc_sm8550_plls,
> +	.num_alpha_plls = ARRAY_SIZE(video_cc_sm8550_plls),
> +	.clk_cbcrs = video_cc_sm8550_critical_cbcrs,
> +	.num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8550_critical_cbcrs),
> +};
> +
>   static const struct qcom_cc_desc video_cc_sm8550_desc = {
>   	.config = &video_cc_sm8550_regmap_config,
>   	.clks = video_cc_sm8550_clocks,
> @@ -527,6 +552,8 @@ static const struct qcom_cc_desc video_cc_sm8550_desc = {
>   	.num_resets = ARRAY_SIZE(video_cc_sm8550_resets),
>   	.gdscs = video_cc_sm8550_gdscs,
>   	.num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs),
> +	.use_rpm = true,
> +	.driver_data = &video_cc_sm8550_driver_data,
>   };
> 
>   static const struct of_device_id video_cc_sm8550_match_table[] = {
> @@ -538,26 +565,7 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8550_match_table);
> 
>   static int video_cc_sm8550_probe(struct platform_device *pdev)
>   {
> -	struct regmap *regmap;
> -	int ret;
> -	u32 sleep_clk_offset = 0x8140;
> -
> -	ret = devm_pm_runtime_enable(&pdev->dev);
> -	if (ret)
> -		return ret;
> -
> -	ret = pm_runtime_resume_and_get(&pdev->dev);
> -	if (ret)
> -		return ret;
> -
> -	regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc);
> -	if (IS_ERR(regmap)) {
> -		pm_runtime_put(&pdev->dev);
> -		return PTR_ERR(regmap);
> -	}
> -
>   	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
> -		sleep_clk_offset = 0x8150;
>   		video_cc_pll0_config.l = 0x1e;
>   		video_cc_pll0_config.alpha = 0xa000;
>   		video_cc_pll1_config.l = 0x2b;
> @@ -569,21 +577,13 @@ static int video_cc_sm8550_probe(struct platform_device *pdev)
>   		video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
>   		video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
>   		video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
> -	}
> -
> -	clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
> -	clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
> 
> -	/* Keep some clocks always-on */
> -	qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */
> -	qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */
> -	qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */
> -
> -	ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap);
> -
> -	pm_runtime_put(&pdev->dev);
> +		video_cc_sm8550_driver_data.clk_cbcrs = video_cc_sm8650_critical_cbcrs;
> +		video_cc_sm8550_driver_data.num_clk_cbcrs =
> +							ARRAY_SIZE(video_cc_sm8650_critical_cbcrs);
> +	}
> 
> -	return ret;
> +	return qcom_cc_probe(pdev, &video_cc_sm8550_desc);
>   }
> 
>   static struct platform_driver video_cc_sm8550_driver = {
> 
> --
> 2.34.1
> 
> 
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>