From: Dave Jiang <dave.jiang@intel.com>
To: Gregory Price <gourry@gourry.net>,
Jonathan Cameron <jonathan.cameron@huawei.com>
Cc: Robert Richter <rrichter@amd.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v3 08/11] cxl/region: Implement endpoint decoder address translation
Date: Wed, 17 Sep 2025 13:57:59 -0700 [thread overview]
Message-ID: <10d3ed8d-7688-4ced-841a-ce4e6d0b7f31@intel.com> (raw)
In-Reply-To: <aMsfWfwMhewTjHD3@gourry-fedora-PF4VCD3F>
On 9/17/25 1:51 PM, Gregory Price wrote:
> On Mon, Sep 15, 2025 at 11:46:14AM +0100, Jonathan Cameron wrote:
>>> + /*
>>> + * Since translated addresses include the interleaving
>>> + * offsets, align the range to 256 MB.
>>
>> So we pass in an HPA range without interleaving offsets and get back
>> one with them? Is that unavoidable, or can we potentially push
>> this bit into the callback? Probably with separate callbacks to
>> get the interleave details.
>>
>> Overall I'm not really following what is going on here. Maybe
>> some ascii art would help?
>>
>
> The endpoints in this case are encoded with "normalized" (base-0) with
> a size of only the memory they provide. As a result, the decoder
> interleave settings will always be passthrough (iw=1, ig=ignored).
>
> This chunk translates the normalized address region to the relevant SPA
> region, and translates the IW/IG to what it actually is (i.e. what it
> *would have* been on a "normal" system).
>
> Took me a while when i originally reviewed and tested this set.
>
> Example - this is how you'd expect a real system supported by this code
> to be programmed:
>
> region {
> .start = 0x20000000
> .end = 0x3fffffff
> .iw = 2
> .ig = 256
> }
>
> endpoint1_decoder {
> .start = 0x0
> .end = 0xfffffff
> .iw = 1
> .ig = 256
> }
>
> endpoint2_decoder {
> .start = 0x0
> .end = 0xfffffff
> .iw = 1
> .ig = 256
> }
>
> when you do the translation from either decoder's hpa start/end,
> you want the following output:
>
> range {
> .start = 0x20000000
> .end = 0x3fffffff
> .iw = 2
> .ig = 256
> }
>
> If you assume a "normal" system - this is the settings the decoders
> would have been programmed with in the first place.
>
> You have to do the alignment because the translation function (may)
> only work on granularity alignment.
>
> Example:
> endpoint1->to_hpa(0) => 0x0
> endpoint1->to_hpa(0xfffffff) => 0xffffe00
> endpoint2->to_hpa(0) => 0x100
> endpoint2->to_hpa(0xfffffff) => 0xfffff00
>
> So this code applies the appropriate alignment and returns the
> translated iw/ig for use elsewhere in the stack when validating the rest
> of the decoders.
Having this explanation added to the Conventions document would be good to have.
>
> (haven't gotten to later commits, but iirc it was eventually used)
>
> ~Gregory
>
>>> + */
>>> + range.start = ALIGN_DOWN(range.start, SZ_256M);
>>> + range.end = ALIGN(range.end, SZ_256M) - 1;
>>> +
>>> + spa_len = range_len(&range);
>>> + if (!len || !spa_len || spa_len % len) {
>>> + dev_warn(&port->dev,
>>> + "CXL address translation: HPA range not contiguous: %#llx-%#llx:%#llx-%#llx(%s)\n",
>>> + range.start, range.end, ctx->hpa_range.start,
>>> + ctx->hpa_range.end, dev_name(&cxld->dev));
>>> + return -ENXIO;
>>> + }
>>> +
>>> + ways = spa_len / len;
>>> + gran = SZ_256;
>>> +
next prev parent reply other threads:[~2025-09-17 20:58 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 14:45 [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-09-12 14:45 ` [PATCH v3 01/11] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-09-12 15:52 ` Dave Jiang
2025-09-15 10:14 ` Jonathan Cameron
2025-09-17 19:56 ` Gregory Price
2025-09-23 21:40 ` Alison Schofield
2025-09-26 17:52 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 02/11] cxl/region: Store HPA range " Robert Richter
2025-09-12 17:17 ` Dave Jiang
2025-09-15 7:19 ` Robert Richter
2025-09-15 16:24 ` Dave Jiang
2025-09-15 10:23 ` Jonathan Cameron
2025-09-17 8:15 ` Robert Richter
2025-09-17 19:58 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 03/11] cxl/region: Rename misleading variable name @hpa to @range Robert Richter
2025-09-12 17:33 ` Dave Jiang
2025-09-15 7:27 ` Robert Richter
2025-09-15 10:25 ` Jonathan Cameron
2025-09-17 8:10 ` Robert Richter
2025-09-17 20:01 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 04/11] cxl/region: Add @range argument to function cxl_find_root_decoder() Robert Richter
2025-09-17 20:05 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 05/11] cxl/region: Add @range argument to function cxl_calc_interleave_pos() Robert Richter
2025-09-17 20:09 ` Gregory Price
2025-09-23 21:52 ` Alison Schofield
2025-09-26 18:22 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 06/11] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-09-12 21:10 ` Dave Jiang
2025-09-15 7:31 ` Robert Richter
2025-09-15 16:26 ` Dave Jiang
2025-09-17 20:15 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 07/11] cxl: Introduce callback to translate a decoder's HPA to the next parent port Robert Richter
2025-09-12 21:21 ` Dave Jiang
2025-09-15 7:55 ` Robert Richter
2025-09-15 16:32 ` Dave Jiang
2025-09-15 20:22 ` Dave Jiang
2025-09-17 8:20 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 08/11] cxl/region: Implement endpoint decoder address translation Robert Richter
2025-09-15 10:46 ` Jonathan Cameron
2025-09-15 16:35 ` Dave Jiang
2025-09-17 9:04 ` Robert Richter
2025-09-17 20:51 ` Gregory Price
2025-09-17 20:57 ` Dave Jiang [this message]
2025-09-18 13:59 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 09/11] cxl/region: Lock decoders that need " Robert Richter
2025-09-17 20:52 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 10/11] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-09-17 20:54 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 11/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-09-12 23:46 ` Dave Jiang
2025-09-15 8:34 ` Robert Richter
2025-09-15 10:59 ` Jonathan Cameron
2025-09-17 9:43 ` Robert Richter
2025-09-17 13:50 ` Jonathan Cameron
2025-09-17 21:01 ` Dave Jiang
2025-09-24 17:09 ` Gregory Price
2025-09-26 16:59 ` Robert Richter
2025-09-27 1:44 ` Gregory Price
2025-09-29 12:39 ` Robert Richter
2025-09-12 15:45 ` [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Dave Jiang
2025-09-15 8:42 ` Robert Richter
2025-09-23 3:26 ` Gregory Price
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