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From: Dave Jiang <dave.jiang@intel.com>
To: Robert Richter <rrichter@amd.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	Davidlohr Bueso <dave@stgolabs.net>
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
	Gregory Price <gourry@gourry.net>,
	"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
	Terry Bowman <terry.bowman@amd.com>,
	Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v3 06/11] cxl/region: Separate region parameter setup and region construction
Date: Fri, 12 Sep 2025 14:10:06 -0700	[thread overview]
Message-ID: <3d44af04-f7d6-4625-b07d-40173bc95c35@intel.com> (raw)
In-Reply-To: <20250912144514.526441-7-rrichter@amd.com>



On 9/12/25 7:45 AM, Robert Richter wrote:
> To construct a region, the region parameters such as address range and
> interleaving config need to be determined. This is done while
> constructing the region by inspecting the endpoint decoder
> configuration. The endpoint decoder is passed as a function argument.
> 
> With address translation the endpoint decoder data is no longer
> sufficient to extract the region parameters as some of the information
> is obtained using other methods such as using firmware calls.
> 
> In a first step, separate code to determine and setup the region
> parameters from the region construction. Temporarily store all the
> data to create the region in the new struct cxl_region_context. Add a
> new function setup_region_parameters() to fill that struct and later
> use it to construct the region. This simplifies the extension of the
> function to support other methods needed, esp. to support address
> translation.
> 
> Patch is a prerequisite to implement address translation.
> 
> Signed-off-by: Robert Richter <rrichter@amd.com>
> ---
>  drivers/cxl/core/region.c | 50 +++++++++++++++++++++++++++++----------
>  1 file changed, 38 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 106692f1e310..57697504410b 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -3414,6 +3414,26 @@ static int match_region_by_range(struct device *dev, const void *data)
>  	return 0;
>  }
>  
> +struct cxl_region_context {
> +	struct cxl_endpoint_decoder *cxled;
> +	struct cxl_memdev *cxlmd;
> +	struct range hpa_range;
> +	int interleave_ways;
> +	int interleave_granularity;
> +};
> +
> +static int setup_region_params(struct cxl_endpoint_decoder *cxled,
> +			       struct cxl_region_context *ctx)
> +{
> +	ctx->cxled = cxled;
> +	ctx->cxlmd = cxled_to_memdev(cxled);
> +	ctx->hpa_range = cxled->cxld.hpa_range;
> +	ctx->interleave_ways = cxled->cxld.interleave_ways;
> +	ctx->interleave_granularity = cxled->cxld.interleave_granularity;

You can init like this:

	*ctx = (struct cxl_region_context) {
		.cxled = cxled,
		.cxlmd = cxled_to_memdev(cxled),
		.hpa_range = cxled->cxld.hpa_range,
		.interleave_ways = cxled->cxld.interleave_ways,
		.interleave_granularity = cxled->cxld.interleave_granularity,
	};


> +
> +	return 0;

Can probably make this function void if no expected errors and only assignments.

DJ

> +}
> +
>  static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
>  					    struct resource *res)
>  {
> @@ -3453,11 +3473,12 @@ static int cxl_extended_linear_cache_resize(struct cxl_region *cxlr,
>  }
>  
>  static int __construct_region(struct cxl_region *cxlr,
> -			      struct cxl_endpoint_decoder *cxled)
> +			      struct cxl_region_context *ctx)
>  {
> +	struct cxl_endpoint_decoder *cxled = ctx->cxled;
>  	struct cxl_root_decoder *cxlrd = cxlr->cxlrd;
> -	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> -	struct range *range = &cxled->cxld.hpa_range;
> +	struct cxl_memdev *cxlmd = ctx->cxlmd;
> +	struct range *range = &ctx->hpa_range;
>  	struct cxl_region_params *p;
>  	struct resource *res;
>  	int rc;
> @@ -3506,8 +3527,8 @@ static int __construct_region(struct cxl_region *cxlr,
>  	}
>  
>  	p->res = res;
> -	p->interleave_ways = cxled->cxld.interleave_ways;
> -	p->interleave_granularity = cxled->cxld.interleave_granularity;
> +	p->interleave_ways = ctx->interleave_ways;
> +	p->interleave_granularity = ctx->interleave_granularity;
>  	p->state = CXL_CONFIG_INTERLEAVE_ACTIVE;
>  
>  	rc = sysfs_update_group(&cxlr->dev.kobj, get_cxl_region_target_group());
> @@ -3527,9 +3548,10 @@ static int __construct_region(struct cxl_region *cxlr,
>  
>  /* Establish an empty region covering the given HPA range */
>  static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
> -					   struct cxl_endpoint_decoder *cxled)
> +					   struct cxl_region_context *ctx)
>  {
> -	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);
> +	struct cxl_endpoint_decoder *cxled = ctx->cxled;
> +	struct cxl_memdev *cxlmd = ctx->cxlmd;
>  	struct cxl_port *port = cxlrd_to_port(cxlrd);
>  	struct cxl_dev_state *cxlds = cxlmd->cxlds;
>  	int rc, part = READ_ONCE(cxled->part);
> @@ -3548,7 +3570,7 @@ static struct cxl_region *construct_region(struct cxl_root_decoder *cxlrd,
>  		return cxlr;
>  	}
>  
> -	rc = __construct_region(cxlr, cxled);
> +	rc = __construct_region(cxlr, ctx);
>  	if (rc) {
>  		devm_release_action(port->uport_dev, unregister_region, cxlr);
>  		return ERR_PTR(rc);
> @@ -3572,13 +3594,17 @@ cxl_find_region_by_range(struct cxl_root_decoder *cxlrd, struct range *range)
>  
>  int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
>  {
> -	struct range *range = &cxled->cxld.hpa_range;
> +	struct cxl_region_context ctx;
>  	struct cxl_region_params *p;
>  	bool attach = false;
>  	int rc;
>  
> +	rc = setup_region_params(cxled, &ctx);
> +	if (rc)
> +		return rc;
> +
>  	struct cxl_root_decoder *cxlrd __free(put_cxl_root_decoder) =
> -		cxl_find_root_decoder(cxled, range);
> +		cxl_find_root_decoder(cxled, &ctx.hpa_range);
>  	if (!cxlrd)
>  		return -ENXIO;
>  
> @@ -3589,9 +3615,9 @@ int cxl_add_to_region(struct cxl_endpoint_decoder *cxled)
>  	 */
>  	mutex_lock(&cxlrd->range_lock);
>  	struct cxl_region *cxlr __free(put_cxl_region) =
> -		cxl_find_region_by_range(cxlrd, range);
> +		cxl_find_region_by_range(cxlrd, &ctx.hpa_range);
>  	if (!cxlr)
> -		cxlr = construct_region(cxlrd, cxled);
> +		cxlr = construct_region(cxlrd, &ctx);
>  	mutex_unlock(&cxlrd->range_lock);
>  
>  	rc = PTR_ERR_OR_ZERO(cxlr);


  reply	other threads:[~2025-09-12 21:10 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-12 14:45 [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-09-12 14:45 ` [PATCH v3 01/11] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-09-12 15:52   ` Dave Jiang
2025-09-15 10:14     ` Jonathan Cameron
2025-09-17 19:56   ` Gregory Price
2025-09-23 21:40   ` Alison Schofield
2025-09-26 17:52     ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 02/11] cxl/region: Store HPA range " Robert Richter
2025-09-12 17:17   ` Dave Jiang
2025-09-15  7:19     ` Robert Richter
2025-09-15 16:24       ` Dave Jiang
2025-09-15 10:23   ` Jonathan Cameron
2025-09-17  8:15     ` Robert Richter
2025-09-17 19:58   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 03/11] cxl/region: Rename misleading variable name @hpa to @range Robert Richter
2025-09-12 17:33   ` Dave Jiang
2025-09-15  7:27     ` Robert Richter
2025-09-15 10:25       ` Jonathan Cameron
2025-09-17  8:10         ` Robert Richter
2025-09-17 20:01   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 04/11] cxl/region: Add @range argument to function cxl_find_root_decoder() Robert Richter
2025-09-17 20:05   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 05/11] cxl/region: Add @range argument to function cxl_calc_interleave_pos() Robert Richter
2025-09-17 20:09   ` Gregory Price
2025-09-23 21:52   ` Alison Schofield
2025-09-26 18:22     ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 06/11] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-09-12 21:10   ` Dave Jiang [this message]
2025-09-15  7:31     ` Robert Richter
2025-09-15 16:26       ` Dave Jiang
2025-09-17 20:15   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 07/11] cxl: Introduce callback to translate a decoder's HPA to the next parent port Robert Richter
2025-09-12 21:21   ` Dave Jiang
2025-09-15  7:55     ` Robert Richter
2025-09-15 16:32       ` Dave Jiang
2025-09-15 20:22   ` Dave Jiang
2025-09-17  8:20     ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 08/11] cxl/region: Implement endpoint decoder address translation Robert Richter
2025-09-15 10:46   ` Jonathan Cameron
2025-09-15 16:35     ` Dave Jiang
2025-09-17  9:04     ` Robert Richter
2025-09-17 20:51     ` Gregory Price
2025-09-17 20:57       ` Dave Jiang
2025-09-18 13:59       ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 09/11] cxl/region: Lock decoders that need " Robert Richter
2025-09-17 20:52   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 10/11] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-09-17 20:54   ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 11/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-09-12 23:46   ` Dave Jiang
2025-09-15  8:34     ` Robert Richter
2025-09-15 10:59   ` Jonathan Cameron
2025-09-17  9:43     ` Robert Richter
2025-09-17 13:50       ` Jonathan Cameron
2025-09-17 21:01   ` Dave Jiang
2025-09-24 17:09   ` Gregory Price
2025-09-26 16:59     ` Robert Richter
2025-09-27  1:44       ` Gregory Price
2025-09-29 12:39         ` Robert Richter
2025-09-12 15:45 ` [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Dave Jiang
2025-09-15  8:42   ` Robert Richter
2025-09-23  3:26 ` Gregory Price

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