From: Yanfei Xu <yanfei.xu@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <alison.schofield@intel.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<ming4.li@intel.com>
Subject: Re: [v2 1/4] cxl/pci: Fix to record only non-zero ranges
Date: Sat, 10 Aug 2024 16:10:51 +0800 [thread overview]
Message-ID: <1e535e17-0e3e-40d5-bafb-58babbcb23ed@intel.com> (raw)
In-Reply-To: <66b66634acec6_25752945e@dwillia2-xfh.jf.intel.com.notmuch>
On 8/10/2024 2:55 AM, Dan Williams wrote:
> Yanfei Xu wrote:
>> The function cxl_dvsec_rr_decode() retrieves and records DVSEC
>> ranges into info->dvsec_range[], regardless of whether it is
>> non-zero range, and the variable info->ranges indicates the number
>> of non-zero ranges. However, in cxl_hdm_decode_init(), the validation
>> for info->dvsec_range[] occurs in a for loop that iterates based
>> on info->ranges. It may result in zero range to be validated but
>> non-zero range not be validated, in turn, the number of allowed
>> ranges is to be 0. Address it by only record non-zero ranges.
>
> When applying this should mention the potential impact of the change,
> something like:
>
> "This fix is not urgent as it requires a configuration that zeroes out
> the first dvsec range while populating the second. This has not been
> observed, but it is theoretically possible. If this gets picked up for
> -stable, no harm done, but there is no urgency to backport."
Thanks, Will add in v3.
Yanfei
next prev parent reply other threads:[~2024-08-10 8:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 9:34 [v2 0/4] Fixes for hdm docoder initialization from DVSEC ranges Yanfei Xu
2024-08-09 9:34 ` [v2 1/4] cxl/pci: Fix to record only non-zero ranges Yanfei Xu
2024-08-09 18:55 ` Dan Williams
2024-08-10 8:10 ` Yanfei Xu [this message]
2024-08-09 9:34 ` [v2 2/4] cxl/pci: Don't set up decoders for disallowed DVSEC ranges Yanfei Xu
2024-08-09 19:02 ` Dan Williams
2024-08-10 11:36 ` Yanfei Xu
2024-08-09 9:34 ` [v2 3/4] cxl/pci: Check Mem_info_valid bit for each applicable DVSEC range Yanfei Xu
2024-08-09 19:13 ` Dan Williams
2024-08-10 11:50 ` Yanfei Xu
2024-08-09 9:34 ` [v2 4/4] cxl/pci: Simplify the code logic of cxl_hdm_decode_init Yanfei Xu
2024-08-09 19:15 ` Dan Williams
2024-08-10 12:11 ` Yanfei Xu
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