From: Yanfei Xu <yanfei.xu@intel.com>
To: linux-cxl@vger.kernel.org
Cc: dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com, ming4.li@intel.com,
yanfei.xu@intel.com
Subject: [v2 0/4] Fixes for hdm docoder initialization from DVSEC ranges
Date: Fri, 9 Aug 2024 17:34:38 +0800 [thread overview]
Message-ID: <20240809093442.646545-1-yanfei.xu@intel.com> (raw)
The first three patches are functional fixes, the fourth one is for adjustment
of code format.
v1:https://lore.kernel.org/linux-cxl/66b4db4ff3730_c144829418@dwillia2-xfh.jf.intel.com.notmuch/T/#t
v1->v2:
separate one big patch into four.
Yanfei Xu (4):
cxl/pci: Fix to record only non-zero ranges
cxl/pci: Don't set up decoders for disallowed DVSEC ranges
cxl/pci: Check Mem_info_valid bit for each applicable DVSEC range
cxl/pci: Simplify the code logic of cxl_hdm_decode_init
drivers/cxl/core/pci.c | 114 ++++++++++++----------------------
drivers/cxl/cxl.h | 2 +-
drivers/cxl/port.c | 2 +-
tools/testing/cxl/test/mock.c | 4 +-
4 files changed, 42 insertions(+), 80 deletions(-)
--
2.39.2
next reply other threads:[~2024-08-09 9:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 9:34 Yanfei Xu [this message]
2024-08-09 9:34 ` [v2 1/4] cxl/pci: Fix to record only non-zero ranges Yanfei Xu
2024-08-09 18:55 ` Dan Williams
2024-08-10 8:10 ` Yanfei Xu
2024-08-09 9:34 ` [v2 2/4] cxl/pci: Don't set up decoders for disallowed DVSEC ranges Yanfei Xu
2024-08-09 19:02 ` Dan Williams
2024-08-10 11:36 ` Yanfei Xu
2024-08-09 9:34 ` [v2 3/4] cxl/pci: Check Mem_info_valid bit for each applicable DVSEC range Yanfei Xu
2024-08-09 19:13 ` Dan Williams
2024-08-10 11:50 ` Yanfei Xu
2024-08-09 9:34 ` [v2 4/4] cxl/pci: Simplify the code logic of cxl_hdm_decode_init Yanfei Xu
2024-08-09 19:15 ` Dan Williams
2024-08-10 12:11 ` Yanfei Xu
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