Re: [v2 3/4] cxl/pci: Check Mem_info_valid bit for each applicable DVSEC range

[Yanfei Xu <yanfei.xu@intel.com>]

On 8/10/2024 3:13 AM, Dan Williams wrote:
> Yanfei Xu wrote:
>> The right way is to checking Mem_info_valid bit for each applicable
>> DVSEC range against HDM_COUNT, not only for the DVSEC range 1. Also
>> the functions to check the Mem_info_valid bit are repeatedly
>> implemented, drop the rough one.
> 
> Again, not a fix, as there is no evidence of a device in the wild that
> initializes memory_info_valid of range1 on a different timescale than
> range2.
> 
> A better description of this patch is something like:
> 
> "commit ce17ad0d5498 ("cxl: Wait Memory_Info_Valid before access memory
> related info") added another implementation of waiting for
> memory_info_valid without realizing it duplicated wait_for_valid()"
> 
> ...I would also *only* do that cleanup and save changing the logic about
> when it is called to a separate patch. Neither of those would be marked
> as a fix because it depends on odd device behavior for it to be a
> problem in practice.

OK. Will split this patch into two and drop the "Fixes"

Thanks,
Yanfei