From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <ira.weiny@intel.com>,
<navneet.singh@intel.com>
Subject: Re: [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time
Date: Tue, 6 Jun 2023 13:36:51 +0100 [thread overview]
Message-ID: <20230606133651.00004f8d@Huawei.com> (raw)
In-Reply-To: <168592153599.1948938.3754212703217628741.stgit@dwillia2-xfh.jf.intel.com>
On Sun, 04 Jun 2023 16:32:16 -0700
Dan Williams <dan.j.williams@intel.com> wrote:
> Switch-level (mid-level) decoders between the platform root and an
> endpoint can dynamically switch modes between HDM-H and HDM-D[B]
> depending on which region they target. Use the region type to fixup each
> decoder that gets allocated to map the given region.
>
> Note that endpoint decoders are meant to determine the region type, so
> warn if those ever need to be fixed up, but since it is possible to
> continue do so.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> drivers/cxl/core/region.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index dca94c458b8f..c7170d92f47f 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -809,6 +809,18 @@ static int cxl_rr_alloc_decoder(struct cxl_port *port, struct cxl_region *cxlr,
> return -EBUSY;
> }
>
> + /*
> + * Endpoints should already match the region type, but backstop that
> + * assumption with an assertion. Switch-decoders change mapping-type
> + * based on what is mapped when they are assigned to a region.
> + */
> + dev_WARN_ONCE(&cxlr->dev,
> + port == cxled_to_port(cxled) &&
> + cxld->target_type != cxlr->type,
> + "%s:%s mismatch decoder type %d -> %d\n",
> + dev_name(&cxled_to_memdev(cxled)->dev),
> + dev_name(&cxld->dev), cxld->target_type, cxlr->type);
> + cxld->target_type = cxlr->type;
> cxl_rr->decoder = cxld;
> return 0;
> }
>
next prev parent reply other threads:[~2023-06-06 12:36 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-04 23:31 [PATCH 00/19] cxl: Device memory setup Dan Williams
2023-06-04 23:31 ` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-05 8:46 ` Jonathan Cameron
2023-06-13 22:03 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-06 10:53 ` Jonathan Cameron
2023-06-13 22:08 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-06 11:10 ` Jonathan Cameron
2023-06-14 0:45 ` Dan Williams
2023-06-13 22:15 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-06 11:15 ` Jonathan Cameron
2023-06-13 20:53 ` Dan Williams
2023-06-04 23:32 ` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM} Dan Williams
2023-06-06 11:21 ` Jonathan Cameron
2023-06-13 21:03 ` Dan Williams
2023-06-04 23:32 ` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-06 11:27 ` Jonathan Cameron
2023-06-13 21:23 ` Dan Williams
2023-06-13 22:32 ` Dan Williams
2023-06-14 9:15 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-06 12:36 ` Jonathan Cameron [this message]
2023-06-13 22:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 08/19] cxl/port: Enumerate flit mode capability Dan Williams
2023-06-06 13:04 ` Jonathan Cameron
2023-06-14 1:06 ` Dan Williams
2023-06-04 23:32 ` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage Dan Williams
2023-06-06 13:26 ` Jonathan Cameron
2023-06-07 16:47 ` Fan Ni
2023-06-13 22:59 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 10/19] cxl/memdev: Indicate probe deferral Dan Williams
2023-06-06 13:54 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse Dan Williams
2023-06-06 14:29 ` Jonathan Cameron
2023-06-13 23:29 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 12/19] cxl/region: Factor out interleave ways setup Dan Williams
2023-06-06 14:31 ` Jonathan Cameron
2023-06-13 23:30 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 13/19] cxl/region: Factor out interleave granularity setup Dan Williams
2023-06-06 14:33 ` Jonathan Cameron
2023-06-13 23:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach() Dan Williams
2023-06-06 14:35 ` Jonathan Cameron
2023-06-13 23:45 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time Dan Williams
2023-06-06 14:42 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation Dan Williams
2023-06-06 14:58 ` Jonathan Cameron
2023-06-13 23:53 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration Dan Williams
2023-06-06 15:23 ` Jonathan Cameron
2023-06-14 0:15 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 18/19] cxl/region: Define a driver interface for region creation Dan Williams
2023-06-06 15:31 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory Dan Williams
2023-06-06 15:34 ` Jonathan Cameron
2023-06-07 21:09 ` Vikram Sethi
2023-06-08 10:47 ` Jonathan Cameron
2023-06-08 14:34 ` Vikram Sethi
2023-06-08 15:22 ` Jonathan Cameron
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