From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <ira.weiny@intel.com>, <navneet.singh@intel.com>
Subject: Re: [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage
Date: Tue, 13 Jun 2023 15:59:49 -0700 [thread overview]
Message-ID: <a5099d00-a505-c6cb-ad3c-a7864d3ff412@intel.com> (raw)
In-Reply-To: <168592154692.1948938.3074738916245299862.stgit@dwillia2-xfh.jf.intel.com>
On 6/4/23 16:32, Dan Williams wrote:
> Move the endpoint port that the cxl_mem driver establishes from drvdata
> to a first class attribute. This is in preparation for device-memory
> drivers reusing the CXL core for memory region management. Those drivers
> need a type-safe method to retrieve their CXL port linkage. Leave
> drvdata for private usage of the cxl_mem driver not external consumers
> of a 'struct cxl_memdev' object.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> drivers/cxl/core/memdev.c | 4 ++--
> drivers/cxl/core/pmem.c | 2 +-
> drivers/cxl/core/port.c | 5 +++--
> drivers/cxl/cxlmem.h | 2 ++
> 4 files changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c
> index 3f2d54f30548..65a685e5616f 100644
> --- a/drivers/cxl/core/memdev.c
> +++ b/drivers/cxl/core/memdev.c
> @@ -149,7 +149,7 @@ int cxl_trigger_poison_list(struct cxl_memdev *cxlmd)
> struct cxl_port *port;
> int rc;
>
> - port = dev_get_drvdata(&cxlmd->dev);
> + port = cxlmd->endpoint;
> if (!port || !is_cxl_endpoint(port))
> return -EINVAL;
>
> @@ -207,7 +207,7 @@ static struct cxl_region *cxl_dpa_to_region(struct cxl_memdev *cxlmd, u64 dpa)
> ctx = (struct cxl_dpa_to_region_context) {
> .dpa = dpa,
> };
> - port = dev_get_drvdata(&cxlmd->dev);
> + port = cxlmd->endpoint;
> if (port && is_cxl_endpoint(port) && port->commit_end != -1)
> device_for_each_child(&port->dev, &ctx, __cxl_dpa_to_region);
>
> diff --git a/drivers/cxl/core/pmem.c b/drivers/cxl/core/pmem.c
> index f8c38d997252..fc94f5240327 100644
> --- a/drivers/cxl/core/pmem.c
> +++ b/drivers/cxl/core/pmem.c
> @@ -64,7 +64,7 @@ static int match_nvdimm_bridge(struct device *dev, void *data)
>
> struct cxl_nvdimm_bridge *cxl_find_nvdimm_bridge(struct cxl_memdev *cxlmd)
> {
> - struct cxl_port *port = find_cxl_root(dev_get_drvdata(&cxlmd->dev));
> + struct cxl_port *port = find_cxl_root(cxlmd->endpoint);
> struct device *dev;
>
> if (!port)
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 71a7547a8d6f..6720ab22a494 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1167,7 +1167,7 @@ static struct device *grandparent(struct device *dev)
> static void delete_endpoint(void *data)
> {
> struct cxl_memdev *cxlmd = data;
> - struct cxl_port *endpoint = dev_get_drvdata(&cxlmd->dev);
> + struct cxl_port *endpoint = cxlmd->endpoint;
> struct cxl_port *parent_port;
> struct device *parent;
>
> @@ -1182,6 +1182,7 @@ static void delete_endpoint(void *data)
> devm_release_action(parent, cxl_unlink_uport, endpoint);
> devm_release_action(parent, unregister_port, endpoint);
> }
> + cxlmd->endpoint = NULL;
> device_unlock(parent);
> put_device(parent);
> out:
> @@ -1193,7 +1194,7 @@ int cxl_endpoint_autoremove(struct cxl_memdev *cxlmd, struct cxl_port *endpoint)
> struct device *dev = &cxlmd->dev;
>
> get_device(&endpoint->dev);
> - dev_set_drvdata(dev, endpoint);
> + cxlmd->endpoint = endpoint;
> cxlmd->depth = endpoint->depth;
> return devm_add_action_or_reset(dev, delete_endpoint, cxlmd);
> }
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index b8bdf7490d2c..7ee78e79933c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -38,6 +38,7 @@
> * @detach_work: active memdev lost a port in its ancestry
> * @cxl_nvb: coordinate removal of @cxl_nvd if present
> * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
> + * @endpoint: connection to the CXL port topology for this memory device
> * @id: id number of this memdev instance.
> * @depth: endpoint port depth
> */
> @@ -48,6 +49,7 @@ struct cxl_memdev {
> struct work_struct detach_work;
> struct cxl_nvdimm_bridge *cxl_nvb;
> struct cxl_nvdimm *cxl_nvd;
> + struct cxl_port *endpoint;
> int id;
> int depth;
> };
>
next prev parent reply other threads:[~2023-06-13 23:00 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-04 23:31 [PATCH 00/19] cxl: Device memory setup Dan Williams
2023-06-04 23:31 ` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-05 8:46 ` Jonathan Cameron
2023-06-13 22:03 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-06 10:53 ` Jonathan Cameron
2023-06-13 22:08 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-06 11:10 ` Jonathan Cameron
2023-06-14 0:45 ` Dan Williams
2023-06-13 22:15 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-06 11:15 ` Jonathan Cameron
2023-06-13 20:53 ` Dan Williams
2023-06-04 23:32 ` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM} Dan Williams
2023-06-06 11:21 ` Jonathan Cameron
2023-06-13 21:03 ` Dan Williams
2023-06-04 23:32 ` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-06 11:27 ` Jonathan Cameron
2023-06-13 21:23 ` Dan Williams
2023-06-13 22:32 ` Dan Williams
2023-06-14 9:15 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-06 12:36 ` Jonathan Cameron
2023-06-13 22:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 08/19] cxl/port: Enumerate flit mode capability Dan Williams
2023-06-06 13:04 ` Jonathan Cameron
2023-06-14 1:06 ` Dan Williams
2023-06-04 23:32 ` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage Dan Williams
2023-06-06 13:26 ` Jonathan Cameron
2023-06-07 16:47 ` Fan Ni
2023-06-13 22:59 ` Dave Jiang [this message]
2023-06-04 23:32 ` [PATCH 10/19] cxl/memdev: Indicate probe deferral Dan Williams
2023-06-06 13:54 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse Dan Williams
2023-06-06 14:29 ` Jonathan Cameron
2023-06-13 23:29 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 12/19] cxl/region: Factor out interleave ways setup Dan Williams
2023-06-06 14:31 ` Jonathan Cameron
2023-06-13 23:30 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 13/19] cxl/region: Factor out interleave granularity setup Dan Williams
2023-06-06 14:33 ` Jonathan Cameron
2023-06-13 23:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach() Dan Williams
2023-06-06 14:35 ` Jonathan Cameron
2023-06-13 23:45 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time Dan Williams
2023-06-06 14:42 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation Dan Williams
2023-06-06 14:58 ` Jonathan Cameron
2023-06-13 23:53 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration Dan Williams
2023-06-06 15:23 ` Jonathan Cameron
2023-06-14 0:15 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 18/19] cxl/region: Define a driver interface for region creation Dan Williams
2023-06-06 15:31 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory Dan Williams
2023-06-06 15:34 ` Jonathan Cameron
2023-06-07 21:09 ` Vikram Sethi
2023-06-08 10:47 ` Jonathan Cameron
2023-06-08 14:34 ` Vikram Sethi
2023-06-08 15:22 ` Jonathan Cameron
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