From: Dave Jiang <dave.jiang@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <linux-cxl@vger.kernel.org>
Cc: <ira.weiny@intel.com>, <navneet.singh@intel.com>
Subject: Re: [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration
Date: Tue, 13 Jun 2023 17:15:33 -0700 [thread overview]
Message-ID: <9cf84597-ad17-bb06-732f-43ece6750ee3@intel.com> (raw)
In-Reply-To: <168592159290.1948938.13522227102445462976.stgit@dwillia2-xfh.jf.intel.com>
On 6/4/23 16:33, Dan Williams wrote:
> CXL region creation involves allocating capacity from device DPA
> (device-physical-address space) and assigning it to decode a given HPA
> (host-physical-address space). Before determininig how much DPA to
> allocate the amount of available HPA must be determined. Also, not all
> HPA is created equal, some specifically targets RAM, some target PMEM,
> some is prepared for the device-memory flows like HDM-D and HDM-DB, and
> some is host-only (HDM-H).
>
> Wrap all of those concerns into an API that retrieves a root decoder
> (platform CXL window) that fits the specified constraints and the
> capacity available for a new region.
>
> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> ---
> drivers/cxl/core/region.c | 143 +++++++++++++++++++++++++++++++++++++++++++++
> drivers/cxl/cxl.h | 5 ++
> drivers/cxl/cxlmem.h | 5 ++
> 3 files changed, 153 insertions(+)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 75c5de627868..a41756249f8d 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -575,6 +575,149 @@ static int free_hpa(struct cxl_region *cxlr)
> return 0;
> }
>
> +struct cxlrd_max_context {
> + struct device * const *host_bridges;
> + int interleave_ways;
> + unsigned long flags;
> + resource_size_t max_hpa;
> + struct cxl_root_decoder *cxlrd;
> +};
> +
> +static int find_max_hpa(struct device *dev, void *data)
> +{
> + struct cxlrd_max_context *ctx = data;
> + struct cxl_switch_decoder *cxlsd;
> + struct cxl_root_decoder *cxlrd;
> + struct resource *res, *prev;
> + struct cxl_decoder *cxld;
> + resource_size_t max;
> + unsigned int seq;
> + int found;
> +
> + if (!is_root_decoder(dev))
> + return 0;
> +
> + cxlrd = to_cxl_root_decoder(dev);
> + cxld = &cxlrd->cxlsd.cxld;
> + if ((cxld->flags & ctx->flags) != ctx->flags)
> + return 0;
> +
> + if (cxld->interleave_ways != ctx->interleave_ways)
> + return 0;
> +
> + cxlsd = &cxlrd->cxlsd;
> + do {
> + found = 0;
> + seq = read_seqbegin(&cxlsd->target_lock);
> + for (int i = 0; i < ctx->interleave_ways; i++)
> + for (int j = 0; j < ctx->interleave_ways; j++)
> + if (ctx->host_bridges[i] ==
> + cxlsd->target[j]->dport) {
> + found++;
> + break;
> + }
> + } while (read_seqretry(&cxlsd->target_lock, seq));
> +
> + if (found != ctx->interleave_ways)
> + return 0;
> +
> + /*
> + * Walk the root decoder resource range relying on cxl_region_rwsem to
> + * preclude sibling arrival/departure and find the largest free space
> + * gap.
> + */
> + lockdep_assert_held_read(&cxl_region_rwsem);
> + max = 0;
> + res = cxlrd->res->child;
> + if (!res)
> + max = resource_size(cxlrd->res);
> + else
> + max = 0;
> + for (prev = NULL; res; prev = res, res = res->sibling) {
> + struct resource *next = res->sibling;
> + resource_size_t free = 0;
> +
> + if (!prev && res->start > cxlrd->res->start) {
> + free = res->start - cxlrd->res->start;
> + max = max(free, max);
> + }
> + if (prev && res->start > prev->end + 1) {
> + free = res->start - prev->end + 1;
> + max = max(free, max);
> + }
Can skip the extra compare, not sure if it's worth the extra level of
indent.
if (!prev) {
if (res->start > cxlrd->res->start) {
free = res->start - cxlrd->res->start;
max = max(free, max)
}
} else {
if (res->start > prev->end + 1) {
free = res->start - prev->end + 1;
max = max(free, max);
}
}
Same below.
DJ
> + if (next && res->end + 1 < next->start) {
> + free = next->start - res->end + 1;
> + max = max(free, max);
> + }
> + if (!next && res->end + 1 < cxlrd->res->end + 1) {
> + free = cxlrd->res->end + 1 - res->end + 1;
> + max = max(free, max);
> + }
> + }
> +
> + if (max > ctx->max_hpa) {
> + if (ctx->cxlrd)
> + put_device(cxlrd_dev(ctx->cxlrd));
> + get_device(cxlrd_dev(cxlrd));
> + ctx->cxlrd = cxlrd;
> + ctx->max_hpa = max;
> + dev_dbg(cxlrd_dev(cxlrd), "found %pa bytes of free space\n", &max);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * cxl_hpa_freespace - find a root decoder with free capacity per constraints
> + * @endpoint: an endpoint that is mapped by the returned decoder
> + * @host_bridges: array of host-bridges that the decoder must interleave
> + * @interleave_ways: number of entries in @host_bridges
> + * @flags: CXL_DECODER_F flags for selecting RAM vs PMEM, and HDM-H vs HDM-D[B]
> + * @max: output parameter of bytes available in the returned decoder
> + *
> + * The return tuple of a 'struct cxl_root_decoder' and 'bytes available (@max)'
> + * is a point in time snapshot. If by the time the caller goes to use this root
> + * decoder's capacity the capacity is reduced then caller needs to loop and
> + * retry.
> + *
> + * The returned root decoder has an elevated reference count that needs to be
> + * put with put_device(cxlrd_dev(cxlrd)). Locking context is with
> + * cxl_{acquire,release}_endpoint(), that ensures removal of the root decoder
> + * does not race.
> + */
> +struct cxl_root_decoder *cxl_hpa_freespace(struct cxl_port *endpoint,
> + struct device *const *host_bridges,
> + int interleave_ways,
> + unsigned long flags,
> + resource_size_t *max)
> +{
> + struct cxlrd_max_context ctx = {
> + .host_bridges = host_bridges,
> + .interleave_ways = interleave_ways,
> + .flags = flags,
> + };
> + struct cxl_port *root;
> +
> + if (!is_cxl_endpoint(endpoint))
> + return ERR_PTR(-EINVAL);
> +
> + root = find_cxl_root(endpoint);
> + if (!root)
> + return ERR_PTR(-ENXIO);
> +
> + down_read(&cxl_region_rwsem);
> + device_for_each_child(&root->dev, &ctx, find_max_hpa);
> + up_read(&cxl_region_rwsem);
> + put_device(&root->dev);
> +
> + if (!ctx.cxlrd)
> + return ERR_PTR(-ENOMEM);
> +
> + *max = ctx.max_hpa;
> + return ctx.cxlrd;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_hpa_freespace, CXL);
> +
> static ssize_t size_store(struct device *dev, struct device_attribute *attr,
> const char *buf, size_t len)
> {
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 55808697773f..8400af85d99f 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -686,6 +686,11 @@ static inline struct device *cxled_dev(struct cxl_endpoint_decoder *cxled)
> return &cxled->cxld.dev;
> }
>
> +static inline struct device *cxlrd_dev(struct cxl_root_decoder *cxlrd)
> +{
> + return &cxlrd->cxlsd.cxld.dev;
> +}
> +
> bool is_root_decoder(struct device *dev);
> bool is_switch_decoder(struct device *dev);
> bool is_endpoint_decoder(struct device *dev);
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 8ec5c305d186..69f07186502d 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -93,6 +93,11 @@ struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_port *endpoint,
> enum cxl_decoder_mode mode,
> resource_size_t min,
> resource_size_t max);
> +struct cxl_root_decoder *cxl_hpa_freespace(struct cxl_port *endpoint,
> + struct device *const *host_bridges,
> + int interleave_ways,
> + unsigned long flags,
> + resource_size_t *max);
>
> static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
> struct cxl_memdev *cxlmd)
>
next prev parent reply other threads:[~2023-06-14 0:15 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-04 23:31 [PATCH 00/19] cxl: Device memory setup Dan Williams
2023-06-04 23:31 ` [PATCH 01/19] cxl/regs: Clarify when a 'struct cxl_register_map' is input vs output Dan Williams
2023-06-05 8:46 ` Jonathan Cameron
2023-06-13 22:03 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 02/19] tools/testing/cxl: Remove unused @cxlds argument Dan Williams
2023-06-06 10:53 ` Jonathan Cameron
2023-06-13 22:08 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 03/19] cxl/mbox: Move mailbox related driver state to its own data structure Dan Williams
2023-06-06 11:10 ` Jonathan Cameron
2023-06-14 0:45 ` Dan Williams
2023-06-13 22:15 ` Dave Jiang
2023-06-04 23:31 ` [PATCH 04/19] cxl/memdev: Make mailbox functionality optional Dan Williams
2023-06-06 11:15 ` Jonathan Cameron
2023-06-13 20:53 ` Dan Williams
2023-06-04 23:32 ` [PATCH 05/19] cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTMEM, DEVMEM} Dan Williams
2023-06-06 11:21 ` Jonathan Cameron
2023-06-13 21:03 ` Dan Williams
2023-06-04 23:32 ` [PATCH 06/19] cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM Dan Williams
2023-06-06 11:27 ` Jonathan Cameron
2023-06-13 21:23 ` Dan Williams
2023-06-13 22:32 ` Dan Williams
2023-06-14 9:15 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 07/19] cxl/region: Manage decoder target_type at decoder-attach time Dan Williams
2023-06-06 12:36 ` Jonathan Cameron
2023-06-13 22:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 08/19] cxl/port: Enumerate flit mode capability Dan Williams
2023-06-06 13:04 ` Jonathan Cameron
2023-06-14 1:06 ` Dan Williams
2023-06-04 23:32 ` [PATCH 09/19] cxl/memdev: Formalize endpoint port linkage Dan Williams
2023-06-06 13:26 ` Jonathan Cameron
2023-06-07 16:47 ` Fan Ni
2023-06-13 22:59 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 10/19] cxl/memdev: Indicate probe deferral Dan Williams
2023-06-06 13:54 ` Jonathan Cameron
2023-06-04 23:32 ` [PATCH 11/19] cxl/region: Factor out construct_region_{begin, end} and drop_region() for reuse Dan Williams
2023-06-06 14:29 ` Jonathan Cameron
2023-06-13 23:29 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 12/19] cxl/region: Factor out interleave ways setup Dan Williams
2023-06-06 14:31 ` Jonathan Cameron
2023-06-13 23:30 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 13/19] cxl/region: Factor out interleave granularity setup Dan Williams
2023-06-06 14:33 ` Jonathan Cameron
2023-06-13 23:42 ` Dave Jiang
2023-06-04 23:32 ` [PATCH 14/19] cxl/region: Clarify locking requirements of cxl_region_attach() Dan Williams
2023-06-06 14:35 ` Jonathan Cameron
2023-06-13 23:45 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 15/19] cxl/region: Specify host-only vs device memory at region creation time Dan Williams
2023-06-06 14:42 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 16/19] cxl/hdm: Define a driver interface for DPA allocation Dan Williams
2023-06-06 14:58 ` Jonathan Cameron
2023-06-13 23:53 ` Dave Jiang
2023-06-04 23:33 ` [PATCH 17/19] cxl/region: Define a driver interface for HPA free space enumeration Dan Williams
2023-06-06 15:23 ` Jonathan Cameron
2023-06-14 0:15 ` Dave Jiang [this message]
2023-06-04 23:33 ` [PATCH 18/19] cxl/region: Define a driver interface for region creation Dan Williams
2023-06-06 15:31 ` Jonathan Cameron
2023-06-04 23:33 ` [PATCH 19/19] tools/testing/cxl: Emulate a CXL accelerator with local memory Dan Williams
2023-06-06 15:34 ` Jonathan Cameron
2023-06-07 21:09 ` Vikram Sethi
2023-06-08 10:47 ` Jonathan Cameron
2023-06-08 14:34 ` Vikram Sethi
2023-06-08 15:22 ` Jonathan Cameron
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