From: Dave Jiang <dave.jiang@intel.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: linux-cxl@vger.kernel.org, dave@stgolabs.net, jic23@kernel.org,
vishal.l.verma@intel.com, ira.weiny@intel.com, djbw@kernel.org
Subject: Re: [PATCH 2/7] cxl/test: Add type2 support for mock CFMWS0
Date: Thu, 7 May 2026 16:36:10 -0700 [thread overview]
Message-ID: <705392c4-a00e-404d-bf5c-285015815c04@intel.com> (raw)
In-Reply-To: <afrFuzfkLtGlkmAP@aschofie-mobl2.lan>
On 5/5/26 9:38 PM, Alison Schofield wrote:
> On Wed, Apr 22, 2026 at 04:02:32PM -0700, Dave Jiang wrote:
>> Add a module parameter 'type2_test' for triggering type2 test support
>> in cxl_test. Setup the CFMWS0 configuration to be type2 when 'type2_test'
>> is set.
>
> Now that this joins the module param party, realizing we need some
> rules. How about starting with a simple enforcement that only one
> module param can be set at a time. Probably a count of params near
> top of cxl_test_init() will suffice.
I'll create a new patch for module param verification.
DJ
>
> Nothing else below, but I am going to comment on type2_test usage
> in Patch 4.
>
>>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> tools/testing/cxl/test/cxl.c | 27 ++++++++++++++++++++++++++-
>> 1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
>> index c26c37cef12c..903223013e41 100644
>> --- a/tools/testing/cxl/test/cxl.c
>> +++ b/tools/testing/cxl/test/cxl.c
>> @@ -16,6 +16,7 @@
>>
>> static int interleave_arithmetic;
>> static bool extended_linear_cache;
>> +static bool type2_test;
>>
>> #define FAKE_QTG_ID 42
>>
>> @@ -383,6 +384,19 @@ static struct {
>> },
>> };
>>
>> +static struct acpi_cedt_cfmws type2_cfmws0 = {
>> + .header = {
>> + .type = ACPI_CEDT_TYPE_CFMWS,
>> + .length = sizeof(mock_cedt.cfmws0),
>> + },
>> + .interleave_ways = 0,
>> + .granularity = 4,
>> + .restrictions = ACPI_CEDT_CFMWS_RESTRICT_DEVMEM |
>> + ACPI_CEDT_CFMWS_RESTRICT_VOLATILE,
>> + .qtg_id = FAKE_QTG_ID,
>> + .window_size = SZ_256M * 4,
>> +};
>> +
>> struct acpi_cedt_cfmws *mock_cfmws[] = {
>> [0] = &mock_cedt.cfmws0.cfmws,
>> [1] = &mock_cedt.cfmws1.cfmws,
>> @@ -471,6 +485,11 @@ static void cfmws_elc_update(struct acpi_cedt_cfmws *window, int index)
>> window->window_size = mock_auto_region_size * 2;
>> }
>>
>> +static void update_type2_cfmws(void)
>> +{
>> + memcpy(&mock_cedt.cfmws0.cfmws, &type2_cfmws0, sizeof(type2_cfmws0));
>> +}
>> +
>> static int populate_cedt(void)
>> {
>> struct cxl_mock_res *res;
>> @@ -492,10 +511,14 @@ static int populate_cedt(void)
>> chbs->length = size;
>> }
>>
>> + if (type2_test)
>> + update_type2_cfmws();
>> +
>> for (i = cfmws_start; i <= cfmws_end; i++) {
>> struct acpi_cedt_cfmws *window = mock_cfmws[i];
>>
>> - cfmws_elc_update(window, i);
>> + if (i == 0 && !type2_test)
>> + cfmws_elc_update(window, i);
>> res = alloc_mock_res(window->window_size, SZ_256M);
>> if (!res)
>> return -ENOMEM;
>> @@ -2029,6 +2052,8 @@ module_param(interleave_arithmetic, int, 0444);
>> MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1");
>> module_param(extended_linear_cache, bool, 0444);
>> MODULE_PARM_DESC(extended_linear_cache, "Enable extended linear cache support");
>> +module_param(type2_test, bool, 0444);
>> +MODULE_PARM_DESC(type2_test, "Enable type 2 support testing");
>> module_init(cxl_test_init);
>> module_exit(cxl_test_exit);
>> MODULE_LICENSE("GPL v2");
>> --
>> 2.53.0
>>
next prev parent reply other threads:[~2026-05-07 23:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-22 23:02 [PATCH 0/7] cxl: Add CXL type2 accelerator support for cxl_test Dave Jiang
2026-04-22 23:02 ` [PATCH 1/7] cxl/test: Refactor mock_init_hdm_decoder() to prep for type2 decoder Dave Jiang
2026-05-06 4:31 ` Alison Schofield
2026-05-07 23:35 ` Dave Jiang
2026-04-22 23:02 ` [PATCH 2/7] cxl/test: Add type2 support for mock CFMWS0 Dave Jiang
2026-05-06 4:38 ` Alison Schofield
2026-05-07 23:36 ` Dave Jiang [this message]
2026-04-22 23:02 ` [PATCH 3/7] cxl/test: Refactor platform device enumerations Dave Jiang
2026-05-06 4:45 ` Alison Schofield
2026-05-07 23:36 ` Dave Jiang
2026-04-22 23:02 ` [PATCH 4/7] cxl/test: Add hierarchy enumeration support for type2 device Dave Jiang
2026-05-06 5:05 ` Alison Schofield
2026-05-07 23:37 ` Dave Jiang
2026-04-22 23:02 ` [PATCH 5/7] cxl/test: Fixup hdm init for auto region to support type2 Dave Jiang
2026-05-06 5:07 ` Alison Schofield
2026-04-22 23:02 ` [PATCH 6/7] cxl/test: Add cxl_test accelerator driver Dave Jiang
2026-05-06 5:19 ` Alison Schofield
2026-05-07 23:41 ` Dave Jiang
2026-04-22 23:02 ` [PATCH 7/7] cxl: Fix double unregistration of CXL regions for type2 devices Dave Jiang
2026-04-23 7:10 ` Alejandro Lucero Palau
2026-04-23 14:36 ` Dave Jiang
2026-04-29 23:45 ` Dan Williams (nvidia)
2026-04-23 7:16 ` [PATCH 0/7] cxl: Add CXL type2 accelerator support for cxl_test Alejandro Lucero Palau
2026-05-06 4:20 ` Alison Schofield
2026-05-06 14:59 ` Dave Jiang
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