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From: Dave Jiang <dave.jiang@intel.com>
To: Anisa Su <anisa.su887@gmail.com>, linux-cxl@vger.kernel.org
Cc: Alison Schofield <alison.schofield@intel.com>,
	Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Li Ming <ming.li@zohomail.com>, Gregory Price <gourry@gourry.net>,
	Richard Cheng <icheng@nvidia.com>,
	Ben Cheatham <benjamin.cheatham@amd.com>,
	Anisa Su <anisa.su@samsung.com>
Subject: Re: [PATCH v14 8/8] Documentation/cxl: Document DPA partition layout and ordering rules
Date: Mon, 21 Sep 2026 15:02:49 -0700	[thread overview]
Message-ID: <9ffddb3d-9b22-4fe4-b355-bbad82f4b8aa@intel.com> (raw)
In-Reply-To: <20260918203049.7273-9-anisa.su@samsung.com>



On 9/18/26 1:30 PM, Anisa Su wrote:
> DC Partitions complicate DPA ordering. Add a DPA Partitions section to
> cxl-driver.rst describing spec-mandated and Linux requirements for the
> layout.
> 
> maturity-map.rst breaks the DCD entry into sub-items so the map shows
> what this series lands: partition enumeration is [1], event handling
> and DC-backed DAX regions remain [0] until the follow-on series enables
> them. The parent stays [0]; nothing is usable yet.
> 
> Suggested-by: Gregory Price <gourry@gourry.net>
> Signed-off-by: Anisa Su <anisa.su@samsung.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> ---
> Changes:
> [jonathan]: drop paragraph describing "support for additional
> dc partitions may be added later..." to avoid predicting future work in
> documentation
> [davidlohr]: add DCD sub-items to maturity-map.rst so a multi-step
> upstreaming shows users what is there and sets expectations.
> ---
>  .../driver-api/cxl/linux/cxl-driver.rst       | 35 +++++++++++++++++++
>  Documentation/driver-api/cxl/maturity-map.rst |  4 +++
>  2 files changed, 39 insertions(+)
> 
> diff --git a/Documentation/driver-api/cxl/linux/cxl-driver.rst b/Documentation/driver-api/cxl/linux/cxl-driver.rst
> index dd6dd17dc536..eb4de2a9a9af 100644
> --- a/Documentation/driver-api/cxl/linux/cxl-driver.rst
> +++ b/Documentation/driver-api/cxl/linux/cxl-driver.rst
> @@ -181,6 +181,41 @@ A Memory Device is a discrete base object that is not a port.  While the
>  physical device it belongs to may also host an `endpoint`, the relationship
>  between an `endpoint` and a `memdev` is not captured in sysfs.
>  
> +DPA Partitions
> +~~~~~~~~~~~~~~
> +A memory device presents its capacity as one flat `Device Physical Address`
> +(DPA) space divided into `partitions`, which Linux lays out in a fixed
> +order::
> +
> +  DPA 0                                                     end
> +  +---------------+---------------+---------------------------+
> +  |      ram      |     pmem      |       dynamic_ram_1       |
> +  +---------------+---------------+---------------------------+
> +  part[0]         part[1]         part[2]
> +
> +Part of that order is required by the CXL specification and part of it is a
> +Linux choice.
> +
> +The `ram` and `pmem` order is mandated.  CXL r4.0 section 8.2.10.9.2.1 "Get
> +Partition Info" (4100h), Table 8-310, mandates that volatile capacity starts
> +at DPA 0 and pmem starts at the DPA immediately following it.
> +
> +Dynamic Capacity partitions only need to be 256MB aligned according to
> +CXL r4.0 section 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
> +(opcode 4800h), Table 8-347. So a device could leave a gap between ram/pmem
> +(static) capacity and its first DC partition, or between one DC partition
> +and the next.
> +
> +Linux chooses not to support gaps between static and dynamic capacity: the
> +first DC partition must begin at the DPA immediately following static
> +capacity -- after pmem, after ram on a device with no pmem, or at DPA 0 on
> +a device with no static capacity at all.
> +
> +Currently, only one dynamic partition is supported. A device may report up
> +to eight (CXL r4.0 Table 8-346); Linux configures the first and exposes it as
> +`dynamic_ram_1`. Gaps between DC partitions are not checked, since only the
> +first is used.
> +
>  Port Relationships
>  ~~~~~~~~~~~~~~~~~~
>  In our example described above, there are four host bridges attached to the
> diff --git a/Documentation/driver-api/cxl/maturity-map.rst b/Documentation/driver-api/cxl/maturity-map.rst
> index 282c1102dd81..fefd31899229 100644
> --- a/Documentation/driver-api/cxl/maturity-map.rst
> +++ b/Documentation/driver-api/cxl/maturity-map.rst

Maybe hold off this commit for when everything goes in? Otherwise it's weird that there's documentation but no code.

> @@ -150,6 +150,10 @@ Memory-pooling
>  * [1] Hotplug of LDs (via PCI hotplug)
>  * [0] Dynamic Capacity Device (DCD) Support
>  
> +  * [1] DC partition enumeration / configuration (Get DC Config, CDAT DSMAS, event interrupts)
> +  * [0] Extent add / release event handling
> +  * [0] DC-backed DAX regions

I would just update maturity map once when the entire DCD code is in.

> +
>  Multi-host sharing
>  ------------------
>  


  reply	other threads:[~2026-09-21 22:02 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-18 20:30 [PATCH v14 0/8] DCD Prep Series Anisa Su
2026-09-18 20:30 ` [PATCH v14 1/8] cxl/mbox: Flag support for Dynamic Capacity Devices (DCD) Anisa Su
2026-09-18 20:30 ` [PATCH v14 2/8] cxl/mem: Read dynamic capacity configuration from the device Anisa Su
2026-09-18 20:44   ` sashiko-bot
2026-09-18 22:59     ` Anisa Su
2026-09-21 21:50   ` Dave Jiang
2026-09-21 23:19   ` Jonathan Cameron
2026-09-22  3:44   ` Richard Cheng
2026-09-24  0:55     ` Jonathan Cameron
2026-09-24  7:01       ` Anisa Su
2026-09-18 20:30 ` [PATCH v14 3/8] cxl/cdat: Gather DSMAS data for DCD partitions Anisa Su
2026-09-21 21:55   ` Dave Jiang
2026-09-24  5:12     ` Anisa Su
2026-09-21 23:27   ` Jonathan Cameron
2026-09-24  5:01     ` Anisa Su
2026-09-22  3:53   ` Richard Cheng
2026-09-22 17:08     ` Dave Jiang
2026-09-22 21:15       ` Anisa Su
2026-09-22 23:05         ` Dave Jiang
2026-09-23  0:05           ` Anisa Su
2026-09-23 15:35             ` Dave Jiang
2026-09-24  4:58               ` Anisa Su
2026-09-18 20:30 ` [PATCH v14 4/8] cxl/events: Split event msgnum configuration from irq setup Anisa Su
2026-09-22  5:35   ` Richard Cheng
2026-09-18 20:30 ` [PATCH v14 5/8] cxl/pci: Factor out interrupt policy check Anisa Su
2026-09-22  5:37   ` Richard Cheng
2026-09-18 20:30 ` [PATCH v14 6/8] cxl/mem: Configure dynamic capacity interrupts Anisa Su
2026-09-18 20:43   ` sashiko-bot
2026-09-18 23:38     ` Anisa Su
2026-09-21 22:00   ` Dave Jiang
2026-09-21 23:42     ` Jonathan Cameron
2026-09-22  0:45       ` Dave Jiang
2026-09-22 21:22         ` Anisa Su
2026-09-24  0:58           ` Jonathan Cameron
2026-09-22  5:48   ` Richard Cheng
2026-09-22  9:15     ` Richard Cheng
2026-09-18 20:30 ` [PATCH v14 7/8] cxl/core: Enforce partition order/simplify partition calls Anisa Su
2026-09-18 20:30 ` [PATCH v14 8/8] Documentation/cxl: Document DPA partition layout and ordering rules Anisa Su
2026-09-21 22:02   ` Dave Jiang [this message]
2026-09-28 21:53     ` Anisa Su
2026-09-28 22:36       ` Dave Jiang

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