[PATCH 0/2] soc: qcom: llcc-qcom: Add support for Eliza and document bindings

[PATCH 0/2] soc: qcom: llcc-qcom: Add support for Eliza and document bindings

[Abel Vesa]

Add support for the Last Level Cache Controller found on the Qualcomm
Eliza SoC.

Eliza's LLCC uses a 4-region register layout, with two per-bank base
regions plus the broadcast OR and AND windows.

Describe that layout in the devicetree bindings and add the corresponding
slice configuration and driver data in llcc-qcom.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Abel Vesa (2):
      dt-bindings: cache: qcom,llcc: Document Eliza LLCC block
      soc: qcom: llcc-qcom: Add support for Eliza

 .../devicetree/bindings/cache/qcom,llcc.yaml       |  22 +++
 drivers/soc/qcom/llcc-qcom.c                       | 180 +++++++++++++++++++++
 2 files changed, 202 insertions(+)
---
base-commit: b9303e6bff706758c167af686b5315ad00233bf8
change-id: 20260428-eliza-llcc-312b07fefc10

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Abel Vesa]

Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
base register regions and an additional AND, OR broadcast region, total 4
register regions.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 995d57815781..90f5a54b76e3 100644
--- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -20,6 +20,7 @@ description: |
 properties:
   compatible:
     enum:
+      - qcom,eliza-llcc
       - qcom,glymur-llcc
       - qcom,ipq5424-llcc
       - qcom,kaanapali-llcc
@@ -341,6 +342,27 @@ allOf:
             - const: llcc_broadcast_base
             - const: llcc_broadcast_and_base
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,eliza-llcc
+    then:
+      properties:
+        reg:
+          items:
+            - description: LLCC0 base register region
+            - description: LLCC2 base register region
+            - description: LLCC broadcast OR register region
+            - description: LLCC broadcast AND register region
+        reg-names:
+          items:
+            - const: llcc0_base
+            - const: llcc2_base
+            - const: llcc_broadcast_base
+            - const: llcc_broadcast_and_base
+
 additionalProperties: false
 
 examples:

-- 
2.54.0

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
> base register regions and an additional AND, OR broadcast region, total 4
> register regions.
> 
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> index 995d57815781..90f5a54b76e3 100644
> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
> @@ -20,6 +20,7 @@ description: |
>  properties:
>    compatible:
>      enum:
> +      - qcom,eliza-llcc
>        - qcom,glymur-llcc
>        - qcom,ipq5424-llcc
>        - qcom,kaanapali-llcc
> @@ -341,6 +342,27 @@ allOf:
>              - const: llcc_broadcast_base
>              - const: llcc_broadcast_and_base
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,eliza-llcc
> +    then:
> +      properties:
> +        reg:
> +          items:
> +            - description: LLCC0 base register region
> +            - description: LLCC2 base register region

LLCC1?

> +            - description: LLCC broadcast OR register region
> +            - description: LLCC broadcast AND register region
> +        reg-names:
> +          items:
> +            - const: llcc0_base
> +            - const: llcc2_base

llcc1_base?

Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Konrad Dybcio]

On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>> base register regions and an additional AND, OR broadcast region, total 4
>> register regions.
>>
>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>> ---
>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>  1 file changed, 22 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> index 995d57815781..90f5a54b76e3 100644
>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>> @@ -20,6 +20,7 @@ description: |
>>  properties:
>>    compatible:
>>      enum:
>> +      - qcom,eliza-llcc
>>        - qcom,glymur-llcc
>>        - qcom,ipq5424-llcc
>>        - qcom,kaanapali-llcc
>> @@ -341,6 +342,27 @@ allOf:
>>              - const: llcc_broadcast_base
>>              - const: llcc_broadcast_and_base
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,eliza-llcc
>> +    then:
>> +      properties:
>> +        reg:
>> +          items:
>> +            - description: LLCC0 base register region
>> +            - description: LLCC2 base register region
> 
> LLCC1?

Unfortunately not

Konrad

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 06/05/2026 10:49, Konrad Dybcio wrote:
> On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
>> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>>> base register regions and an additional AND, OR broadcast region, total 4
>>> register regions.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>> ---
>>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>>  1 file changed, 22 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> index 995d57815781..90f5a54b76e3 100644
>>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>> @@ -20,6 +20,7 @@ description: |
>>>  properties:
>>>    compatible:
>>>      enum:
>>> +      - qcom,eliza-llcc
>>>        - qcom,glymur-llcc
>>>        - qcom,ipq5424-llcc
>>>        - qcom,kaanapali-llcc
>>> @@ -341,6 +342,27 @@ allOf:
>>>              - const: llcc_broadcast_base
>>>              - const: llcc_broadcast_and_base
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,eliza-llcc
>>> +    then:
>>> +      properties:
>>> +        reg:
>>> +          items:
>>> +            - description: LLCC0 base register region
>>> +            - description: LLCC2 base register region
>>
>> LLCC1?
> 
> Unfortunately not

Then let's just skip the names, because it will cause unnecessary
confusion when name is llcc1 (since it is the NEXT entry) but it points
to block called LLCC2 in the manual.


Best regards,
Krzysztof

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Konrad Dybcio]

On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
> On 06/05/2026 10:49, Konrad Dybcio wrote:
>> On 5/6/26 10:25 AM, Krzysztof Kozlowski wrote:
>>> On Mon, May 04, 2026 at 01:00:07PM +0300, Abel Vesa wrote:
>>>> Document the Last Level Cache Controller on Eliza SoC. Eliza LLCC has 2
>>>> base register regions and an additional AND, OR broadcast region, total 4
>>>> register regions.
>>>>
>>>> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
>>>> ---
>>>>  .../devicetree/bindings/cache/qcom,llcc.yaml       | 22 ++++++++++++++++++++++
>>>>  1 file changed, 22 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> index 995d57815781..90f5a54b76e3 100644
>>>> --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
>>>> @@ -20,6 +20,7 @@ description: |
>>>>  properties:
>>>>    compatible:
>>>>      enum:
>>>> +      - qcom,eliza-llcc
>>>>        - qcom,glymur-llcc
>>>>        - qcom,ipq5424-llcc
>>>>        - qcom,kaanapali-llcc
>>>> @@ -341,6 +342,27 @@ allOf:
>>>>              - const: llcc_broadcast_base
>>>>              - const: llcc_broadcast_and_base
>>>>  
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            enum:
>>>> +              - qcom,eliza-llcc
>>>> +    then:
>>>> +      properties:
>>>> +        reg:
>>>> +          items:
>>>> +            - description: LLCC0 base register region
>>>> +            - description: LLCC2 base register region
>>>
>>> LLCC1?
>>
>> Unfortunately not
> 
> Then let's just skip the names, because it will cause unnecessary
> confusion when name is llcc1 (since it is the NEXT entry) but it points
> to block called LLCC2 in the manual.

I don't think skipping the names is a good idea, especially since if
we keep them, we could teach the driver what channel the region actually
corresponds to

Konrad

Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Document Eliza LLCC block

[Krzysztof Kozlowski]

On 06/05/2026 12:47, Konrad Dybcio wrote:
> On 5/6/26 11:56 AM, Krzysztof Kozlowski wrote:
>>>>> +    then:
>>>>> +      properties:
>>>>> +        reg:
>>>>> +          items:
>>>>> +            - description: LLCC0 base register region
>>>>> +            - description: LLCC2 base register region
>>>>
>>>> LLCC1?
>>>
>>> Unfortunately not
>>
>> Then let's just skip the names, because it will cause unnecessary
>> confusion when name is llcc1 (since it is the NEXT entry) but it points
>> to block called LLCC2 in the manual.
> 
> I don't think skipping the names is a good idea, especially since if
> we keep them, we could teach the driver what channel the region actually
> corresponds to

You still can do it, because indices are fixed. Names are only helper
and makes that easier.

The problem looks to me purely doc-related, because this is logically
second channel, so LLCC1, just like qcom,sc7280-llcc or
qcom,sdm670-llcc. Does naming it as third channel (LLCC2) is relevant
for programming interface? Imagine driver taking LLCCx and using the 'x'
as offset?

I tried to find something in HPG but no luck.


Best regards,
Krzysztof

[PATCH 2/2] soc: qcom: llcc-qcom: Add support for Eliza

[Abel Vesa]

Eliza uses a 4-region LLCC register layout made up of two per-bank base
register regions together with the broadcast OR and AND regions.

Document that layout in the devicetree bindings.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 drivers/soc/qcom/llcc-qcom.c | 180 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 180 insertions(+)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 0161ceec8842..7c05cb3619b2 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -181,6 +181,171 @@ enum llcc_reg_offset {
 	LLCC_TRP_WRS_CACHEABLE_EN,
 };
 
+static const struct llcc_slice_config eliza_data[] = {
+	{
+		.usecase_id = LLCC_CPUSS,
+		.slice_id = 1,
+		.max_cap = 896,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.write_scid_en = true,
+		.stale_en = true,
+	},
+	{
+		.usecase_id = LLCC_MDMHPFX,
+		.slice_id = 24,
+		.max_cap = 1024,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_VIDSC0,
+		.slice_id = 2,
+		.max_cap = 128,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_MDMHPGRW,
+		.slice_id = 25,
+		.max_cap = 1024,
+		.priority = 5,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_GPUHTW,
+		.slice_id = 11,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_GPU,
+		.slice_id = 9,
+		.max_cap = 896,
+		.priority = 1,
+		.bonus_ways = 0xfff,
+		.write_scid_cacheable_en = true,
+	},
+	{
+		.usecase_id = LLCC_MMUHWT,
+		.slice_id = 18,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+	},
+	{
+		.usecase_id = LLCC_MDMPNG,
+		.slice_id = 27,
+		.max_cap = 256,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+	},
+	{
+		.usecase_id = LLCC_MODPE,
+		.slice_id = 29,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xf00,
+		.alloc_oneway_en = true,
+	},
+	{
+		.usecase_id = LLCC_WRCACHE,
+		.slice_id = 31,
+		.max_cap = 256,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+	},
+	{
+		.usecase_id = LLCC_LCPDARE,
+		.slice_id = 30,
+		.max_cap = 128,
+		.priority = 5,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.alloc_oneway_en = true,
+	},
+	{
+		.usecase_id = LLCC_ISLAND1,
+		.slice_id = 12,
+		.max_cap = 1280,
+		.priority = 7,
+		.fixed_size = true,
+		.res_ways = 0x3ff,
+	},
+	{
+		.usecase_id = LLCC_CAMOFE,
+		.slice_id = 33,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMRTIP,
+		.slice_id = 13,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMSRTIP,
+		.slice_id = 14,
+		.max_cap = 512,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMRTRF,
+		.slice_id = 7,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CAMSRTRF,
+		.slice_id = 21,
+		.max_cap = 1024,
+		.priority = 1,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.stale_en = true,
+		.parent_slice_id = 13,
+	},
+	{
+		.usecase_id = LLCC_CPUSSMPAM,
+		.slice_id = 6,
+		.max_cap = 512,
+		.priority = 0,
+		.fixed_size = true,
+		.bonus_ways = 0xfff,
+		.activate_on_init = true,
+		.write_scid_en = true,
+		.stale_en = true,
+	},
+};
+
 static const struct llcc_slice_config glymur_data[] = {
 	{
 		.usecase_id = LLCC_CPUSS,
@@ -4141,6 +4306,15 @@ static const u32 llcc_v6_reg_offset[] = {
 	[LLCC_TRP_WRS_CACHEABLE_EN]	= 0x00042088,
 };
 
+static const struct qcom_llcc_config eliza_cfg[] = {
+	{
+		.sct_data	= eliza_data,
+		.size		= ARRAY_SIZE(eliza_data),
+		.reg_offset	= llcc_v6_reg_offset,
+		.edac_reg_offset = &llcc_v6_edac_reg_offset,
+	},
+};
+
 static const struct qcom_llcc_config kaanapali_cfg[] = {
 	{
 		.sct_data	= kaanapali_data,
@@ -4397,6 +4571,11 @@ static const struct qcom_llcc_config x1e80100_cfg[] = {
 	},
 };
 
+static const struct qcom_sct_config eliza_cfgs = {
+	.llcc_config	= eliza_cfg,
+	.num_config	= ARRAY_SIZE(eliza_cfg),
+};
+
 static const struct qcom_sct_config kaanapali_cfgs = {
 	.llcc_config	= kaanapali_cfg,
 	.num_config	= ARRAY_SIZE(kaanapali_cfg),
@@ -5238,6 +5417,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_llcc_of_match[] = {
+	{ .compatible = "qcom,eliza-llcc", .data = &eliza_cfgs },
 	{ .compatible = "qcom,glymur-llcc", .data = &glymur_cfgs },
 	{ .compatible = "qcom,ipq5424-llcc", .data = &ipq5424_cfgs},
 	{ .compatible = "qcom,kaanapali-llcc", .data = &kaanapali_cfgs},

-- 
2.54.0

Re: [PATCH 2/2] soc: qcom: llcc-qcom: Add support for Eliza

[Konrad Dybcio]

On 5/4/26 12:00 PM, Abel Vesa wrote:
> Eliza uses a 4-region LLCC register layout made up of two per-bank base
> register regions together with the broadcast OR and AND regions.
> 
> Document that layout in the devicetree bindings.

:)

Otherwise, matches the docs

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 2/2] soc: qcom: llcc-qcom: Add support for Eliza

[Abel Vesa]

On 26-05-04 12:24:56, Konrad Dybcio wrote:
> On 5/4/26 12:00 PM, Abel Vesa wrote:
> > Eliza uses a 4-region LLCC register layout made up of two per-bank base
> > register regions together with the broadcast OR and AND regions.
> > 
> > Document that layout in the devicetree bindings.
> 
> :)
> 
> Otherwise, matches the docs

Will drop and resend.

> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad
> 

Thanks.