From: Manivannan Sadhasivam <mani@kernel.org>
To: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Saravana Kannan" <saravanak@google.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>
Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>,
Brian Norris <briannorris@chromium.org>,
Bjorn Helgaas <helgaas@kernel.org>
Subject: Re: (subset) [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available
Date: Wed, 17 Sep 2025 15:40:35 +0530 [thread overview]
Message-ID: <175810383525.37722.6338178642788441926.b4-ty@kernel.org> (raw)
In-Reply-To: <20250912-pci-pwrctrl-perst-v3-0-3c0ac62b032c@oss.qualcomm.com>
On Fri, 12 Sep 2025 14:05:00 +0530, Manivannan Sadhasivam wrote:
> This series is the proper version for toggling PERST# from the pwrctrl
> framework after the initial RFC posted earlier [1].
>
> Problem statement
> =================
>
> Pwrctrl framework is intented to control the supplies to the components on the
> PCI bus. However, if the platform supports the PERST# signal, it should be
> toggled as per the requirements in the electromechanical specifications like
> PCIe CEM, Mini, and M.2. Since the pwrctrl framework is controlling the power
> supplies, it should also toggle PERST# as per the requirements in the above
> mentioned specifications. Right now, it is just controlling the power to the
> components and rely on controller drivers to toggle PERST#, which goes against
> the specs. For instance, controller drivers will deassert PERST# even before the
> pwrctrl driver enables the supplies. This causes the device to see PERST#
> deassert immediately after power on, thereby violating the delay requirements in
> the PCI Electromechanical specs.
>
> [...]
Applied, thanks!
[2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
commit: af8df709bf365f5583d31091280354e1ef0b201f
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2025-09-17 10:10 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 8:35 [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available Manivannan Sadhasivam via B4 Relay
2025-09-12 8:35 ` [PATCH v3 1/4] PCI/pwrctrl: Add support for asserting/deasserting PERST# Manivannan Sadhasivam via B4 Relay
2025-09-12 8:35 ` [PATCH v3 2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port Manivannan Sadhasivam via B4 Relay
2025-09-12 23:23 ` Bjorn Helgaas
2025-09-15 13:01 ` Manivannan Sadhasivam
2025-09-16 20:08 ` Bjorn Helgaas
2025-09-17 10:10 ` Manivannan Sadhasivam
2025-09-12 8:35 ` [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes Manivannan Sadhasivam via B4 Relay
2025-09-12 23:28 ` Bjorn Helgaas
2025-09-15 12:53 ` Manivannan Sadhasivam
2025-09-16 19:49 ` Bjorn Helgaas
2025-09-17 10:08 ` Manivannan Sadhasivam
2025-09-12 8:35 ` [PATCH v3 4/4] PCI: qcom: Allow pwrctrl core to control PERST# if 'reset-gpios' property is available Manivannan Sadhasivam via B4 Relay
2025-09-16 20:48 ` Bjorn Helgaas
2025-09-17 10:23 ` Manivannan Sadhasivam
2025-09-18 18:53 ` Bjorn Helgaas
2025-09-19 8:15 ` Manivannan Sadhasivam
2025-09-22 16:00 ` Bjorn Helgaas
2025-09-22 16:33 ` Manivannan Sadhasivam
2025-09-17 10:10 ` Manivannan Sadhasivam [this message]
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