public inbox for devicetree@vger.kernel.org
 help / color / mirror / Atom feed
From: Bjorn Helgaas <helgaas@kernel.org>
To: manivannan.sadhasivam@oss.qualcomm.com
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Saravana Kannan" <saravanak@google.com>,
	linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Brian Norris" <briannorris@chromium.org>
Subject: Re: [PATCH v3 2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
Date: Tue, 16 Sep 2025 15:08:17 -0500	[thread overview]
Message-ID: <20250916200817.GA1814336@bhelgaas> (raw)
In-Reply-To: <20250912-pci-pwrctrl-perst-v3-2-3c0ac62b032c@oss.qualcomm.com>

On Fri, Sep 12, 2025 at 02:05:02PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> 
> DT binding allows specifying 'phy' and 'reset' properties in both host
> bridge and Root Port nodes, though specifying in the host bridge node is
> marked as deprecated. Still, the pcie-qcom driver should support both
> combinations for maintaining the DT backwards compatibility. For this
> purpose, the driver is holding the relevant pointers of these properties in
> two structs: struct qcom_pcie_port and struct qcom_pcie.
> 
> However, this causes confusion and increases the driver complexity. Hence,
> move the pointers from struct qcom_pcie to struct qcom_pcie_port. As a
> result, even if these properties are specified in the host bridge node,
> the pointers will be stored in struct qcom_pcie_port as if the properties
> are specified in a single Root Port node. This logic simplifies the driver
> a lot.
> 
> Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> 

I would put this patch by itself on pci/controller/qcom immediately
because it's not related to the rest of the series, and we should make
sure it's in v6.18 regardless of the rest.

> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 87 ++++++++++++++--------------------
>  1 file changed, 36 insertions(+), 51 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 294babe1816e4d0c2b2343fe22d89af72afcd6cd..6170c86f465f43f980f5b2f88bd8799c3c152e68 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -279,8 +279,6 @@ struct qcom_pcie {
>  	void __iomem *elbi;			/* DT elbi */
>  	void __iomem *mhi;
>  	union qcom_pcie_resources res;
> -	struct phy *phy;
> -	struct gpio_desc *reset;
>  	struct icc_path *icc_mem;
>  	struct icc_path *icc_cpu;
>  	const struct qcom_pcie_cfg *cfg;
> @@ -297,11 +295,8 @@ static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert)
>  	struct qcom_pcie_port *port;
>  	int val = assert ? 1 : 0;
>  
> -	if (list_empty(&pcie->ports))
> -		gpiod_set_value_cansleep(pcie->reset, val);
> -	else
> -		list_for_each_entry(port, &pcie->ports, list)
> -			gpiod_set_value_cansleep(port->reset, val);
> +	list_for_each_entry(port, &pcie->ports, list)
> +		gpiod_set_value_cansleep(port->reset, val);
>  
>  	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
>  }
> @@ -1253,57 +1248,32 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci)
>  	return val & PCI_EXP_LNKSTA_DLLLA;
>  }
>  
> -static void qcom_pcie_phy_exit(struct qcom_pcie *pcie)
> -{
> -	struct qcom_pcie_port *port;
> -
> -	if (list_empty(&pcie->ports))
> -		phy_exit(pcie->phy);
> -	else
> -		list_for_each_entry(port, &pcie->ports, list)
> -			phy_exit(port->phy);
> -}
> -
>  static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie)
>  {
>  	struct qcom_pcie_port *port;
>  
> -	if (list_empty(&pcie->ports)) {
> -		phy_power_off(pcie->phy);
> -	} else {
> -		list_for_each_entry(port, &pcie->ports, list)
> -			phy_power_off(port->phy);
> -	}
> +	list_for_each_entry(port, &pcie->ports, list)
> +		phy_power_off(port->phy);
>  }
>  
>  static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie)
>  {
>  	struct qcom_pcie_port *port;
> -	int ret = 0;
> +	int ret;
>  
> -	if (list_empty(&pcie->ports)) {
> -		ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> +	list_for_each_entry(port, &pcie->ports, list) {
> +		ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
>  		if (ret)
>  			return ret;
>  
> -		ret = phy_power_on(pcie->phy);
> -		if (ret)
> +		ret = phy_power_on(port->phy);
> +		if (ret) {
> +			qcom_pcie_phy_power_off(pcie);
>  			return ret;
> -	} else {
> -		list_for_each_entry(port, &pcie->ports, list) {
> -			ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
> -			if (ret)
> -				return ret;
> -
> -			ret = phy_power_on(port->phy);
> -			if (ret) {
> -				qcom_pcie_phy_power_off(pcie);
> -				return ret;
> -			}
>  		}
>  	}
>  
> -	return ret;
> +	return 0;
>  }
>  
>  static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
> @@ -1748,8 +1718,10 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pcie)
>  	return ret;
>  
>  err_port_del:
> -	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> +	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> +		phy_exit(port->phy);
>  		list_del(&port->list);
> +	}
>  
>  	return ret;
>  }
> @@ -1757,20 +1729,32 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *pcie)
>  static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie)
>  {
>  	struct device *dev = pcie->pci->dev;
> +	struct qcom_pcie_port *port;
> +	struct gpio_desc *reset;
> +	struct phy *phy;
>  	int ret;
>  
> -	pcie->phy = devm_phy_optional_get(dev, "pciephy");
> -	if (IS_ERR(pcie->phy))
> -		return PTR_ERR(pcie->phy);
> +	phy = devm_phy_optional_get(dev, "pciephy");
> +	if (IS_ERR(phy))
> +		return PTR_ERR(phy);
>  
> -	pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> -	if (IS_ERR(pcie->reset))
> -		return PTR_ERR(pcie->reset);
> +	reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> +	if (IS_ERR(reset))
> +		return PTR_ERR(reset);
>  
> -	ret = phy_init(pcie->phy);
> +	ret = phy_init(phy);
>  	if (ret)
>  		return ret;
>  
> +	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> +	if (!port)
> +		return -ENOMEM;
> +
> +	port->reset = reset;
> +	port->phy = phy;
> +	INIT_LIST_HEAD(&port->list);
> +	list_add_tail(&port->list, &pcie->ports);
> +
>  	return 0;
>  }
>  
> @@ -1984,9 +1968,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>  err_host_deinit:
>  	dw_pcie_host_deinit(pp);
>  err_phy_exit:
> -	qcom_pcie_phy_exit(pcie);
> -	list_for_each_entry_safe(port, tmp, &pcie->ports, list)
> +	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> +		phy_exit(port->phy);
>  		list_del(&port->list);
> +	}
>  err_pm_runtime_put:
>  	pm_runtime_put(dev);
>  	pm_runtime_disable(dev);
> 
> -- 
> 2.45.2
> 
> 

  parent reply	other threads:[~2025-09-16 20:08 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-12  8:35 [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available Manivannan Sadhasivam via B4 Relay
2025-09-12  8:35 ` [PATCH v3 1/4] PCI/pwrctrl: Add support for asserting/deasserting PERST# Manivannan Sadhasivam via B4 Relay
2025-09-12  8:35 ` [PATCH v3 2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port Manivannan Sadhasivam via B4 Relay
2025-09-12 23:23   ` Bjorn Helgaas
2025-09-15 13:01     ` Manivannan Sadhasivam
2025-09-16 20:08   ` Bjorn Helgaas [this message]
2025-09-17 10:10     ` Manivannan Sadhasivam
2025-09-12  8:35 ` [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes Manivannan Sadhasivam via B4 Relay
2025-09-12 23:28   ` Bjorn Helgaas
2025-09-15 12:53     ` Manivannan Sadhasivam
2025-09-16 19:49       ` Bjorn Helgaas
2025-09-17 10:08         ` Manivannan Sadhasivam
2025-09-12  8:35 ` [PATCH v3 4/4] PCI: qcom: Allow pwrctrl core to control PERST# if 'reset-gpios' property is available Manivannan Sadhasivam via B4 Relay
2025-09-16 20:48   ` Bjorn Helgaas
2025-09-17 10:23     ` Manivannan Sadhasivam
2025-09-18 18:53       ` Bjorn Helgaas
2025-09-19  8:15         ` Manivannan Sadhasivam
2025-09-22 16:00           ` Bjorn Helgaas
2025-09-22 16:33             ` Manivannan Sadhasivam
2025-09-17 10:10 ` (subset) [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available Manivannan Sadhasivam

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250916200817.GA1814336@bhelgaas \
    --to=helgaas@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=brgl@bgdev.pl \
    --cc=briannorris@chromium.org \
    --cc=devicetree@vger.kernel.org \
    --cc=krishna.chundru@oss.qualcomm.com \
    --cc=kwilczynski@kernel.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lpieralisi@kernel.org \
    --cc=mani@kernel.org \
    --cc=manivannan.sadhasivam@oss.qualcomm.com \
    --cc=robh@kernel.org \
    --cc=saravanak@google.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox