From: Bjorn Helgaas <helgaas@kernel.org>
To: manivannan.sadhasivam@oss.qualcomm.com
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
"Saravana Kannan" <saravanak@google.com>,
linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
"Brian Norris" <briannorris@chromium.org>
Subject: Re: [PATCH v3 2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port
Date: Fri, 12 Sep 2025 18:23:48 -0500 [thread overview]
Message-ID: <20250912232348.GA1653056@bhelgaas> (raw)
In-Reply-To: <20250912-pci-pwrctrl-perst-v3-2-3c0ac62b032c@oss.qualcomm.com>
On Fri, Sep 12, 2025 at 02:05:02PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
>
> DT binding allows specifying 'phy' and 'reset' properties in both host
> bridge and Root Port nodes, though specifying in the host bridge node is
> marked as deprecated. Still, the pcie-qcom driver should support both
> combinations for maintaining the DT backwards compatibility. For this
> purpose, the driver is holding the relevant pointers of these properties in
> two structs: struct qcom_pcie_port and struct qcom_pcie.
>
> However, this causes confusion and increases the driver complexity. Hence,
> move the pointers from struct qcom_pcie to struct qcom_pcie_port. As a
> result, even if these properties are specified in the host bridge node,
> the pointers will be stored in struct qcom_pcie_port as if the properties
> are specified in a single Root Port node. This logic simplifies the driver
> a lot.
> @@ -297,11 +295,8 @@ static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert)
> struct qcom_pcie_port *port;
> int val = assert ? 1 : 0;
>
> - if (list_empty(&pcie->ports))
> - gpiod_set_value_cansleep(pcie->reset, val);
> - else
> - list_for_each_entry(port, &pcie->ports, list)
> - gpiod_set_value_cansleep(port->reset, val);
> + list_for_each_entry(port, &pcie->ports, list)
> + gpiod_set_value_cansleep(port->reset, val);
This is so much nicer, thanks for doing this!
> static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie)
> {
> struct device *dev = pcie->pci->dev;
> + struct qcom_pcie_port *port;
> + struct gpio_desc *reset;
> + struct phy *phy;
> int ret;
>
> - pcie->phy = devm_phy_optional_get(dev, "pciephy");
> - if (IS_ERR(pcie->phy))
> - return PTR_ERR(pcie->phy);
> + phy = devm_phy_optional_get(dev, "pciephy");
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
Seems like it would be easier to integrate this fallback into
qcom_pcie_parse_port() instead if separating it into
qcom_pcie_parse_legacy_binding().
What if you did something like this in qcom_pcie_parse_port():
qcom_pcie_parse_port
{
reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
"reset", GPIOD_OUT_HIGH, "PERST#");
if (IS_ERR(reset)) {
reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
if (IS_ERR(reset))
return PTR_ERR(reset);
}
...
Then you could share all the port kzalloc and port list management.
Could do the same with the PHY stuff.
> - pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> - if (IS_ERR(pcie->reset))
> - return PTR_ERR(pcie->reset);
> + reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> + if (IS_ERR(reset))
> + return PTR_ERR(reset);
>
> - ret = phy_init(pcie->phy);
> + ret = phy_init(phy);
> if (ret)
> return ret;
>
> + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> + if (!port)
> + return -ENOMEM;
> +
> + port->reset = reset;
> + port->phy = phy;
> + INIT_LIST_HEAD(&port->list);
> + list_add_tail(&port->list, &pcie->ports);
> +
> return 0;
> }
next prev parent reply other threads:[~2025-09-12 23:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 8:35 [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available Manivannan Sadhasivam via B4 Relay
2025-09-12 8:35 ` [PATCH v3 1/4] PCI/pwrctrl: Add support for asserting/deasserting PERST# Manivannan Sadhasivam via B4 Relay
2025-09-12 8:35 ` [PATCH v3 2/4] PCI: qcom: Move host bridge 'phy' and 'reset' pointers to struct qcom_pcie_port Manivannan Sadhasivam via B4 Relay
2025-09-12 23:23 ` Bjorn Helgaas [this message]
2025-09-15 13:01 ` Manivannan Sadhasivam
2025-09-16 20:08 ` Bjorn Helgaas
2025-09-17 10:10 ` Manivannan Sadhasivam
2025-09-12 8:35 ` [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes Manivannan Sadhasivam via B4 Relay
2025-09-12 23:28 ` Bjorn Helgaas
2025-09-15 12:53 ` Manivannan Sadhasivam
2025-09-16 19:49 ` Bjorn Helgaas
2025-09-17 10:08 ` Manivannan Sadhasivam
2025-09-12 8:35 ` [PATCH v3 4/4] PCI: qcom: Allow pwrctrl core to control PERST# if 'reset-gpios' property is available Manivannan Sadhasivam via B4 Relay
2025-09-16 20:48 ` Bjorn Helgaas
2025-09-17 10:23 ` Manivannan Sadhasivam
2025-09-18 18:53 ` Bjorn Helgaas
2025-09-19 8:15 ` Manivannan Sadhasivam
2025-09-22 16:00 ` Bjorn Helgaas
2025-09-22 16:33 ` Manivannan Sadhasivam
2025-09-17 10:10 ` (subset) [PATCH v3 0/4] PCI/pwrctrl: Allow pwrctrl framework to control PERST# if available Manivannan Sadhasivam
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