Re: [PATCH v3 3/4] PCI: qcom: Parse PERST# from all PCIe bridge nodes

[Bjorn Helgaas <helgaas@kernel.org>]

On Mon, Sep 15, 2025 at 06:23:45PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Sep 12, 2025 at 06:28:11PM GMT, Bjorn Helgaas wrote:
> > On Fri, Sep 12, 2025 at 02:05:03PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> > > From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> > > 
> > > Devicetree schema allows the PERST# GPIO to be present in all
> > > PCIe bridge nodes, not just in Root Port node. But the current
> > > logic parses PERST# only from the Root Port nodes. Though it is
> > > not causing any issue on the current platforms, the upcoming
> > > platforms will have PERST# in PCIe switch downstream ports also.
> > > So this requires parsing all the PCIe bridge nodes for the
> > > PERST# GPIO.
> > > 
> > > Hence, rework the parsing logic to extend to all PCIe bridge
> > > nodes starting from the Root Port node. If the 'reset-gpios'
> > > property is found for a PCI bridge node, the GPIO descriptor
> > > will be stored in qcom_pcie_perst::desc and added to the
> > > qcom_pcie_port::perst list.
> > 
> > The switch part doesn't seem qcom specific.  Aren't we going to
> > end up with lots of drivers reimplementing something like the
> > qcom_pcie_port.perst list?
> 
> If this kind of switch is attached to other platforms, then yes.
> Right now, Qcom host is the only known DT based host platform that
> has seen this requirement.

So I guess the issue here is that pwrctrl controls power to a slot
below a Switch Downstream Port, and we want pwrctrl to also control
PERST# to that same slot so that pwrctrl can power up the slot and
then deassert PERST# to the slot later, e.g., after a T_PVPERL delay?

Seems like whatever parses the devicetree power regulator information
for the slot should also parse the PERST# GPIO for the slot.

Bjorn