From: Ben Zong-You Xie <ben717@andestech.com>
Cc: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<tglx@linutronix.de>, <daniel.lezcano@linaro.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
"Ben Zong-You Xie" <ben717@andestech.com>
Subject: [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache
Date: Sat, 3 May 2025 23:18:26 +0800 [thread overview]
Message-ID: <20250503151829.605006-7-ben717@andestech.com> (raw)
In-Reply-To: <20250503151829.605006-1-ben717@andestech.com>
The current device tree binding for the Andes AX45MP L2 cache enforces
a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
the QiLai SoC. This change allows both 1024 and 2048 as valid values for
"cache-sets".
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
---
.../devicetree/bindings/cache/andestech,ax45mp-cache.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
index d2cbe49f4e15..798aa71dc4ec 100644
--- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
@@ -44,7 +44,7 @@ properties:
const: 2
cache-sets:
- const: 1024
+ enum: [1024, 2048]
cache-size:
enum: [131072, 262144, 524288, 1048576, 2097152]
--
2.34.1
next prev parent reply other threads:[~2025-05-03 15:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-03 15:18 [PATCH v2 0/9] add Voyager board support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-06 16:24 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-06 16:27 ` Conor Dooley
2025-05-03 15:18 ` Ben Zong-You Xie [this message]
2025-05-06 16:23 ` [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Conor Dooley
2025-05-09 14:57 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-06 16:26 ` Conor Dooley
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