From: Conor Dooley <conor@kernel.org>
To: Ben Zong-You Xie <ben717@andestech.com>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
tglx@linutronix.de, daniel.lezcano@linaro.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, tim609@andestech.com
Subject: Re: [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer
Date: Tue, 6 May 2025 17:27:39 +0100 [thread overview]
Message-ID: <20250506-bonehead-security-fdd71309a721@spud> (raw)
In-Reply-To: <20250503151829.605006-6-ben717@andestech.com>
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On Sat, May 03, 2025 at 11:18:25PM +0800, Ben Zong-You Xie wrote:
> Add the DT binding documentation for Andes machine timer.
>
> The RISC-V architecture defines a machine timer that provides a real-time
> counter and generates timer interrupts. Andes machiner timer (PLMT0) is
> the implementation of the machine timer, and it contains memory-mapped
> registers (mtime and mtimecmp). This device supports up to 32 cores.
>
> Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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next prev parent reply other threads:[~2025-05-06 16:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-03 15:18 [PATCH v2 0/9] add Voyager board support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-06 16:24 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-06 16:27 ` Conor Dooley [this message]
2025-05-03 15:18 ` [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Ben Zong-You Xie
2025-05-06 16:23 ` Conor Dooley
2025-05-09 14:57 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-06 16:26 ` Conor Dooley
-- strict thread matches above, loose matches on Subject: below --
2025-07-11 13:30 [PATCH v2 0/9] add Voyager board support Ben Zong-You Xie
2025-07-11 13:30 ` [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-07-14 16:18 ` Daniel Lezcano
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