From: Conor Dooley <conor@kernel.org>
To: Ben Zong-You Xie <ben717@andestech.com>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
tglx@linutronix.de, daniel.lezcano@linaro.org,
prabhakar.mahadev-lad.rj@bp.renesas.com, tim609@andestech.com
Subject: Re: [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache
Date: Fri, 9 May 2025 15:57:36 +0100 [thread overview]
Message-ID: <20250509-anatomy-marry-a4e1513c613e@spud> (raw)
In-Reply-To: <20250506-clammy-punctuate-6cb07dd0e81e@spud>
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On Tue, May 06, 2025 at 05:23:21PM +0100, Conor Dooley wrote:
> On Sat, May 03, 2025 at 11:18:26PM +0800, Ben Zong-You Xie wrote:
> > The current device tree binding for the Andes AX45MP L2 cache enforces
> > a fixed number of cache-sets (1024). However, there are 2048 cache-sets in
> > the QiLai SoC. This change allows both 1024 and 2048 as valid values for
> > "cache-sets".
> >
> > Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
> > Acked-by: Rob Herring (Arm) <robh@kernel.org>
>
> Applied, thanks.
You know what, I am starting to have second thoughts here. Why does the
qilai not have a specific compatible like the plic etc? I think you
should have one, and only allow the 2048 cache-sets there. I'm going to
go and drop this patch, and please do that for the next version.
Prabhakar, should we add a specific one for the rz/five too?
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next prev parent reply other threads:[~2025-05-09 14:57 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-03 15:18 [PATCH v2 0/9] add Voyager board support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-06 16:24 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-06 16:27 ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Ben Zong-You Xie
2025-05-06 16:23 ` Conor Dooley
2025-05-09 14:57 ` Conor Dooley [this message]
2025-05-03 15:18 ` [PATCH v2 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 8/9] riscv: dts: andes: add Voyager board " Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-06 16:26 ` Conor Dooley
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