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From: Ben Zong-You Xie <ben717@andestech.com>
Cc: <devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <alex@ghiti.fr>,
	<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
	<tglx@linutronix.de>, <daniel.lezcano@linaro.org>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
	"Ben Zong-You Xie" <ben717@andestech.com>
Subject: [PATCH v2 8/9] riscv: dts: andes: add Voyager board device tree
Date: Sat, 3 May 2025 23:18:28 +0800	[thread overview]
Message-ID: <20250503151829.605006-9-ben717@andestech.com> (raw)
In-Reply-To: <20250503151829.605006-1-ben717@andestech.com>

Introduce the device tree support for Voyager development board.

Currently only support booting into console with only uart,
other features will be added later.

Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
---
 arch/riscv/boot/dts/Makefile                |  1 +
 arch/riscv/boot/dts/andes/Makefile          |  2 ++
 arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++++++++++++++++++++
 3 files changed, 31 insertions(+)
 create mode 100644 arch/riscv/boot/dts/andes/Makefile
 create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index 64a898da9aee..3b99e91efa25 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
+subdir-y += andes
 subdir-y += canaan
 subdir-y += microchip
 subdir-y += renesas
diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes/Makefile
new file mode 100644
index 000000000000..c545c668ef70
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ANDES) += qilai-voyager.dtb
diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/dts/andes/qilai-voyager.dts
new file mode 100644
index 000000000000..fa7d2b32a9b4
--- /dev/null
+++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 Andes Technology Corporation. All rights reserved.
+ */
+
+#include "qilai.dtsi"
+
+/ {
+	model = "Voyager";
+	compatible = "andestech,voyager", "andestech,qilai";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@400000000 {
+		device_type = "memory";
+		reg = <0x4 0x00000000 0x4 0x00000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
-- 
2.34.1

  parent reply	other threads:[~2025-05-03 15:45 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-03 15:18 [PATCH v2 0/9] add Voyager board support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Ben Zong-You Xie
2025-05-03 15:18 ` [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Ben Zong-You Xie
2025-05-06 16:24   ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Ben Zong-You Xie
2025-05-06 16:27   ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 6/9] dt-bindings: cache: ax45mp-cache: allow variable cache-sets for Andes L2 cache Ben Zong-You Xie
2025-05-06 16:23   ` Conor Dooley
2025-05-09 14:57     ` Conor Dooley
2025-05-03 15:18 ` [PATCH v2 7/9] riscv: dts: andes: add QiLai SoC device tree Ben Zong-You Xie
2025-05-03 15:18 ` Ben Zong-You Xie [this message]
2025-05-03 15:18 ` [PATCH v2 9/9] riscv: defconfig: enable Andes SoC Ben Zong-You Xie
2025-05-06 16:26   ` Conor Dooley

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