* [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
2026-04-30 10:30 [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
@ 2026-04-30 10:30 ` Yixun Lan
2026-04-30 18:55 ` Conor Dooley
2026-04-30 10:30 ` [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Yixun Lan
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Yixun Lan @ 2026-04-30 10:30 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Inochi Amaoto, Krzysztof Kozlowski, linux-clk, linux-riscv,
devicetree, spacemit, linux-kernel, Yixun Lan
Add clock IDs of PCIe DBI (Data Bus Interface) clock.
Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h
index b22336f3ae40..dfae52547cda 100644
--- a/include/dt-bindings/clock/spacemit,k3-clocks.h
+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h
@@ -380,6 +380,11 @@
#define CLK_APMU_ISIM_VCLK1 86
#define CLK_APMU_ISIM_VCLK2 87
#define CLK_APMU_ISIM_VCLK3 88
+#define CLK_APMU_PCIE_PORTA_DBI 89
+#define CLK_APMU_PCIE_PORTB_DBI 90
+#define CLK_APMU_PCIE_PORTC_DBI 91
+#define CLK_APMU_PCIE_PORTD_DBI 92
+#define CLK_APMU_PCIE_PORTE_DBI 93
/* DCIU clocks */
#define CLK_DCIU_HDMA 0
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
2026-04-30 10:30 ` [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
@ 2026-04-30 18:55 ` Conor Dooley
2026-05-02 11:32 ` Yixun Lan
0 siblings, 1 reply; 9+ messages in thread
From: Conor Dooley @ 2026-04-30 18:55 UTC (permalink / raw)
To: Yixun Lan
Cc: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Krzysztof Kozlowski, linux-clk,
linux-riscv, devicetree, spacemit, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1212 bytes --]
On Thu, Apr 30, 2026 at 10:30:26AM +0000, Yixun Lan wrote:
> Add clock IDs of PCIe DBI (Data Bus Interface) clock.
>
> Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support")
Why is this a fix? As-is, this looks like you're abusing the Fixes tag
so that this gets backported alongside things that are a fix that depend
on it.
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
> include/dt-bindings/clock/spacemit,k3-clocks.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h
> index b22336f3ae40..dfae52547cda 100644
> --- a/include/dt-bindings/clock/spacemit,k3-clocks.h
> +++ b/include/dt-bindings/clock/spacemit,k3-clocks.h
> @@ -380,6 +380,11 @@
> #define CLK_APMU_ISIM_VCLK1 86
> #define CLK_APMU_ISIM_VCLK2 87
> #define CLK_APMU_ISIM_VCLK3 88
> +#define CLK_APMU_PCIE_PORTA_DBI 89
> +#define CLK_APMU_PCIE_PORTB_DBI 90
> +#define CLK_APMU_PCIE_PORTC_DBI 91
> +#define CLK_APMU_PCIE_PORTD_DBI 92
> +#define CLK_APMU_PCIE_PORTE_DBI 93
>
> /* DCIU clocks */
> #define CLK_DCIU_HDMA 0
>
> --
> 2.53.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
2026-04-30 18:55 ` Conor Dooley
@ 2026-05-02 11:32 ` Yixun Lan
0 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2026-05-02 11:32 UTC (permalink / raw)
To: Conor Dooley
Cc: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, Krzysztof Kozlowski, linux-clk,
linux-riscv, devicetree, spacemit, linux-kernel
On 19:55 Thu 30 Apr , Conor Dooley wrote:
> On Thu, Apr 30, 2026 at 10:30:26AM +0000, Yixun Lan wrote:
> > Add clock IDs of PCIe DBI (Data Bus Interface) clock.
> >
> > Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support")
>
> Why is this a fix? As-is, this looks like you're abusing the Fixes tag
> so that this gets backported alongside things that are a fix that depend
> on it.
Ok, will drop the Fixes tag, since the PCIe isn't actually activated yet
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock
2026-04-30 10:30 [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
2026-04-30 10:30 ` [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
@ 2026-04-30 10:30 ` Yixun Lan
2026-05-01 9:28 ` Krzysztof Kozlowski
2026-04-30 10:30 ` [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Yixun Lan
2026-04-30 10:30 ` [PATCH 4/4] clk: spacemit: k3: Fix PCIe clock register offset Yixun Lan
3 siblings, 1 reply; 9+ messages in thread
From: Yixun Lan @ 2026-04-30 10:30 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Inochi Amaoto, Krzysztof Kozlowski, linux-clk, linux-riscv,
devicetree, spacemit, linux-kernel, Yixun Lan
Add PCIe DBI (Data Bus Interface) clock which was missing.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/clk/spacemit/ccu-k3.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index e98afd59f05c..bd60c0d776b4 100644
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -949,14 +949,19 @@ CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT
CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
+CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
+CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
+CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
+CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
+CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
static const struct clk_parent_data emac_1588_parents[] = {
CCU_PARENT_NAME(vctcxo_24m),
@@ -1391,14 +1396,19 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw,
[CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw,
[CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw,
+ [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw,
[CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw,
[CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw,
[CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw,
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock
2026-04-30 10:30 ` [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Yixun Lan
@ 2026-05-01 9:28 ` Krzysztof Kozlowski
2026-05-02 11:30 ` Yixun Lan
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2026-05-01 9:28 UTC (permalink / raw)
To: Yixun Lan, Stephen Boyd, Michael Turquette, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Inochi Amaoto, linux-clk, linux-riscv, devicetree, spacemit,
linux-kernel
On 30/04/2026 12:30, Yixun Lan wrote:
> Add PCIe DBI (Data Bus Interface) clock which was missing.
>
> Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Describe what the bug is in your commit msg.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock
2026-05-01 9:28 ` Krzysztof Kozlowski
@ 2026-05-02 11:30 ` Yixun Lan
0 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2026-05-02 11:30 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Inochi Amaoto, linux-clk, linux-riscv, devicetree,
spacemit, linux-kernel
Hi Krzysztof,
On 11:28 Fri 01 May , Krzysztof Kozlowski wrote:
> On 30/04/2026 12:30, Yixun Lan wrote:
> > Add PCIe DBI (Data Bus Interface) clock which was missing.
> >
> > Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
>
> Describe what the bug is in your commit msg.
Since we've not yet activated the PCIe driver, so this shouldn't cause any
real bug, and as Conor already point out - this is kind of abusing Fixes tag,
so I will drop it in next version.
FYI, for problem I see while testing PCIe driver,
- DBI clock is required in DTS, so it will trigger a check warning
- the DBI clock will be in undetermined state
--
Yixun Lan (dlan)
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
2026-04-30 10:30 [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
2026-04-30 10:30 ` [PATCH 1/4] dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs Yixun Lan
2026-04-30 10:30 ` [PATCH 2/4] clk: spacemit: k3: Add PCIe DBI clock Yixun Lan
@ 2026-04-30 10:30 ` Yixun Lan
2026-04-30 10:30 ` [PATCH 4/4] clk: spacemit: k3: Fix PCIe clock register offset Yixun Lan
3 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2026-04-30 10:30 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Inochi Amaoto, Krzysztof Kozlowski, linux-clk, linux-riscv,
devicetree, spacemit, linux-kernel, Yixun Lan
According to SpacemiT updated docs, the PCIe master and slave clock's
parent is the pll2_d6 clock, so fix it.
Fixes: e371a77255b8 ("clk: spacemit: k3: add the clock tree")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/clk/spacemit/ccu-k3.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c
index bd60c0d776b4..196d32194125 100644
--- a/drivers/clk/spacemit/ccu-k3.c
+++ b/drivers/clk/spacemit/ccu-k3.c
@@ -947,20 +947,20 @@ static const struct clk_parent_data edp1_pclk_parents[] = {
};
CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0);
-CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
-CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
+CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
+CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
-CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
-CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
+CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
+CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
-CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
-CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
+CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
+CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
-CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
-CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
+CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
+CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
-CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
-CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
+CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
+CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
static const struct clk_parent_data emac_1588_parents[] = {
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/4] clk: spacemit: k3: Fix PCIe clock register offset
2026-04-30 10:30 [PATCH 0/4] riscv: spacemit: k3: some clock fixes related to PCIe Yixun Lan
` (2 preceding siblings ...)
2026-04-30 10:30 ` [PATCH 3/4] clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock Yixun Lan
@ 2026-04-30 10:30 ` Yixun Lan
3 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2026-04-30 10:30 UTC (permalink / raw)
To: Stephen Boyd, Michael Turquette, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Inochi Amaoto, Krzysztof Kozlowski, linux-clk, linux-riscv,
devicetree, spacemit, linux-kernel, Yixun Lan
The offset of PCIe Clock CTRL register for port B and C controller was
wrongle swapped, correct it here.
Fixes: 091d19cc2401 ("clk: spacemit: k3: extract common header")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
include/soc/spacemit/k3-syscon.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/soc/spacemit/k3-syscon.h b/include/soc/spacemit/k3-syscon.h
index 0299bea065a0..a68255dd641f 100644
--- a/include/soc/spacemit/k3-syscon.h
+++ b/include/soc/spacemit/k3-syscon.h
@@ -168,8 +168,8 @@
#define APMU_CPU_C2_CLK_CTRL 0x394
#define APMU_CPU_C3_CLK_CTRL 0x208
#define APMU_PCIE_CLK_RES_CTRL_A 0x1f0
-#define APMU_PCIE_CLK_RES_CTRL_B 0x1c8
-#define APMU_PCIE_CLK_RES_CTRL_C 0x1d0
+#define APMU_PCIE_CLK_RES_CTRL_B 0x1d0
+#define APMU_PCIE_CLK_RES_CTRL_C 0x1c8
#define APMU_PCIE_CLK_RES_CTRL_D 0x1e0
#define APMU_PCIE_CLK_RES_CTRL_E 0x1e8
#define APMU_EMAC0_CLK_RES_CTRL 0x3e4
--
2.53.0
^ permalink raw reply related [flat|nested] 9+ messages in thread