* [PATCH] schemas: Allow clocks: property in cache nodes @ 2026-05-03 15:44 Marek Vasut 2026-05-03 18:09 ` Conor Dooley 0 siblings, 1 reply; 3+ messages in thread From: Marek Vasut @ 2026-05-03 15:44 UTC (permalink / raw) To: devicetree Cc: Marek Vasut, Conor Dooley, Geert Uytterhoeven, Krzysztof Kozlowski, Rob Herring, linux-renesas-soc Renesas R-Mobile APE6 currently describes clock which supply the cache controller in their DT using "clocks" property. This is not the only hardware that has cache controller clock controllable via some sort of clock controller, for example Altera SoCFPGA Cyclone V and Arria V also has controllable cache controller clock. Allow clocks: property in cache controller node to allow users to fully describe such hardware. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> --- Cc: Conor Dooley <conor+dt@kernel.org> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- dtschema/schemas/cache.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dtschema/schemas/cache.yaml b/dtschema/schemas/cache.yaml index 73d345f..dee1cd5 100644 --- a/dtschema/schemas/cache.yaml +++ b/dtschema/schemas/cache.yaml @@ -33,6 +33,9 @@ properties: compatible: const: cache + clocks: + maxItems: 1 + power-domains: maxItems: 1 -- 2.53.0 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] schemas: Allow clocks: property in cache nodes 2026-05-03 15:44 [PATCH] schemas: Allow clocks: property in cache nodes Marek Vasut @ 2026-05-03 18:09 ` Conor Dooley 2026-05-04 8:19 ` Geert Uytterhoeven 0 siblings, 1 reply; 3+ messages in thread From: Conor Dooley @ 2026-05-03 18:09 UTC (permalink / raw) To: Marek Vasut Cc: devicetree, Conor Dooley, Geert Uytterhoeven, Krzysztof Kozlowski, Rob Herring, linux-renesas-soc [-- Attachment #1: Type: text/plain, Size: 1392 bytes --] On Sun, May 03, 2026 at 05:44:13PM +0200, Marek Vasut wrote: > Renesas R-Mobile APE6 currently describes clock which supply the cache > controller in their DT using "clocks" property. This is not the only > hardware that has cache controller clock controllable via some sort of > clock controller, for example Altera SoCFPGA Cyclone V and Arria V also > has controllable cache controller clock. Allow clocks: property in cache > controller node to allow users to fully describe such hardware. Hmm, shouldn't these cache controllers have dedicated bindings that enforce their clock requirements? > > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> > --- > Cc: Conor Dooley <conor+dt@kernel.org> > Cc: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> > Cc: Rob Herring <robh@kernel.org> > Cc: devicetree@vger.kernel.org > Cc: linux-renesas-soc@vger.kernel.org > --- > dtschema/schemas/cache.yaml | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/dtschema/schemas/cache.yaml b/dtschema/schemas/cache.yaml > index 73d345f..dee1cd5 100644 > --- a/dtschema/schemas/cache.yaml > +++ b/dtschema/schemas/cache.yaml > @@ -33,6 +33,9 @@ properties: > compatible: > const: cache > > + clocks: > + maxItems: 1 > + > power-domains: > maxItems: 1 > > -- > 2.53.0 > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] schemas: Allow clocks: property in cache nodes 2026-05-03 18:09 ` Conor Dooley @ 2026-05-04 8:19 ` Geert Uytterhoeven 0 siblings, 0 replies; 3+ messages in thread From: Geert Uytterhoeven @ 2026-05-04 8:19 UTC (permalink / raw) To: Conor Dooley Cc: Marek Vasut, devicetree, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-renesas-soc Hi Conor, On Sun, 3 May 2026 at 20:09, Conor Dooley <conor@kernel.org> wrote: > On Sun, May 03, 2026 at 05:44:13PM +0200, Marek Vasut wrote: > > Renesas R-Mobile APE6 currently describes clock which supply the cache > > controller in their DT using "clocks" property. This is not the only > > hardware that has cache controller clock controllable via some sort of > > clock controller, for example Altera SoCFPGA Cyclone V and Arria V also > > has controllable cache controller clock. Allow clocks: property in cache > > controller node to allow users to fully describe such hardware. > > Hmm, shouldn't these cache controllers have dedicated bindings that > enforce their clock requirements? Just a few general comments: - All electronics needs power, so "power-domains" should always be permitted, - All synchronous logic needs a clock, so "clocks" should always be permitteded, - All reasonably complex circuits need a reset, so "resets" should always be permitted. > > Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> As I have sent the same patch before[1]: Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> > > --- a/dtschema/schemas/cache.yaml > > +++ b/dtschema/schemas/cache.yaml > > @@ -33,6 +33,9 @@ properties: > > compatible: > > const: cache > > > > + clocks: > > + maxItems: 1 > > + > > power-domains: > > maxItems: 1 [1] https://lore.kernel.org/20260113075243.1192477-1-geert+renesas@glider.be/ Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-05-04 8:19 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-03 15:44 [PATCH] schemas: Allow clocks: property in cache nodes Marek Vasut 2026-05-03 18:09 ` Conor Dooley 2026-05-04 8:19 ` Geert Uytterhoeven
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