* [PATCH v6 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
The Iris block on SM8350 and SC8280XP is compatible with the Iris
(Venus) on SM8250. Describing in the bindings that the block is Iris v2
and not Venus. Document SM8350 and SC8280XP IP cores, using
qcom,sm8250-venus as a fallback compatible.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,sm8250-venus.yaml | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
index 43a10d9f664e..aca748e42aca 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
@@ -10,15 +10,21 @@ maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
description: |
- The Venus IP is a video encode and decode accelerator present
- on Qualcomm platforms
+ The Iris v2.xx IP is a video encode and decode accelerator present on
+ Qualcomm platforms
allOf:
- $ref: qcom,venus-common.yaml#
properties:
compatible:
- const: qcom,sm8250-venus
+ oneOf:
+ - const: qcom,sm8250-venus
+ - items:
+ - enum:
+ - qcom,sc8280xp-iris
+ - qcom,sm8350-iris
+ - const: qcom,sm8250-venus
power-domains:
minItems: 2
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v6 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Move memory region reserved for the GPU to its proper place in DT.
Fixes: 6e9612ced0c9 ("arm64: dts: qcom: sc8280xp: create common zap-shader node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f47..b09bc6f3b518 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -692,11 +692,6 @@ reserved-region@85b00000 {
no-map;
};
- pil_gpu_mem: gpu-mem@8bf00000 {
- reg = <0 0x8bf00000 0 0x2000>;
- no-map;
- };
-
pil_adsp_mem: adsp-region@86c00000 {
reg = <0 0x86c00000 0 0x2000000>;
no-map;
@@ -712,6 +707,11 @@ pil_nsp0_mem: cdsp0-region@8a100000 {
no-map;
};
+ pil_gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
pil_nsp1_mem: cdsp1-region@8c600000 {
reg = <0 0x8c600000 0 0x1e00000>;
no-map;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
2026-05-14 4:57 ` sashiko-bot
2026-05-13 12:34 ` [PATCH v6 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold, Bryan O'Donoghue, Konrad Dybcio
From: Konrad Dybcio <konradybcio@kernel.org>
Add the required nodes to enable Iris core on SC8280XP.
[ bod: added interconnect tags ]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[ johan: use sm8350 videocc defines ]
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[ bod: dropped video encoder/decoder declarations ]
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
[ db: dropped llcc icc, switched to sc8280xp compat, corrected OPP table ]
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 99 ++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index b09bc6f3b518..4f540f2a0fc8 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -11,13 +11,16 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -692,6 +695,11 @@ reserved-region@85b00000 {
no-map;
};
+ pil_video_mem: pil_video_region@86700000 {
+ reg = <0 0x86700000 0 0x500000>;
+ no-map;
+ };
+
pil_adsp_mem: adsp-region@86c00000 {
reg = <0 0x86c00000 0 0x2000000>;
no-map;
@@ -4182,6 +4190,97 @@ usb_1_dwc3_ss: endpoint {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
+ reg = <0x0 0x0aa00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd SC8280XP_MX>,
+ <&rpmhpd SC8280XP_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mx",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "bus", "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ operating-points-v2 = <&iris_opp_table>;
+ iommus = <&apps_smmu 0x2a00 0x400>;
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sc8280xp-videocc";
+ reg = <0 0x0abf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
cci0: cci@ac4a000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
2026-05-13 12:34 ` [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
@ 2026-05-14 4:57 ` sashiko-bot
0 siblings, 0 replies; 9+ messages in thread
From: sashiko-bot @ 2026-05-14 4:57 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: conor+dt, devicetree, krzk+dt, robh
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] The Venus/Iris driver ignores the `mmcx` power domain, failing to vote for its performance states which will cause MMCX under-voltage and AXI bus hangs at high clock speeds.
- [Low] The `power-domains` property in the `video-codec` node has 4 items, but the YAML binding `qcom,sm8250-venus.yaml` restricts it to a maximum of 3 items.
- [Low] The reserved memory node name 'pil_video_region@86700000' uses underscores instead of hyphens.
--
commit 436af127f4d0421fee1976f98a2eab9818c98aa4
Author: Konrad Dybcio <konradybcio@kernel.org>
arm64: dts: qcom: sc8280xp: Add Iris core
Add the required nodes to enable Iris core on SC8280XP.
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[ ... ]
@@ -691,6 +694,11 @@ reserved-region@85b00000 {
no-map;
};
> + pil_video_mem: pil_video_region@86700000 {
> + reg = <0 0x86700000 0 0x500000>;
> + no-map;
> + };
> +
This isn't a bug, but device tree conventions expect node names to use hyphens
instead of underscores. Should pil_video_region@86700000 be renamed to
pil-video-region@86700000 to avoid dtc W=1 warnings?
[ ... ]
@@ -4181,6 +4189,97 @@ usb_1_dwc3_ss: endpoint {
};
};
> + iris: video-codec@aa00000 {
> + compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
> + reg = <0x0 0x0aa00000 0x0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd SC8280XP_MX>,
> + <&rpmhpd SC8280XP_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx",
> + "mmcx";
Does the YAML binding for qcom,sm8250-venus support 4 power domains?
Without adding a conditional block for qcom,sc8280xp-iris, won't this fail
dtbs_check since the fallback schema restricts power-domains to a maximum
of 3 items (venus, vcodec0, mx)?
Additionally, since this falls back to qcom,sm8250-venus, will the Venus
driver properly attach and vote for the mmcx power domain?
The video codec driver using sm8250 data explicitly defines only mx as the
OPP power domain. As a result, devm_pm_domain_attach_list() might only
attach mx and ignore mmcx.
If mmcx is ignored by the driver, won't it remain permanently at the lowest
statically configured state? When the codec dynamically scales to higher
frequencies (e.g., 560MHz) requiring turbo_l1 for mmcx, could this lead to
hardware under-voltage and AXI bus lockups?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-iris-sc8280xp-v6-0-0d11d90d3e26@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v6 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (2 preceding siblings ...)
2026-05-13 12:34 ` [PATCH v6 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
2026-05-13 12:34 ` [PATCH v6 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov
5 siblings, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold, Bryan O'Donoghue, Konrad Dybcio
From: Konrad Dybcio <konradybcio@kernel.org>
Enable Iris and point the driver to the correct firmware file.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d84ca010ab9d..0eab03495b8a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -932,6 +932,12 @@ keyboard@68 {
};
};
+&iris {
+ firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn";
+
+ status = "okay";
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (3 preceding siblings ...)
2026-05-13 12:34 ` [PATCH v6 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
2026-05-14 5:38 ` sashiko-bot
2026-05-13 12:34 ` [PATCH v6 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov
5 siblings, 1 reply; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Add Iris and video clock controller devices, describing the Iris2 core
present on this platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 81 ++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c830953156ec..2148a140f162 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
@@ -19,6 +20,7 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -2747,6 +2749,85 @@ usb_2_dwc3: usb@a800000 {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sm8350-iris", "qcom,sm8250-venus";
+ reg = <0x0 0x0aa00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MX>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mx",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "bus", "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ operating-points-v2 = <&iris_opp_table>;
+ iommus = <&apps_smmu 0x2100 0x400>;
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sm8350-videocc";
+ reg = <0 0x0abf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8350-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device
2026-05-13 12:34 ` [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
@ 2026-05-14 5:38 ` sashiko-bot
0 siblings, 0 replies; 9+ messages in thread
From: sashiko-bot @ 2026-05-14 5:38 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: krzk+dt, conor+dt, robh, devicetree
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Missing power domain management for `mmcx` in the fallback driver leads to voltage underruns at high frequencies.
- [Medium] Device Tree schema violation: `power-domains` count mismatch for `qcom,sm8250-venus` fallback.
--
commit bd1540a2aea97fb87b08697e9a713ca663a208e8
Author: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
arm64: dts: qcom: sm8350: add Iris device
This commit adds the Iris video codec and video clock controller devices
to the SM8350 device tree, describing the Iris2 core present on this platform.
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 5c8fe213f5e4e..eedf677a7070d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
[ ... ]
> @@ -2745,6 +2747,85 @@ usb_2_dwc3: usb@a800000 {
> };
> };
>
> + iris: video-codec@aa00000 {
> + compatible = "qcom,sm8350-iris", "qcom,sm8250-venus";
> + reg = <0x0 0x0aa00000 0x0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&videocc VIDEO_CC_MVS0C_CLK>,
> + <&videocc VIDEO_CC_MVS0_CLK>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core";
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd RPMHPD_MX>,
> + <&rpmhpd RPMHPD_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx",
> + "mmcx";
Does this configuration violate the device tree schema for the fallback
compatible?
The qcom,sm8250-venus schema limits power-domains to 3 items (venus, vcodec0,
mx). By adding mmcx as a fourth power domain without updating the
qcom,sm8250-venus schema, running make dtbs_check will result in validation
errors.
Furthermore, because the kernel lacks explicit driver match data for
qcom,sm8350-iris, the device will bind using the fallback qcom,sm8250-venus
compatible.
The driver configuration for sm8250 strictly requests and attaches only a
single OPP-scaled power domain (mx), completely ignoring mmcx. This means
mmcx will not be dynamically scaled by the PM OPP core and will remain at its
static initial voltage (likely low_svs, as requested by the videocc clock
controller).
[ ... ]
> + opp-444000000 {
> + opp-hz = /bits/ 64 <444000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_nom>;
> + };
Will this cause a voltage underrun when scaling to higher frequencies?
When the hardware scales to 444MHz, the opp-table mandates that mmcx
requires nom voltage. Running at 444MHz while mmcx is starved at low_svs
due to being unmanaged by the sm8250 driver configuration could lead to
hardware instability, crashes, or synchronous external aborts.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260513-iris-sc8280xp-v6-0-0d11d90d3e26@oss.qualcomm.com?part=5
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v6 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core
2026-05-13 12:34 [PATCH v6 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (4 preceding siblings ...)
2026-05-13 12:34 ` [PATCH v6 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
@ 2026-05-13 12:34 ` Dmitry Baryshkov
5 siblings, 0 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2026-05-13 12:34 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Enable video en/decoder on the SM8350 HDK board. The firmware is not
(yet) a part of linux-firmware and needs to be extracted from Android
data.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 5f975d009465..055fc8ade85a 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -472,6 +472,12 @@ lt9611_out: endpoint {
};
};
+&iris {
+ firmware-name = "qcom/vpu/vpu20_p4_sm8350.mbn";
+
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
--
2.47.3
^ permalink raw reply related [flat|nested] 9+ messages in thread