* [PATCH v7 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
The Iris block on SM8350 and SC8280XP is compatible with the Iris
(Venus) on SM8250. Describing in the bindings that the block is Iris v2
and not Venus. Document SM8350 and SC8280XP IP cores, using
qcom,sm8250-venus as a fallback compatible.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
.../devicetree/bindings/media/qcom,sm8250-venus.yaml | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
index 43a10d9f664e..aca748e42aca 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
@@ -10,15 +10,21 @@ maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
description: |
- The Venus IP is a video encode and decode accelerator present
- on Qualcomm platforms
+ The Iris v2.xx IP is a video encode and decode accelerator present on
+ Qualcomm platforms
allOf:
- $ref: qcom,venus-common.yaml#
properties:
compatible:
- const: qcom,sm8250-venus
+ oneOf:
+ - const: qcom,sm8250-venus
+ - items:
+ - enum:
+ - qcom,sc8280xp-iris
+ - qcom,sm8350-iris
+ - const: qcom,sm8250-venus
power-domains:
minItems: 2
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v7 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Move memory region reserved for the GPU to its proper place in DT.
Fixes: 6e9612ced0c9 ("arm64: dts: qcom: sc8280xp: create common zap-shader node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 761f229e8f47..b09bc6f3b518 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -692,11 +692,6 @@ reserved-region@85b00000 {
no-map;
};
- pil_gpu_mem: gpu-mem@8bf00000 {
- reg = <0 0x8bf00000 0 0x2000>;
- no-map;
- };
-
pil_adsp_mem: adsp-region@86c00000 {
reg = <0 0x86c00000 0 0x2000000>;
no-map;
@@ -712,6 +707,11 @@ pil_nsp0_mem: cdsp0-region@8a100000 {
no-map;
};
+ pil_gpu_mem: gpu-mem@8bf00000 {
+ reg = <0 0x8bf00000 0 0x2000>;
+ no-map;
+ };
+
pil_nsp1_mem: cdsp1-region@8c600000 {
reg = <0 0x8c600000 0 0x1e00000>;
no-map;
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 1/6] media: dt-bindings: Document SC8280XP/SM8350 Iris Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 2/6] arm64: dts: qcom: sc8280xp: sort reserved memory regions Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
2026-05-15 11:42 ` sashiko-bot
2026-05-15 10:56 ` [PATCH v7 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold, Bryan O'Donoghue, Konrad Dybcio
From: Konrad Dybcio <konradybcio@kernel.org>
Add the required nodes to enable Iris core on SC8280XP.
[ bod: added interconnect tags ]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[ johan: use sm8350 videocc defines ]
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
[ bod: dropped video encoder/decoder declarations ]
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
[ db: dropped llcc icc, switched to sc8280xp compat, corrected OPP table ]
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 99 ++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index b09bc6f3b518..092b5c369f95 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -11,13 +11,16 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -692,6 +695,11 @@ reserved-region@85b00000 {
no-map;
};
+ pil_video_mem: video-region@86700000 {
+ reg = <0 0x86700000 0 0x500000>;
+ no-map;
+ };
+
pil_adsp_mem: adsp-region@86c00000 {
reg = <0 0x86c00000 0 0x2000000>;
no-map;
@@ -4182,6 +4190,97 @@ usb_1_dwc3_ss: endpoint {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
+ reg = <0x0 0x0aa00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd SC8280XP_MX>,
+ <&rpmhpd SC8280XP_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mx",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "bus", "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ operating-points-v2 = <&iris_opp_table>;
+ iommus = <&apps_smmu 0x2a00 0x400>;
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533000000 {
+ opp-hz = /bits/ 64 <533000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sc8280xp-videocc";
+ reg = <0 0x0abf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd SC8280XP_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
cci0: cci@ac4a000 {
compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
reg = <0 0x0ac4a000 0 0x1000>;
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
2026-05-15 10:56 ` [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
@ 2026-05-15 11:42 ` sashiko-bot
2026-05-15 12:14 ` Dmitry Baryshkov
0 siblings, 1 reply; 10+ messages in thread
From: sashiko-bot @ 2026-05-15 11:42 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: krzk+dt, devicetree, robh, conor+dt
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `iris` device tree node adds an `mmcx` power domain and two `required-opps` per OPP entry, which violates the fallback compatible's DT binding schema and causes hardware instability due to unhandled power domain scaling.
--
commit 39fd9222ebc24cef337abe30cd891e4af77696e1
Author: Konrad Dybcio <konradybcio@kernel.org>
arm64: dts: qcom: sc8280xp: Add Iris core
Add the required nodes to enable Iris core on SC8280XP.
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 41c57e7dc4333..45e1dd5a230cd 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
[ ... ]
> @@ -4181,6 +4189,97 @@ usb_1_dwc3_ss: endpoint {
> };
> };
>
> + iris: video-codec@aa00000 {
> + compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
> + reg = <0x0 0x0aa00000 0x0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
[ ... ]
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd SC8280XP_MX>,
> + <&rpmhpd SC8280XP_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx",
> + "mmcx";
The qcom,sm8250-venus fallback compatible is used here. Does the
qcom,sm8250-venus.yaml device tree binding schema support a fourth power
domain?
It appears the schema might restrict power-domains to a maximum of 3 items
(venus, vcodec0, mx), which could trigger dtbs_check failures when mmcx
is added.
[ ... ]
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
[ ... ]
> + opp-560000000 {
> + opp-hz = /bits/ 64 <560000000>;
> + required-opps = <&rpmhpd_opp_nom>,
> + <&rpmhpd_opp_turbo_l1>;
> + };
> + };
> + };
When using the qcom,sm8250-venus fallback, the Venus driver currently
configures a single OPP PM domain (mx) via dev_pm_opp_set_config().
Since this node specifies two required-opps per state, will the generic OPP
core skip scaling the mmcx rail? When _set_required_opps() in
drivers/opp/core.c iterates over expected devices, a missing mmcx device
pointer might cause the mmcx rail to remain trapped at the static low_svs
level voted by the videocc node.
If the Venus hardware operates at turbo frequencies (e.g., 560MHz) while mmcx
remains at low_svs, can this undervolt the hardware and cause system
instability?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-iris-sc8280xp-v7-0-2e21f6db1897@oss.qualcomm.com?part=3
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core
2026-05-15 11:42 ` sashiko-bot
@ 2026-05-15 12:14 ` Dmitry Baryshkov
0 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 12:14 UTC (permalink / raw)
To: sashiko-reviews; +Cc: krzk+dt, devicetree, robh, conor+dt
On Fri, May 15, 2026 at 11:42:07AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [High] The `iris` device tree node adds an `mmcx` power domain and two `required-opps` per OPP entry, which violates the fallback compatible's DT binding schema and causes hardware instability due to unhandled power domain scaling.
This comment and the other comment for SM8350: no, it's a part of the
media-pending tree.
> --
>
> commit 39fd9222ebc24cef337abe30cd891e4af77696e1
> Author: Konrad Dybcio <konradybcio@kernel.org>
>
> arm64: dts: qcom: sc8280xp: Add Iris core
>
> Add the required nodes to enable Iris core on SC8280XP.
>
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > index 41c57e7dc4333..45e1dd5a230cd 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> [ ... ]
> > @@ -4181,6 +4189,97 @@ usb_1_dwc3_ss: endpoint {
> > };
> > };
> >
> > + iris: video-codec@aa00000 {
> > + compatible = "qcom,sc8280xp-iris", "qcom,sm8250-venus";
> > + reg = <0x0 0x0aa00000 0x0 0x100000>;
> > + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> [ ... ]
> > + power-domains = <&videocc MVS0C_GDSC>,
> > + <&videocc MVS0_GDSC>,
> > + <&rpmhpd SC8280XP_MX>,
> > + <&rpmhpd SC8280XP_MMCX>;
> > + power-domain-names = "venus",
> > + "vcodec0",
> > + "mx",
> > + "mmcx";
>
> The qcom,sm8250-venus fallback compatible is used here. Does the
> qcom,sm8250-venus.yaml device tree binding schema support a fourth power
> domain?
>
> It appears the schema might restrict power-domains to a maximum of 3 items
> (venus, vcodec0, mx), which could trigger dtbs_check failures when mmcx
> is added.
>
> [ ... ]
> > + iris_opp_table: opp-table {
> > + compatible = "operating-points-v2";
> > +
> > + opp-240000000 {
> > + opp-hz = /bits/ 64 <240000000>;
> > + required-opps = <&rpmhpd_opp_svs>,
> > + <&rpmhpd_opp_low_svs>;
> > + };
> [ ... ]
> > + opp-560000000 {
> > + opp-hz = /bits/ 64 <560000000>;
> > + required-opps = <&rpmhpd_opp_nom>,
> > + <&rpmhpd_opp_turbo_l1>;
> > + };
> > + };
> > + };
>
> When using the qcom,sm8250-venus fallback, the Venus driver currently
> configures a single OPP PM domain (mx) via dev_pm_opp_set_config().
>
> Since this node specifies two required-opps per state, will the generic OPP
> core skip scaling the mmcx rail? When _set_required_opps() in
> drivers/opp/core.c iterates over expected devices, a missing mmcx device
> pointer might cause the mmcx rail to remain trapped at the static low_svs
> level voted by the videocc node.
>
> If the Venus hardware operates at turbo frequencies (e.g., 560MHz) while mmcx
> remains at low_svs, can this undervolt the hardware and cause system
> instability?
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20260515-iris-sc8280xp-v7-0-2e21f6db1897@oss.qualcomm.com?part=3
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (2 preceding siblings ...)
2026-05-15 10:56 ` [PATCH v7 3/6] arm64: dts: qcom: sc8280xp: Add Iris core Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
2026-05-15 10:56 ` [PATCH v7 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov
5 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold, Bryan O'Donoghue, Konrad Dybcio
From: Konrad Dybcio <konradybcio@kernel.org>
Enable Iris and point the driver to the correct firmware file.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index d84ca010ab9d..0eab03495b8a 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -932,6 +932,12 @@ keyboard@68 {
};
};
+&iris {
+ firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcvss8280.mbn";
+
+ status = "okay";
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (3 preceding siblings ...)
2026-05-15 10:56 ` [PATCH v7 4/6] arm64: dts: qcom: sc8280xp-x13s: Enable Iris Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
2026-05-15 12:08 ` sashiko-bot
2026-05-15 10:56 ` [PATCH v7 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core Dmitry Baryshkov
5 siblings, 1 reply; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Add Iris and video clock controller devices, describing the Iris2 core
present on this platform.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 81 ++++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index c830953156ec..2148a140f162 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,sm8350-videocc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
@@ -19,6 +20,7 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
+#include <dt-bindings/reset/qcom,sm8350-videocc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
@@ -2747,6 +2749,85 @@ usb_2_dwc3: usb@a800000 {
};
};
+ iris: video-codec@aa00000 {
+ compatible = "qcom,sm8350-iris", "qcom,sm8250-venus";
+ reg = <0x0 0x0aa00000 0x0 0x100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>;
+ clock-names = "iface",
+ "core",
+ "vcodec0_core";
+ power-domains = <&videocc MVS0C_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MX>,
+ <&rpmhpd RPMHPD_MMCX>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mx",
+ "mmcx";
+
+ resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "bus", "core";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ operating-points-v2 = <&iris_opp_table>;
+ iommus = <&apps_smmu 0x2100 0x400>;
+ memory-region = <&pil_video_mem>;
+
+ status = "disabled";
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ videocc: clock-controller@abf0000 {
+ compatible = "qcom,sm8350-videocc";
+ reg = <0 0x0abf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,sm8350-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device
2026-05-15 10:56 ` [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
@ 2026-05-15 12:08 ` sashiko-bot
0 siblings, 0 replies; 10+ messages in thread
From: sashiko-bot @ 2026-05-15 12:08 UTC (permalink / raw)
To: Dmitry Baryshkov; +Cc: krzk+dt, robh, devicetree, conor+dt
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The fallback driver `qcom,sm8250-venus` lacks support for the `mmcx` power domain, causing silent dynamic voltage scaling failures and hardware instability.
- [Medium] The `video-codec@aa00000` node violates the `qcom,sm8250-venus` DT schema constraints by defining 4 power domains.
--
commit 2b4298f622bad3f707d0f7effff3c5046a527949
Author: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
arm64: dts: qcom: sm8350: add Iris device
This commit adds Iris and video clock controller devices, describing the
Iris2 core present on this platform.
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
[ ... ]
> @@ -2745,6 +2747,85 @@ usb_2_dwc3: usb@a800000 {
[ ... ]
> + iris: video-codec@aa00000 {
> + compatible = "qcom,sm8350-iris", "qcom,sm8250-venus";
> + reg = <0x0 0x0aa00000 0x0 0x100000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
> + <&videocc VIDEO_CC_MVS0C_CLK>,
> + <&videocc VIDEO_CC_MVS0_CLK>;
> + clock-names = "iface",
> + "core",
> + "vcodec0_core";
> + power-domains = <&videocc MVS0C_GDSC>,
> + <&videocc MVS0_GDSC>,
> + <&rpmhpd RPMHPD_MX>,
> + <&rpmhpd RPMHPD_MMCX>;
> + power-domain-names = "venus",
> + "vcodec0",
> + "mx",
> + "mmcx";
The qcom,sm8250-venus schema restricts power-domains to maxItems: 3 and
power-domain-names to venus, vcodec0, and mx. Since this node uses the
qcom,sm8250-venus fallback compatible string and defines 4 power domains
including mmcx, will this cause make dtbs_check to fail with validation
errors?
> +
> + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>,
> + <&videocc VIDEO_CC_MVS0C_CLK_ARES>;
> + reset-names = "bus", "core";
> +
> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> + <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "cpu-cfg",
> + "video-mem";
> +
> + operating-points-v2 = <&iris_opp_table>;
> + iommus = <&apps_smmu 0x2100 0x400>;
> + memory-region = <&pil_video_mem>;
> +
> + status = "disabled";
> +
> + iris_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-240000000 {
> + opp-hz = /bits/ 64 <240000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_low_svs>;
> + };
> +
> + opp-338000000 {
> + opp-hz = /bits/ 64 <338000000>;
> + required-opps = <&rpmhpd_opp_svs>,
> + <&rpmhpd_opp_svs>;
> + };
> +
> + opp-366000000 {
> + opp-hz = /bits/ 64 <366000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-444000000 {
> + opp-hz = /bits/ 64 <444000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>,
> + <&rpmhpd_opp_nom>;
> + };
The iris_opp_table specifies two required-opps for each frequency point to
dynamically scale both the mx and mmcx power domains. However, because a
specific qcom,sm8350-iris driver is not implemented, the kernel will bind
this device to the fallback qcom,sm8250-venus driver.
The qcom,sm8250-venus platform driver data explicitly requests and attaches
only the mx OPP domain, entirely omitting mmcx. During dynamic voltage
scaling, the OPP framework will silently skip casting the second required-opp
vote because the mmcx index in required_devs is NULL.
Will this cause the MMCX voltage to statically remain at its baseline low_svs
while the Iris core runs at high frequencies like 444MHz, potentially leading
to hardware hangs or system crashes?
> + };
> + };
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260515-iris-sc8280xp-v7-0-2e21f6db1897@oss.qualcomm.com?part=5
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 6/6] arm64: dts: qcom: sm8350-hdk: enable Iris core
2026-05-15 10:56 [PATCH v7 0/6] media: iris: enable SM8350 and SC8280XP support Dmitry Baryshkov
` (4 preceding siblings ...)
2026-05-15 10:56 ` [PATCH v7 5/6] arm64: dts: qcom: sm8350: add Iris device Dmitry Baryshkov
@ 2026-05-15 10:56 ` Dmitry Baryshkov
5 siblings, 0 replies; 10+ messages in thread
From: Dmitry Baryshkov @ 2026-05-15 10:56 UTC (permalink / raw)
To: Vikash Garodia, Dikshita Agarwal, Bryan O'Donoghue,
Mauro Carvalho Chehab, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Konrad Dybcio, Abhinav Kumar, Bjorn Andersson,
David Heidelberg, Stanimir Varbanov
Cc: linux-media, linux-arm-msm, devicetree, linux-kernel,
Konrad Dybcio, Johan Hovold
Enable video en/decoder on the SM8350 HDK board. The firmware is not
(yet) a part of linux-firmware and needs to be extracted from Android
data.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 5f975d009465..055fc8ade85a 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -472,6 +472,12 @@ lt9611_out: endpoint {
};
};
+&iris {
+ firmware-name = "qcom/vpu/vpu20_p4_sm8350.mbn";
+
+ status = "okay";
+};
+
&mdss {
status = "okay";
};
--
2.47.3
^ permalink raw reply related [flat|nested] 10+ messages in thread