* [PATCH v2 0/2] arm64: renesas: r8a78000-ironhide: enable SCMI @ 2026-05-19 7:47 Wolfram Sang 2026-05-19 7:47 ` [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes Wolfram Sang 2026-05-19 7:47 ` [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI Wolfram Sang 0 siblings, 2 replies; 7+ messages in thread From: Wolfram Sang @ 2026-05-19 7:47 UTC (permalink / raw) To: linux-renesas-soc Cc: Wolfram Sang, Conor Dooley, devicetree, Geert Uytterhoeven, Krzysztof Kozlowski, Magnus Damm, Rob Herring Here are the DT additions which allow the Renesas R-Car Gen5 board Ironhide to handle clocks via the SCP through SCMI. For that, we enable MFIS controllers, STCM transport nodes, and finally, SCMI. Needs the MFIS driver which is currently in -next. Changes since (internal) v1: * improved comment about transport nodes in patch 1 * fixed abbreviation typo in commit message in patch 2 (Thanks, Marek!) Kuninori Morimoto (2): arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes arm64: renesas: r8a78000-ironhide: enable to use SCMI .../boot/dts/renesas/r8a78000-ironhide.dts | 34 +++++ arch/arm64/boot/dts/renesas/r8a78000.dtsi | 129 +++++++++++++++++- 2 files changed, 160 insertions(+), 3 deletions(-) -- 2.51.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes 2026-05-19 7:47 [PATCH v2 0/2] arm64: renesas: r8a78000-ironhide: enable SCMI Wolfram Sang @ 2026-05-19 7:47 ` Wolfram Sang 2026-05-19 8:05 ` sashiko-bot 2026-05-19 7:47 ` [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI Wolfram Sang 1 sibling, 1 reply; 7+ messages in thread From: Wolfram Sang @ 2026-05-19 7:47 UTC (permalink / raw) To: linux-renesas-soc Cc: Kuninori Morimoto, Vinh Nguyen, Hai Pham, Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Describe the MFIS and MFIS SCP instances which are used for various tasks including inter-processor communication. Remove the PRR node because it is part of MFIS on R-Car X5H and should be handled using the MFIS compatible. Also, describe the STCM transport area used for shared memory mailboxing. Signed-off-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm64/boot/dts/renesas/r8a78000.dtsi | 129 +++++++++++++++++++++- 1 file changed, 126 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi index 3ec1b53d2782..3509d29bfdd8 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi @@ -678,9 +678,123 @@ soc: soc { #size-cells = <2>; ranges; - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; + mfis: system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0 0x189e0000 0 0x1000>, <0 0x18800000 0 0x40000>; + reg-names = "common", "mboxes"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + mfis_scp: system-controller@189e1000 { + compatible = "renesas,r8a78000-mfis-scp"; + reg = <0 0x189e1000 0 0x1000>, <0 0x18840000 0 0x2c000>; + reg-names = "common", "mboxes"; + interrupts = <GIC_ESPI 296 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 298 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 300 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 302 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 304 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 310 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 314 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 316 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 318 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 320 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 322 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 324 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_ESPI 326 IRQ_TYPE_LEVEL_HIGH>, <GIC_ESPI 327 IRQ_TYPE_LEVEL_HIGH>; + /* SCP uses I side IRQ only */ + interrupt-names = "ch0i", "ch1i", "ch2i", "ch3i", "ch4i", "ch5i", "ch6i", "ch7i", + "ch8i", "ch9i", "ch10i", "ch11i", "ch12i", "ch13i", "ch14i", "ch15i", + "ch16i", "ch17i", "ch18i", "ch19i", "ch20i", "ch21i", "ch22i", "ch23i", + "ch24i", "ch25i", "ch26i", "ch27i", "ch28i", "ch29i", "ch30i", "ch31i"; + #mbox-cells = <2>; + #hwlock-cells = <1>; + status = "disabled"; }; /* Application Processors manage View-1 of a GIC-720AE */ @@ -773,6 +887,15 @@ hscif3: serial@c071c000 { clock-names = "fck", "brg_int", "scif_clk"; status = "disabled"; }; + + stcm_transport: sram@c1060000 { + compatible = "mmio-sram"; + reg = <0x0 0xc1060000 0x0 0x1c00>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1060000 0x1c00>; + /* actual transport nodes must be set per board file */ + }; }; timer { -- 2.51.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes 2026-05-19 7:47 ` [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes Wolfram Sang @ 2026-05-19 8:05 ` sashiko-bot 2026-05-19 8:38 ` Wolfram Sang 0 siblings, 1 reply; 7+ messages in thread From: sashiko-bot @ 2026-05-19 8:05 UTC (permalink / raw) To: Wolfram Sang; +Cc: devicetree, wsa+renesas, conor+dt, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] Removing the `prr` node silently breaks SoC revision detection and hardware ID verification in the Renesas SoC initialization driver. -- commit c054ca5a70ce33a42761e6ba3a791607f5814e31 Author: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes This commit describes the MFIS and MFIS SCP instances used for tasks including inter-processor communication. It removes the PRR node, handling it using the MFIS compatible instead, and describes the STCM transport area for shared memory mailboxing. > diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi > index 3e1c98903cea0..d77bed5326832 100644 > --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi > @@ -678,9 +678,123 @@ soc: soc { > #size-cells = <2>; > ranges; > > - prr: chipid@189e0044 { > - compatible = "renesas,prr"; > - reg = <0 0x189e0044 0 4>; > + mfis: system-controller@189e0000 { > + compatible = "renesas,r8a78000-mfis"; Does removing the prr node break SoC revision detection and hardware ID verification in the Renesas SoC initialization driver? The drivers/soc/renesas/renesas-soc.c driver uses the renesas_ids array to find the chip ID register, which currently matches "renesas,prr" and "renesas,bsid". The driver can also fall back to a hardcoded family->reg address, but the fam_rcar_gen5 family structure leaves .reg uninitialized. Since the prr node is replaced with renesas,r8a78000-mfis without updating renesas_ids, will renesas_soc_init() fail to map the chip ID register and skip reading the product register? This would prevent the hardware revision from populating in sysfs (/sys/devices/soc0/revision). -- Sashiko AI review · https://sashiko.dev/#/patchset/20260519074702.3308-4-wsa+renesas@sang-engineering.com?part=1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes 2026-05-19 8:05 ` sashiko-bot @ 2026-05-19 8:38 ` Wolfram Sang 0 siblings, 0 replies; 7+ messages in thread From: Wolfram Sang @ 2026-05-19 8:38 UTC (permalink / raw) To: sashiko-reviews; +Cc: devicetree, conor+dt, robh [-- Attachment #1: Type: text/plain, Size: 349 bytes --] On Tue, May 19, 2026 at 08:05:19AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] Removing the `prr` node silently breaks SoC revision detection and hardware ID verification in the Renesas SoC initialization driver. This is handled in -next properly. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI 2026-05-19 7:47 [PATCH v2 0/2] arm64: renesas: r8a78000-ironhide: enable SCMI Wolfram Sang 2026-05-19 7:47 ` [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes Wolfram Sang @ 2026-05-19 7:47 ` Wolfram Sang 2026-05-19 8:17 ` sashiko-bot 1 sibling, 1 reply; 7+ messages in thread From: Wolfram Sang @ 2026-05-19 7:47 UTC (permalink / raw) To: linux-renesas-soc Cc: Kuninori Morimoto, Wolfram Sang, Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Enable SCMI via MFIS-SCP and STCM transport area to manage clocks. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- .../boot/dts/renesas/r8a78000-ironhide.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts index a721734fbd5d..86bbe5fbb118 100644 --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts @@ -6,6 +6,7 @@ */ /dts-v1/; +#include <dt-bindings/soc/renesas,r8a78000-mfis.h> #include "r8a78000.dtsi" / { @@ -20,6 +21,23 @@ chosen { stdout-path = "serial0:1843200n8"; }; + firmware { + scmi: scmi { + compatible = "arm,scmi"; + mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>, <&mfis_scp 2 MFIS_CHANNEL_RX>; + mbox-names = "tx", "rx"; + shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>; + arm,no-completion-irq; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + memory@60600000 { device_type = "memory"; /* first 518MiB is reserved for other purposes. */ @@ -80,6 +98,22 @@ &hscif0 { status = "okay"; }; +&mfis_scp { + status = "okay"; +}; + &scif_clk { clock-frequency = <26000000>; }; + +&stcm_transport { + scmi_tx_shmem: sram@1200 { + compatible = "arm,scmi-shmem"; + reg = <0x1200 0x0100>; + }; + + scmi_rx_shmem: sram@1300 { + compatible = "arm,scmi-shmem"; + reg = <0x1300 0x100>; + }; +}; -- 2.51.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI 2026-05-19 7:47 ` [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI Wolfram Sang @ 2026-05-19 8:17 ` sashiko-bot 2026-05-19 8:39 ` Wolfram Sang 0 siblings, 1 reply; 7+ messages in thread From: sashiko-bot @ 2026-05-19 8:17 UTC (permalink / raw) To: Wolfram Sang; +Cc: conor+dt, wsa+renesas, devicetree, robh Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The patch adds an include directive for `<dt-bindings/soc/renesas,r8a78000-mfis.h>`, but this header is not included in the commit and does not exist in the repository. -- commit 12e4bb3b81767937e835c191fd20007f6b57db69 Author: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> arm64: renesas: r8a78000-ironhide: enable to use SCMI This commit enables SCMI via MFIS-SCP and the STCM transport area to manage clocks on the r8a78000-ironhide platform. > diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts > index a721734fbd5d0..86bbe5fbb118a 100644 > --- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts > +++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts > @@ -6,6 +6,7 @@ > */ > > /dts-v1/; > +#include <dt-bindings/soc/renesas,r8a78000-mfis.h> Is the dt-bindings/soc/renesas,r8a78000-mfis.h header missing from this patch? The file doesn't seem to be included in the commit or currently present in the repository, which causes a build failure during the C preprocessing step. [ ... ] > @@ -20,6 +21,23 @@ chosen { > stdout-path = "serial0:1843200n8"; > }; > > + firmware { > + scmi: scmi { > + compatible = "arm,scmi"; > + mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>, <&mfis_scp 2 MFIS_CHANNEL_RX>; Are MFIS_CHANNEL_TX and MFIS_CHANNEL_RX defined anywhere else? Without the header file included above, these macros remain undefined. -- Sashiko AI review · https://sashiko.dev/#/patchset/20260519074702.3308-4-wsa+renesas@sang-engineering.com?part=2 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI 2026-05-19 8:17 ` sashiko-bot @ 2026-05-19 8:39 ` Wolfram Sang 0 siblings, 0 replies; 7+ messages in thread From: Wolfram Sang @ 2026-05-19 8:39 UTC (permalink / raw) To: sashiko-reviews; +Cc: conor+dt, devicetree, robh [-- Attachment #1: Type: text/plain, Size: 381 bytes --] On Tue, May 19, 2026 at 08:17:17AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Low] The patch adds an include directive for `<dt-bindings/soc/renesas,r8a78000-mfis.h>`, but this header is not included in the commit and does not exist in the repository. This is handled in -next properly. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 833 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-05-19 8:39 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-19 7:47 [PATCH v2 0/2] arm64: renesas: r8a78000-ironhide: enable SCMI Wolfram Sang 2026-05-19 7:47 ` [PATCH v2 1/2] arm64: renesas: r8a78000: add MFIS, MFIS SCP and transport nodes Wolfram Sang 2026-05-19 8:05 ` sashiko-bot 2026-05-19 8:38 ` Wolfram Sang 2026-05-19 7:47 ` [PATCH v2 2/2] arm64: renesas: r8a78000-ironhide: enable to use SCMI Wolfram Sang 2026-05-19 8:17 ` sashiko-bot 2026-05-19 8:39 ` Wolfram Sang
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