Re: [PATCH 13/22] arm64: dts: qcom: talos: Fix the PCIe iommu-map entries

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Adding the SID mask to `iommu-map` changes the entry size to 5 cells, which misaligns with the PCIe driver's hardcoded 4-cell parsing struct, causing incorrect hardware configuration.
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--- Patch [13]: [PATCH 13/22] arm64: dts: qcom: talos: Fix the PCIe iommu-map entries ---
commit 398a25f1ebfa492fb313949f16b10fc5fb1ad185
Author: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

arm64: dts: qcom: talos: Fix the PCIe iommu-map entries

This commit modifies the PCIe iommu-map entries to add an extra cell (the
SID mask) to match the apps_smmu provider's #iommu-cells property. This
addresses an OF core warning about 1-cell entries targeting 2-cell outputs.

> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
> index fb1bbc51bb8a4..76b1e86b57b07 100644
> --- a/arch/arm64/boot/dts/qcom/talos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi
> @@ -1349,8 +1349,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  					 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
>  			interconnect-names = "pcie-mem", "cpu-pcie";
>  
> -			iommu-map = <0x0 &apps_smmu 0x400 0x1>,
> -				    <0x100 &apps_smmu 0x401 0x1>;
> +			iommu-map = <0x0 &apps_smmu 0x400 0x0 0x1>,
> +				    <0x100 &apps_smmu 0x401 0x0 0x1>;

[Severity: High]
Does adding the SID mask cause a regression in the PCIe controller driver's
parsing of this property?

Looking at drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_config_sid_1_9_0(),
the driver appears to expect each iommu-map entry to be exactly 4 u32 cells:

	struct {
		u32 bdf;
		u32 phandle;
		u32 smmu_sid;
		u32 smmu_sid_len;
	} *map;

When it reads the property into this array via of_property_read_u32_array(),
the new 5-cell entries will cause the parsing to misalign.

For the second entry (BDF 0x100), the driver will read the previous entry's
length (0x1) as the BDF, the rid-base (0x100) as the phandle, and the phandle
as the smmu_sid. Could this result in corrupted hardware programming for downstream
PCIe devices?

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260730-iommu-map-fix-v1-0-83405d37ba41@oss.qualcomm.com?part=13