Re: [PATCH 15/22] arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] Incomplete fix for malformed `iommu-map` entries. The patch series fixes base DTSI files (e.g., `monaco.dtsi`, `lemans.dtsi`) to provide 5-cell `iommu-map` entries when targeting an IOMMU with `#iommu-cells = <2>`. However, it misses board and overlay files that explicitly override `iommu-map` with the old broken 4-cell format. Because these overrides shadow the base DT configuration, compiling these specific boards will still result in the exact same `of: Respect #{iommu,msi}-cells in maps` warning the series intends to resolve.
--

--- Patch [15]: [PATCH 15/22] arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries ---
commit fe3050666c02dc7e846b1c3b4ae001c0063dea37
Author: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>

arm64: dts: qcom: monaco: Fix the PCIe iommu-map entries

This patch updates the PCIe iommu-map entries in monaco.dtsi to use 5 cells,
adding the missing SID mask. This matches the IOMMU provider's
#iommu-cells = <2> property and prevents a warning from the OF core.

> diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
> index e4c8466f941bd..799d13d7558f3 100644
> --- a/arch/arm64/boot/dts/qcom/monaco.dtsi
> +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
> @@ -2349,8 +2349,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>  			interconnect-names = "pcie-mem",
>  					     "cpu-pcie";
>  
> -			iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
> -				    <0x100 &pcie_smmu 0x0001 0x1>;
> +			iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>,
> +				    <0x100 &pcie_smmu 0x0001 0x0 0x1>;

[Severity: Medium]
This isn't a bug introduced by this patch, but this fix appears to be
incomplete. Board and overlay files explicitly override iommu-map using the
old 4-cell format, which will shadow this base DT fix and still trigger the
OF core warning.

For example, in arch/arm64/boot/dts/qcom/monaco-monza-som.dtsi:&pcie0:
    iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,

In arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso:&pcie0:
    iommu-map = <0x0   &pcie_smmu 0x0 0x1>,

And in arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso:&pcie0:
    iommu-map = <0x0 &pcie_smmu 0x0 0x1>,

Should these files also be updated to use the 5-cell format?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260730-iommu-map-fix-v1-0-83405d37ba41@oss.qualcomm.com?part=15