[PATCH 00/25] ARM: rockchip: Add peripheral support for RV1106

[PATCH 00/25] ARM: rockchip: Add peripheral support for RV1106

[Vladislav Leonov]

Basic support for the Rockchip RV1106/RV1103 SoCs currently under review.
This series builds on top of that and enables the peripherals needed to
bring up a board beyond a serial console:

 - CRU reset controller support (dt-bindings + clk driver), needed
   by most of the other peripherals below.
 - Ethernet (GMAC) via dwmac-rk.
 - USB2 PHY and USB3-OTG (DWC3).
 - I2C (rk3x).
 - DMA (PL330) + support DMA for the UART nodes.
 - SPI, including a new SCLK_IN_SPI1 clock gate.
 - RNG.
 - SDMMC1.
 - A dts-only quirk (arm,cpu-registers-not-fw-configured) needed on
   the ARM timer node when booting without a secure firmware that
   pre-configures the CPU timer registers.
 - PWM.

Each new dt-binding is added ahead of the driver and dts nodes that
depend on it, so the series bisects cleanly.

This series depends on:
 - "Add support for the Rockchip RV1106 and RV1103" (v3)
   https://lore.kernel.org/all/20260729133609.3465563-1-sjg@chromium.org

 - "pinctrl: Add support for the Rockchip RV1106" (v3)
   https://lore.kernel.org/all/20260729132736.3807082-1-sjg@chromium.org

Testing: boot-tested on custom RV1106 board, with every peripheral
touched by this series: reset/CRU, Ethernet, USB2 PHY/USB3 DWC3,
I2C, DMA+UART, SPI, RNG, SDMMC1 and PWM - exercised and confirmed working.


Vladislav Leonov (25):
  dt-bindings: reset: Add RV1106 CRU reset definitions
  clk: rockchip: Add reset controller support for RV1106
  ARM: dts: rockchip: Add reset bindings to RV1106
  dt-bindings: net: rockchip-dwmac: add RV1106 compatible
  net: ethernet: stmicro: stmmac: dwmac-rk: Add RV1106 support
  ARM: dts: rockchip: Add Ethernet GMAC node for RV1106
  dt-bindings: phy: rockchip,inno-usb2phy: Add RV1106 compatible
  phy: rockchip: inno-usb2: Add support for RV1106
  dt-bindings: usb: rockchip,dwc3: add RV1106 SoC support
  ARM: dts: rockchip: Add USB2 PHY and USB3-OTG (DWC3) nodes for RV1106
  dt-bindings: i2c: rk3x: Add RV1106 compatible
  ARM: dts: rockchip: Add I2C nodes for RV1106
  ARM: dts: rockchip: Add DMAC node for RV1106
  ARM: dts: rockchip: Add DMA support to UART nodes
  dt-bindings: clock: rockchip: Add SCLK_IN_SPI1 for RV1106
  clk: rockchip: Add SCLK_IN_SPI1 gate for RV1106
  dt-bindings: spi: rockchip: Add RV1106 compatible
  spi: rockchip: Add support for RV1106
  ARM: dts: rockchip: Add SPI nodes for RV1106
  dt-bindings: rng: rockchip: Add RV1106 compatible
  ARM: dts: rockchip: Add RNG node for RV1106
  ARM: dts: rockchip: Add SDMMC1 node for RV1106
  ARM: dts: rockchip: add arm,cpu-registers-not-fw-configured to RV1106
    timer node
  dt-bindings: pwm: rockchip: Add RV1106 compatible
  ARM: dts: rockchip: Add PWM nodes for RV1106

 .../devicetree/bindings/i2c/i2c-rk3x.yaml     |   1 +
 .../bindings/net/rockchip-dwmac.yaml          |   2 +
 .../bindings/phy/rockchip,inno-usb2phy.yaml   |   9 +-
 .../devicetree/bindings/pwm/pwm-rockchip.yaml |   8 +
 .../bindings/rng/rockchip,rk3588-rng.yaml     |  11 +-
 .../devicetree/bindings/spi/spi-rockchip.yaml |   5 +
 .../bindings/usb/rockchip,dwc3.yaml           |  35 +-
 arch/arm/boot/dts/rockchip/rv1106.dtsi        | 426 ++++++++++++++++++
 drivers/clk/rockchip/Makefile                 |   2 +-
 drivers/clk/rockchip/clk-rv1106.c             |   4 +
 drivers/clk/rockchip/clk.h                    |   1 +
 drivers/clk/rockchip/rst-rv1106.c             | 340 ++++++++++++++
 .../net/ethernet/stmicro/stmmac/dwmac-rk.c    |  55 +++
 drivers/phy/rockchip/phy-rockchip-inno-usb2.c |  76 ++++
 drivers/spi/spi-rockchip.c                    |   1 +
 .../dt-bindings/clock/rockchip,rv1106-cru.h   |   2 +
 .../dt-bindings/reset/rockchip,rv1106-cru.h   | 305 +++++++++++++
 17 files changed, 1272 insertions(+), 11 deletions(-)
 create mode 100644 drivers/clk/rockchip/rst-rv1106.c
 create mode 100644 include/dt-bindings/reset/rockchip,rv1106-cru.h

---
base-commit: ac414f5eda0814030636177593400acdacfe5e1e
branch: rv1106

-- 
2.47.3

[PATCH 01/25] dt-bindings: reset: Add RV1106 CRU reset definitions

[Vladislav Leonov]

Add the reset ID definitions for the Rockchip RV1106 clock and
reset unit (CRU), to be used by the reset controller driver and
device tree nodes.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 .../dt-bindings/reset/rockchip,rv1106-cru.h   | 305 ++++++++++++++++++
 1 file changed, 305 insertions(+)
 create mode 100644 include/dt-bindings/reset/rockchip,rv1106-cru.h

diff --git a/include/dt-bindings/reset/rockchip,rv1106-cru.h b/include/dt-bindings/reset/rockchip,rv1106-cru.h
new file mode 100644
index 000000000000..d2567ccda94e
--- /dev/null
+++ b/include/dt-bindings/reset/rockchip,rv1106-cru.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1106_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RV1106_H
+
+/* ==========================list all of reset fields id=========================== */
+
+/* PMU-->SOFTRST_CON00 */
+#define SRST_P_I2C1		0
+#define SRST_I2C1		1
+#define SRST_H_PMU_BIU		2
+#define SRST_P_PMU_BIU		3
+#define SRST_H_PMU_SRAM		4
+#define SRST_PMU_MCU		5
+#define SRST_PMU_MCU_PWRUP	6
+#define SRST_PMU_MCU_CPU	7
+#define SRST_T_PMU_MCU_CPU	8
+
+/* PMU-->SOFTRST_CON01 */
+#define SRST_P_PMU_GPIO0	9
+#define SRST_PMU_GPIO0		10
+#define SRST_PVTM_PMU		11
+#define SRST_P_PVTM_PMU		12
+#define SRST_DDR_FAIL_SAFE	13
+
+/* PMU-->SOFTRST_CON02 */
+#define SRST_P_PMU_HP_TIMER	14
+#define SRST_PMU_HP_TIMER	15
+#define SRST_PMU_32K_HP_TIMER	16
+#define SRST_P_PMU_IOC		17
+#define SRST_P_PMU_CRU		18
+#define SRST_P_PMU_GRF		19
+#define SRST_P_PMU_SGRF		20
+#define SRST_P_PMU_SGRF_REMAP	21
+#define SRST_P_PMU_WDT		22
+#define SRST_T_PMU_WDT		23
+#define SRST_P_PMU_MAILBOX	24
+
+/* TOP-->SOFTRST_CON02 */
+#define SRST_REF_PVTPLL_0	25
+#define SRST_REF_PVTPLL_1	26
+#define SRST_P_CRU		27
+#define SRST_P_CRU_BIU		28
+
+/* PERI-->SOFTRST_CON00 */
+#define SRST_P_PERI_BIU		29
+#define SRST_A_PERI_BIU		30
+#define SRST_H_PERI_BIU		31
+#define SRST_H_BOOTROM		32
+#define SRST_P_TIMER		33
+#define SRST_TIMER0		34
+#define SRST_TIMER1		35
+#define SRST_TIMER2		36
+#define SRST_TIMER3		37
+#define SRST_TIMER4		38
+#define SRST_TIMER5		39
+#define SRST_P_STIMER		40
+
+/* PERI-->SOFTRST_CON01 */
+#define SRST_STIMER0		41
+#define SRST_STIMER1		42
+#define SRST_P_WDT_NS		43
+#define SRST_T_WDT_NS		44
+#define SRST_P_WDT_S		45
+#define SRST_T_WDT_S		46
+#define SRST_P_I2C0		47
+#define SRST_I2C0		48
+#define SRST_P_I2C2		49
+#define SRST_I2C2		50
+#define SRST_P_I2C3		51
+#define SRST_I2C3		52
+#define SRST_P_I2C4		53
+#define SRST_I2C4		54
+
+/* PERI-->SOFTRST_CON02 */
+#define SRST_P_GPIO4		55
+#define SRST_GPIO4		56
+#define SRST_P_PERI_IOC		57
+#define SRST_P_UART2		58
+#define SRST_S_UART2		59
+#define SRST_P_UART3		60
+#define SRST_S_UART3		61
+#define SRST_P_UART4		62
+#define SRST_S_UART4		63
+#define SRST_P_UART5		64
+
+/* PERI-->SOFTRST_CON03 */
+#define SRST_S_UART5		65
+#define SRST_P_SARADC		66
+#define SRST_SARADC		67
+#define SRST_SARADC_PHY		68
+#define SRST_P_SPI1		69
+#define SRST_SPI1		70
+#define SRST_H_TRNG_NS		71
+#define SRST_H_TRNG_S		72
+#define SRST_CORE_CRYPTO	73
+#define SRST_PKA_CRYPTO		74
+#define SRST_A_CRYPTO		75
+#define SRST_H_CRYPTO		76
+#define SRST_P_PWM1_PERI	77
+
+/* PERI-->SOFTRST_CON04 */
+#define SRST_PWM1_PERI		78
+#define SRST_P_PWM2_PERI	79
+#define SRST_PWM2_PERI		80
+#define SRST_P_PERI_GRF		81
+#define SRST_P_PERI_CRU		82
+#define SRST_A_USBOTG		83
+#define SRST_A_BUS_BIU		84
+#define SRST_H_EMMC		85
+#define SRST_H_SFC		86
+
+/* PERI-->SOFTRST_CON05 */
+#define SRST_S_SFC		87
+#define SRST_P_USBPHY		88
+#define SRST_USBPHY_POR		89
+#define SRST_USBPHY_OTG		90
+#define SRST_A_DMAC		91
+#define SRST_A_DECOM		92
+#define SRST_P_DECOM		93
+#define SRST_D_DECOM		94
+#define SRST_P_PERI_SGRF	95
+#define SRST_H_SAI		96
+#define SRST_M_SAI		97
+#define SRST_M_I2S0_8CH_TX	98
+
+/* PERI-->SOFTRST_CON06 */
+#define SRST_H_I2S0		99
+#define SRST_M_DSM		100
+#define SRST_P_DSM		101
+#define SRST_P_ACODEC		102
+#define SRST_M_I2S0_8CH_RX	103
+#define SRST_P_DFT2APB		104
+#define SRST_H_IVE		105
+#define SRST_A_IVE		106
+#define SRST_P_UART0		107
+#define SRST_S_UART0		108
+#define SRST_P_UART1		109
+
+/* PERI-->SOFTRST_CON07 */
+#define SRST_S_UART1		110
+#define SRST_P_PWM0_PERI	111
+#define SRST_PWM0_PERI		112
+
+/* VI-->SOFTRST_CON00 */
+#define SRST_H_VI_BIU		113
+#define SRST_A_VI_BIU		114
+#define SRST_P_VI_BIU		115
+#define SRST_CORE_ISP3P2	116
+#define SRST_D_VICAP		117
+#define SRST_P_VICAP		118
+#define SRST_A_VICAP		119
+#define SRST_H_VICAP		120
+#define SRST_VICAP_I0		121
+#define SRST_VICAP_I1		122
+
+/* VI-->SOFTRST_CON01 */
+#define SRST_VICAP_RX0		123
+#define SRST_VICAP_RX1		124
+#define SRST_VICAP_ISP0		125
+#define SRST_P_CSIHOST0		126
+#define SRST_P_CSIHOST1		127
+#define SRST_H_SDMMC		128
+#define SRST_SDMMC_DETN_FLT	129
+#define SRST_P_MIPICSIPHY	130
+#define SRST_P_GPIO3		131
+
+/* VI-->SOFTRST_CON02 */
+#define SRST_GPIO3		132
+#define SRST_P_VI_IOC		133
+#define SRST_P_VI_GRF		134
+#define SRST_P_VI_SGRF		135
+#define SRST_P_VI_CRU		136
+#define SRST_P_VI_RTC_TEST	137
+#define SRST_P_VI_RTC_NIU	138
+
+/* NPU-->SOFTRST_CON00 */
+#define SRST_H_NPU_BIU		139
+#define SRST_A_NPU_BIU		140
+#define SRST_P_NPU_BIU		141
+#define SRST_P_NPU_CRU		142
+#define SRST_P_NPU_SGRF		143
+#define SRST_P_NPU_GRF		144
+#define SRST_H_RKNN		145
+#define SRST_A_RKNN		146
+
+/* CORE-->SOFTRST_CON00 */
+#define SRST_NCOREPORESET	147
+#define SRST_NCORESET		148
+#define SRST_NDBGRESET		149
+#define SRST_NL2RESET		150
+#define SRST_A_M_CORE_BIU	151
+#define SRST_P_DBG		152
+#define SRST_POT_DBG		153
+#define SRST_NT_DBG		154
+#define SRST_P_CORE_GRF		155
+#define SRST_H_CPU_BIU		156
+#define SRST_P_CPU_BIU		157
+#define SRST_PVTM_CORE		158
+#define SRST_P_PVTM_CORE	159
+
+/* CORE-->SOFTRST_CON01 */
+#define SRST_REF_PVTPLL_CORE	160
+#define SRST_CORE_MCU		161
+#define SRST_CORE_MCU_PWRUP	162
+#define SRST_CORE_MCU_CPU	163
+#define SRST_T_CORE_MCU_CPU	164
+#define SRST_MCU_BIU		165
+#define SRST_P_MAILBOX		166
+#define SRST_P_INTMUX		167
+#define SRST_P_CORE_CRU		168
+#define SRST_P_CORE_SGRF	169
+#define SRST_H_CACHE		170
+
+/* VEPU-->SOFTRST_CON00 */
+#define SRST_H_VEPU_BIU		171
+#define SRST_A_VEPU_BIU		172
+#define SRST_A_VEPU_COM_BIU	173
+#define SRST_P_VEPU_BIU		174
+#define SRST_H_VEPU		175
+#define SRST_A_VEPU		176
+#define SRST_CORE_VEPU		177
+#define SRST_H_VEPU_PP		178
+#define SRST_A_VEPU_PP		179
+#define SRST_CORE_VEPU_DVBM	180
+#define SRST_P_VICAP_VEPU	181
+#define SRST_P_GPIO1		182
+
+/* VEPU-->SOFTRST_CON01 */
+#define SRST_GPIO1		183
+#define SRST_P_VEPU_IOC		184
+#define SRST_P_SPI0		185
+#define SRST_SPI0		186
+#define SRST_P_VEPU_CRU		187
+#define SRST_P_VEPU_SGRF	188
+#define SRST_P_VEPU_GRF		189
+#define SRST_UART_DETN_FLT	190
+
+/* VO-->SOFTRST_CON00 */
+#define SRST_A_VO_BIU		191
+#define SRST_H_VO_BIU		192
+#define SRST_H_RGA2E		193
+#define SRST_A_RGA2E		194
+#define SRST_CORE_RGA2E		195
+#define SRST_P_VO_GRF		196
+#define SRST_A_VOP_BIU		197
+#define SRST_H_VOP		198
+#define SRST_D_VOP		199
+#define SRST_A_VOP		200
+
+/* VO-->SOFTRST_CON01 */
+#define SRST_P_MAC_BIU		201
+#define SRST_A_MAC_BIU		202
+#define SRST_A_MAC		203
+#define SRST_P_VO_SGRF		204
+#define SRST_P_VO_CRU		205
+#define SRST_H_SDIO		206
+
+/* VO-->SOFTRST_CON02 */
+#define SRST_P_TSADC		207
+#define SRST_TSADC		208
+#define SRST_P_OTPC_NS		209
+#define SRST_SBPI_OTPC_NS	210
+#define SRST_USER_OTPC_NS	211
+#define SRST_P_OTPC_S		212
+#define SRST_SBPI_OTPC_S	213
+#define SRST_USER_OTPC_S	214
+#define SRST_OTPC_ARB		215
+#define SRST_MACPHY		216
+#define SRST_P_OTP_MASK		217
+#define SRST_PMC_OTP		218
+
+/* VO-->SOFTRST_CON03 */
+#define SRST_P_GPIO2		219
+#define SRST_GPIO2		220
+#define SRST_P_VO_IOC		221
+
+/* DDR-->SOFTRST_CON00 */
+#define SRST_P_DDR_BIU		222
+#define SRST_P_DDRC		223
+#define SRST_P_DDRMON		224
+#define SRST_TIMER_DDRMON	225
+#define SRST_P_DFICTRL		226
+#define SRST_A_SYS_SHRM		227
+#define SRST_A_SHRM_NIU		228
+#define SRST_P_DDR_GRF		229
+
+/* DDR-->SOFTRST_CON01 */
+#define SRST_P_DDR_CRU		230
+#define SRST_P_DDR_HWLP		231
+#define SRST_P_DDRPHY		232
+
+/* SUBDDR-->SOFTRST_CON00 */
+#define SRST_MSCH_BIU		233
+#define SRST_A_DDRC		234
+#define SRST_CORE_DDRC		235
+#define SRST_DDRMON		236
+#define SRST_DFICTRL		237
+#define SRST_DDR_PHY		238
+
+#endif
-- 
2.47.3

[PATCH 02/25] clk: rockchip: Add reset controller support for RV1106

[Vladislav Leonov]

Implement the reset controller for the RV1106 CRU by wiring up the
software reset registers and exposing them through the reset
framework. Hook the registration into clk-rv1106 and add the
per-register reset lookup table in rst-rv1106.c.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 drivers/clk/rockchip/Makefile     |   2 +-
 drivers/clk/rockchip/clk-rv1106.c |   2 +
 drivers/clk/rockchip/clk.h        |   1 +
 drivers/clk/rockchip/rst-rv1106.c | 340 ++++++++++++++++++++++++++++++
 4 files changed, 344 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/rockchip/rst-rv1106.c

diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 554b7eb83dc9..e511018477f3 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -19,7 +19,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
 
 obj-$(CONFIG_CLK_PX30)          += clk-px30.o
 obj-$(CONFIG_CLK_RV1103B)	+= clk-rv1103b.o
-obj-$(CONFIG_CLK_RV1106)	+= clk-rv1106.o
+obj-$(CONFIG_CLK_RV1106)	+= clk-rv1106.o rst-rv1106.o
 obj-$(CONFIG_CLK_RV110X)        += clk-rv1108.o
 obj-$(CONFIG_CLK_RV1126)        += clk-rv1126.o
 obj-$(CONFIG_CLK_RV1126B)	+= clk-rv1126b.o rst-rv1126b.o
diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
index 3f26573e6cb7..1e3a110192bb 100644
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -1077,6 +1077,8 @@ static int __init clk_rv1106_probe(struct platform_device *pdev)
 					ARRAY_SIZE(rv1106_grf_clk_branches));
 	}
 
+	rv1106_rst_init(np, reg_base);
+
 	rockchip_register_restart_notifier(ctx, RV1106_GLB_SRST_FST, NULL);
 
 	rockchip_clk_of_add_provider(np, ctx);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 9e3503e2ffc2..ef258c77b243 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -1392,6 +1392,7 @@ static inline void rockchip_register_softrst(struct device_node *np,
 	return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
 }
 
+void rv1106_rst_init(struct device_node *np, void __iomem *reg_base);
 void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
 void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
 void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
diff --git a/drivers/clk/rockchip/rst-rv1106.c b/drivers/clk/rockchip/rst-rv1106.c
new file mode 100644
index 000000000000..5055c0a54d3f
--- /dev/null
+++ b/drivers/clk/rockchip/rst-rv1106.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2026 Vladislav Leonov <vlad@zlab.su>
+ * Author: Vladislav Leonov <vlad@zlab.su>
+ * Based on Elaine Zhang's implementation for RV1126B
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <dt-bindings/reset/rockchip,rv1106-cru.h>
+#include "clk.h"
+
+#define SOFTRST_CON(x)	((x) * 0x4 + 0xa00)
+
+/* CRU base 0x00000 (PMU) + 0x0A00 */
+#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit)
+/* CRU base 0x10000 (TOP) + 0x0A00 */
+#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit)
+/* CRU base 0x12000 (PERI) + 0x0A00 */
+#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x12000 * 4 + reg * 16 + bit)
+/* CRU base 0x14000 (VI) + 0x0A00 */
+#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x14000 * 4 + reg * 16 + bit)
+/* CRU base 0x16000 (NPU) + 0x0A00 */
+#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x16000 * 4 + reg * 16 + bit)
+/* CRU base 0x18000 (CORE) + 0x0A00 */
+#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x18000 * 4 + reg * 16 + bit)
+/* CRU base 0x1a000 (VEPU) + 0x0A00 */
+#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x1a000 * 4 + reg * 16 + bit)
+/* CRU base 0x1c000 (VO) + 0x0A00 */
+#define VOCRU_RESET_OFFSET(id, reg, bit) [id] = (0x1c000 * 4 + reg * 16 + bit)
+/* CRU base 0x1e000 (DDR) + 0x0A00 */
+#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x1e000 * 4 + reg * 16 + bit)
+/* CRU base 0x1f000 (SUBDDR) + 0x0A00 */
+#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x1f000 * 4 + reg * 16 + bit)
+
+/* =================mapping table for reset ID to register offset================== */
+static const int rv1106_register_offset[] = {
+	/* PMU-->SOFTRST_CON00 */
+	PMUCRU_RESET_OFFSET(SRST_P_I2C1, 0, 3),
+	PMUCRU_RESET_OFFSET(SRST_I2C1, 0, 4),
+	PMUCRU_RESET_OFFSET(SRST_H_PMU_BIU, 0, 6),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_BIU, 0, 7),
+	PMUCRU_RESET_OFFSET(SRST_H_PMU_SRAM, 0, 8),
+	PMUCRU_RESET_OFFSET(SRST_PMU_MCU, 0, 9),
+	PMUCRU_RESET_OFFSET(SRST_PMU_MCU_PWRUP, 0, 10),
+	PMUCRU_RESET_OFFSET(SRST_PMU_MCU_CPU, 0, 11),
+	PMUCRU_RESET_OFFSET(SRST_T_PMU_MCU_CPU, 0, 12),
+
+	/* PMU-->SOFTRST_CON01 */
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_GPIO0, 1, 2),
+	PMUCRU_RESET_OFFSET(SRST_PMU_GPIO0, 1, 3),
+	PMUCRU_RESET_OFFSET(SRST_PVTM_PMU, 1, 4),
+	PMUCRU_RESET_OFFSET(SRST_P_PVTM_PMU, 1, 5),
+	PMUCRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 15),
+
+	/* PMU-->SOFTRST_CON02 */
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_HP_TIMER, 2, 0),
+	PMUCRU_RESET_OFFSET(SRST_PMU_HP_TIMER, 2, 1),
+	PMUCRU_RESET_OFFSET(SRST_PMU_32K_HP_TIMER, 2, 2),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_IOC, 2, 3),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_CRU, 2, 4),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_GRF, 2, 5),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_SGRF, 2, 6),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_SGRF_REMAP, 2, 7),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_WDT, 2, 8),
+	PMUCRU_RESET_OFFSET(SRST_T_PMU_WDT, 2, 9),
+	PMUCRU_RESET_OFFSET(SRST_P_PMU_MAILBOX, 2, 10),
+
+	/* TOP-->SOFTRST_CON02 */
+	TOPCRU_RESET_OFFSET(SRST_REF_PVTPLL_0, 2, 7),
+	TOPCRU_RESET_OFFSET(SRST_REF_PVTPLL_1, 2, 8),
+	TOPCRU_RESET_OFFSET(SRST_P_CRU, 2, 10),
+	TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 2, 11),
+
+	/* PERI-->SOFTRST_CON00 */
+	PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 0, 4),
+	PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 0, 5),
+	PERICRU_RESET_OFFSET(SRST_H_PERI_BIU, 0, 6),
+	PERICRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7),
+	PERICRU_RESET_OFFSET(SRST_P_TIMER, 0, 8),
+	PERICRU_RESET_OFFSET(SRST_TIMER0, 0, 9),
+	PERICRU_RESET_OFFSET(SRST_TIMER1, 0, 10),
+	PERICRU_RESET_OFFSET(SRST_TIMER2, 0, 11),
+	PERICRU_RESET_OFFSET(SRST_TIMER3, 0, 12),
+	PERICRU_RESET_OFFSET(SRST_TIMER4, 0, 13),
+	PERICRU_RESET_OFFSET(SRST_TIMER5, 0, 14),
+	PERICRU_RESET_OFFSET(SRST_P_STIMER, 0, 15),
+
+	/* PERI-->SOFTRST_CON01 */
+	PERICRU_RESET_OFFSET(SRST_STIMER0, 1, 0),
+	PERICRU_RESET_OFFSET(SRST_STIMER1, 1, 1),
+	PERICRU_RESET_OFFSET(SRST_P_WDT_NS, 1, 2),
+	PERICRU_RESET_OFFSET(SRST_T_WDT_NS, 1, 3),
+	PERICRU_RESET_OFFSET(SRST_P_WDT_S, 1, 4),
+	PERICRU_RESET_OFFSET(SRST_T_WDT_S, 1, 5),
+	PERICRU_RESET_OFFSET(SRST_P_I2C0, 1, 6),
+	PERICRU_RESET_OFFSET(SRST_I2C0, 1, 7),
+	PERICRU_RESET_OFFSET(SRST_P_I2C2, 1, 10),
+	PERICRU_RESET_OFFSET(SRST_I2C2, 1, 11),
+	PERICRU_RESET_OFFSET(SRST_P_I2C3, 1, 12),
+	PERICRU_RESET_OFFSET(SRST_I2C3, 1, 13),
+	PERICRU_RESET_OFFSET(SRST_P_I2C4, 1, 14),
+	PERICRU_RESET_OFFSET(SRST_I2C4, 1, 15),
+
+	/* PERI-->SOFTRST_CON02 */
+	PERICRU_RESET_OFFSET(SRST_P_GPIO4, 2, 0),
+	PERICRU_RESET_OFFSET(SRST_GPIO4, 2, 1),
+	PERICRU_RESET_OFFSET(SRST_P_PERI_IOC, 2, 2),
+	PERICRU_RESET_OFFSET(SRST_P_UART2, 2, 3),
+	PERICRU_RESET_OFFSET(SRST_S_UART2, 2, 6),
+	PERICRU_RESET_OFFSET(SRST_P_UART3, 2, 7),
+	PERICRU_RESET_OFFSET(SRST_S_UART3, 2, 10),
+	PERICRU_RESET_OFFSET(SRST_P_UART4, 2, 11),
+	PERICRU_RESET_OFFSET(SRST_S_UART4, 2, 14),
+	PERICRU_RESET_OFFSET(SRST_P_UART5, 2, 15),
+
+	/* PERI-->SOFTRST_CON03 */
+	PERICRU_RESET_OFFSET(SRST_S_UART5, 3, 2),
+	PERICRU_RESET_OFFSET(SRST_P_SARADC, 3, 3),
+	PERICRU_RESET_OFFSET(SRST_SARADC, 3, 4),
+	PERICRU_RESET_OFFSET(SRST_SARADC_PHY, 3, 5),
+	PERICRU_RESET_OFFSET(SRST_P_SPI1, 3, 6),
+	PERICRU_RESET_OFFSET(SRST_SPI1, 3, 7),
+	PERICRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 9),
+	PERICRU_RESET_OFFSET(SRST_H_TRNG_S, 3, 10),
+	PERICRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 11),
+	PERICRU_RESET_OFFSET(SRST_PKA_CRYPTO, 3, 12),
+	PERICRU_RESET_OFFSET(SRST_A_CRYPTO, 3, 13),
+	PERICRU_RESET_OFFSET(SRST_H_CRYPTO, 3, 14),
+	PERICRU_RESET_OFFSET(SRST_P_PWM1_PERI, 3, 15),
+
+	/* PERI-->SOFTRST_CON04 */
+	PERICRU_RESET_OFFSET(SRST_PWM1_PERI, 4, 0),
+	PERICRU_RESET_OFFSET(SRST_P_PWM2_PERI, 4, 2),
+	PERICRU_RESET_OFFSET(SRST_PWM2_PERI, 4, 3),
+	PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 4, 5),
+	PERICRU_RESET_OFFSET(SRST_P_PERI_CRU, 4, 6),
+	PERICRU_RESET_OFFSET(SRST_A_USBOTG, 4, 7),
+	PERICRU_RESET_OFFSET(SRST_A_BUS_BIU, 4, 10),
+	PERICRU_RESET_OFFSET(SRST_H_EMMC, 4, 13),
+	PERICRU_RESET_OFFSET(SRST_H_SFC, 4, 14),
+
+	/* PERI-->SOFTRST_CON05 */
+	PERICRU_RESET_OFFSET(SRST_S_SFC, 5, 0),
+	PERICRU_RESET_OFFSET(SRST_P_USBPHY, 5, 1),
+	PERICRU_RESET_OFFSET(SRST_USBPHY_POR, 5, 2),
+	PERICRU_RESET_OFFSET(SRST_USBPHY_OTG, 5, 3),
+	PERICRU_RESET_OFFSET(SRST_A_DMAC, 5, 8),
+	PERICRU_RESET_OFFSET(SRST_A_DECOM, 5, 9),
+	PERICRU_RESET_OFFSET(SRST_P_DECOM, 5, 10),
+	PERICRU_RESET_OFFSET(SRST_D_DECOM, 5, 11),
+	PERICRU_RESET_OFFSET(SRST_P_PERI_SGRF, 5, 12),
+	PERICRU_RESET_OFFSET(SRST_H_SAI, 5, 13),
+	PERICRU_RESET_OFFSET(SRST_M_SAI, 5, 14),
+	PERICRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 5, 15),
+
+	/* PERI-->SOFTRST_CON06 */
+	PERICRU_RESET_OFFSET(SRST_H_I2S0, 6, 0),
+	PERICRU_RESET_OFFSET(SRST_M_DSM, 6, 1),
+	PERICRU_RESET_OFFSET(SRST_P_DSM, 6, 2),
+	PERICRU_RESET_OFFSET(SRST_P_ACODEC, 6, 3),
+	PERICRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 6, 6),
+	PERICRU_RESET_OFFSET(SRST_P_DFT2APB, 6, 7),
+	PERICRU_RESET_OFFSET(SRST_H_IVE, 6, 9),
+	PERICRU_RESET_OFFSET(SRST_A_IVE, 6, 10),
+	PERICRU_RESET_OFFSET(SRST_P_UART0, 6, 11),
+	PERICRU_RESET_OFFSET(SRST_S_UART0, 6, 14),
+	PERICRU_RESET_OFFSET(SRST_P_UART1, 6, 15),
+
+	/* PERI-->SOFTRST_CON07 */
+	PERICRU_RESET_OFFSET(SRST_S_UART1, 7, 2),
+	PERICRU_RESET_OFFSET(SRST_P_PWM0_PERI, 7, 3),
+	PERICRU_RESET_OFFSET(SRST_PWM0_PERI, 7, 4),
+
+	/* VI-->SOFTRST_CON00 */
+	VICRU_RESET_OFFSET(SRST_H_VI_BIU, 0, 4),
+	VICRU_RESET_OFFSET(SRST_A_VI_BIU, 0, 5),
+	VICRU_RESET_OFFSET(SRST_P_VI_BIU, 0, 6),
+	VICRU_RESET_OFFSET(SRST_CORE_ISP3P2, 0, 9),
+	VICRU_RESET_OFFSET(SRST_D_VICAP, 0, 10),
+	VICRU_RESET_OFFSET(SRST_P_VICAP, 0, 11),
+	VICRU_RESET_OFFSET(SRST_A_VICAP, 0, 12),
+	VICRU_RESET_OFFSET(SRST_H_VICAP, 0, 13),
+	VICRU_RESET_OFFSET(SRST_VICAP_I0, 0, 14),
+	VICRU_RESET_OFFSET(SRST_VICAP_I1, 0, 15),
+
+	/* VI-->SOFTRST_CON01 */
+	VICRU_RESET_OFFSET(SRST_VICAP_RX0, 1, 0),
+	VICRU_RESET_OFFSET(SRST_VICAP_RX1, 1, 1),
+	VICRU_RESET_OFFSET(SRST_VICAP_ISP0, 1, 2),
+	VICRU_RESET_OFFSET(SRST_P_CSIHOST0, 1, 4),
+	VICRU_RESET_OFFSET(SRST_P_CSIHOST1, 1, 6),
+	VICRU_RESET_OFFSET(SRST_H_SDMMC, 1, 12),
+	VICRU_RESET_OFFSET(SRST_SDMMC_DETN_FLT, 1, 13),
+	VICRU_RESET_OFFSET(SRST_P_MIPICSIPHY, 1, 14),
+	VICRU_RESET_OFFSET(SRST_P_GPIO3, 1, 15),
+
+	/* VI-->SOFTRST_CON02 */
+	VICRU_RESET_OFFSET(SRST_GPIO3, 2, 0),
+	VICRU_RESET_OFFSET(SRST_P_VI_IOC, 2, 1),
+	VICRU_RESET_OFFSET(SRST_P_VI_GRF, 2, 2),
+	VICRU_RESET_OFFSET(SRST_P_VI_SGRF, 2, 3),
+	VICRU_RESET_OFFSET(SRST_P_VI_CRU, 2, 4),
+	VICRU_RESET_OFFSET(SRST_P_VI_RTC_TEST, 2, 5),
+	VICRU_RESET_OFFSET(SRST_P_VI_RTC_NIU, 2, 7),
+
+	/* NPU-->SOFTRST_CON00 */
+	NPUCRU_RESET_OFFSET(SRST_H_NPU_BIU, 0, 3),
+	NPUCRU_RESET_OFFSET(SRST_A_NPU_BIU, 0, 4),
+	NPUCRU_RESET_OFFSET(SRST_P_NPU_BIU, 0, 5),
+	NPUCRU_RESET_OFFSET(SRST_P_NPU_CRU, 0, 6),
+	NPUCRU_RESET_OFFSET(SRST_P_NPU_SGRF, 0, 7),
+	NPUCRU_RESET_OFFSET(SRST_P_NPU_GRF, 0, 8),
+	NPUCRU_RESET_OFFSET(SRST_H_RKNN, 0, 9),
+	NPUCRU_RESET_OFFSET(SRST_A_RKNN, 0, 10),
+
+	/* CORE-->SOFTRST_CON00 */
+	CORECRU_RESET_OFFSET(SRST_NCOREPORESET, 0, 1),
+	CORECRU_RESET_OFFSET(SRST_NCORESET, 0, 2),
+	CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 3),
+	CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 4),
+	CORECRU_RESET_OFFSET(SRST_A_M_CORE_BIU, 0, 5),
+	CORECRU_RESET_OFFSET(SRST_P_DBG, 0, 6),
+	CORECRU_RESET_OFFSET(SRST_POT_DBG, 0, 7),
+	CORECRU_RESET_OFFSET(SRST_NT_DBG, 0, 8),
+	CORECRU_RESET_OFFSET(SRST_P_CORE_GRF, 0, 11),
+	CORECRU_RESET_OFFSET(SRST_H_CPU_BIU, 0, 12),
+	CORECRU_RESET_OFFSET(SRST_P_CPU_BIU, 0, 13),
+	CORECRU_RESET_OFFSET(SRST_PVTM_CORE, 0, 14),
+	CORECRU_RESET_OFFSET(SRST_P_PVTM_CORE, 0, 15),
+
+	/* CORE-->SOFTRST_CON01 */
+	CORECRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 1, 0),
+	CORECRU_RESET_OFFSET(SRST_CORE_MCU, 1, 1),
+	CORECRU_RESET_OFFSET(SRST_CORE_MCU_PWRUP, 1, 2),
+	CORECRU_RESET_OFFSET(SRST_CORE_MCU_CPU, 1, 3),
+	CORECRU_RESET_OFFSET(SRST_T_CORE_MCU_CPU, 1, 4),
+	CORECRU_RESET_OFFSET(SRST_MCU_BIU, 1, 5),
+	CORECRU_RESET_OFFSET(SRST_P_MAILBOX, 1, 8),
+	CORECRU_RESET_OFFSET(SRST_P_INTMUX, 1, 9),
+	CORECRU_RESET_OFFSET(SRST_P_CORE_CRU, 1, 10),
+	CORECRU_RESET_OFFSET(SRST_P_CORE_SGRF, 1, 11),
+	CORECRU_RESET_OFFSET(SRST_H_CACHE, 1, 12),
+
+	/* VEPU-->SOFTRST_CON00 */
+	VEPUCRU_RESET_OFFSET(SRST_H_VEPU_BIU, 0, 4),
+	VEPUCRU_RESET_OFFSET(SRST_A_VEPU_BIU, 0, 5),
+	VEPUCRU_RESET_OFFSET(SRST_A_VEPU_COM_BIU, 0, 6),
+	VEPUCRU_RESET_OFFSET(SRST_P_VEPU_BIU, 0, 7),
+	VEPUCRU_RESET_OFFSET(SRST_H_VEPU, 0, 8),
+	VEPUCRU_RESET_OFFSET(SRST_A_VEPU, 0, 9),
+	VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU, 0, 10),
+	VEPUCRU_RESET_OFFSET(SRST_H_VEPU_PP, 0, 11),
+	VEPUCRU_RESET_OFFSET(SRST_A_VEPU_PP, 0, 12),
+	VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU_DVBM, 0, 13),
+	VEPUCRU_RESET_OFFSET(SRST_P_VICAP_VEPU, 0, 14),
+	VEPUCRU_RESET_OFFSET(SRST_P_GPIO1, 0, 15),
+
+	/* VEPU-->SOFTRST_CON01 */
+	VEPUCRU_RESET_OFFSET(SRST_GPIO1, 1, 0),
+	VEPUCRU_RESET_OFFSET(SRST_P_VEPU_IOC, 1, 1),
+	VEPUCRU_RESET_OFFSET(SRST_P_SPI0, 1, 2),
+	VEPUCRU_RESET_OFFSET(SRST_SPI0, 1, 3),
+	VEPUCRU_RESET_OFFSET(SRST_P_VEPU_CRU, 1, 5),
+	VEPUCRU_RESET_OFFSET(SRST_P_VEPU_SGRF, 1, 6),
+	VEPUCRU_RESET_OFFSET(SRST_P_VEPU_GRF, 1, 7),
+	VEPUCRU_RESET_OFFSET(SRST_UART_DETN_FLT, 1, 8),
+
+	/* VO-->SOFTRST_CON00 */
+	VOCRU_RESET_OFFSET(SRST_A_VO_BIU, 0, 3),
+	VOCRU_RESET_OFFSET(SRST_H_VO_BIU, 0, 4),
+	VOCRU_RESET_OFFSET(SRST_H_RGA2E, 0, 7),
+	VOCRU_RESET_OFFSET(SRST_A_RGA2E, 0, 8),
+	VOCRU_RESET_OFFSET(SRST_CORE_RGA2E, 0, 9),
+	VOCRU_RESET_OFFSET(SRST_P_VO_GRF, 0, 10),
+	VOCRU_RESET_OFFSET(SRST_A_VOP_BIU, 0, 12),
+	VOCRU_RESET_OFFSET(SRST_H_VOP, 0, 13),
+	VOCRU_RESET_OFFSET(SRST_D_VOP, 0, 14),
+	VOCRU_RESET_OFFSET(SRST_A_VOP, 0, 15),
+
+	/* VO-->SOFTRST_CON01 */
+	VOCRU_RESET_OFFSET(SRST_P_MAC_BIU, 1, 6),
+	VOCRU_RESET_OFFSET(SRST_A_MAC_BIU, 1, 7),
+	VOCRU_RESET_OFFSET(SRST_A_MAC, 1, 8),
+	VOCRU_RESET_OFFSET(SRST_P_VO_SGRF, 1, 12),
+	VOCRU_RESET_OFFSET(SRST_P_VO_CRU, 1, 13),
+	VOCRU_RESET_OFFSET(SRST_H_SDIO, 1, 15),
+
+	/* VO-->SOFTRST_CON02 */
+	VOCRU_RESET_OFFSET(SRST_P_TSADC, 2, 0),
+	VOCRU_RESET_OFFSET(SRST_TSADC, 2, 1),
+	VOCRU_RESET_OFFSET(SRST_P_OTPC_NS, 2, 3),
+	VOCRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 2, 5),
+	VOCRU_RESET_OFFSET(SRST_USER_OTPC_NS, 2, 6),
+	VOCRU_RESET_OFFSET(SRST_P_OTPC_S, 2, 7),
+	VOCRU_RESET_OFFSET(SRST_SBPI_OTPC_S, 2, 9),
+	VOCRU_RESET_OFFSET(SRST_USER_OTPC_S, 2, 10),
+	VOCRU_RESET_OFFSET(SRST_OTPC_ARB, 2, 11),
+	VOCRU_RESET_OFFSET(SRST_MACPHY, 2, 13),
+	VOCRU_RESET_OFFSET(SRST_P_OTP_MASK, 2, 14),
+	VOCRU_RESET_OFFSET(SRST_PMC_OTP, 2, 15),
+
+	/* VO-->SOFTRST_CON03 */
+	VOCRU_RESET_OFFSET(SRST_P_GPIO2, 3, 0),
+	VOCRU_RESET_OFFSET(SRST_GPIO2, 3, 1),
+	VOCRU_RESET_OFFSET(SRST_P_VO_IOC, 3, 2),
+
+	/* DDR-->SOFTRST_CON00 */
+	DDRCRU_RESET_OFFSET(SRST_P_DDR_BIU, 0, 2),
+	DDRCRU_RESET_OFFSET(SRST_P_DDRC, 0, 5),
+	DDRCRU_RESET_OFFSET(SRST_P_DDRMON, 0, 7),
+	DDRCRU_RESET_OFFSET(SRST_TIMER_DDRMON, 0, 8),
+	DDRCRU_RESET_OFFSET(SRST_P_DFICTRL, 0, 11),
+	DDRCRU_RESET_OFFSET(SRST_A_SYS_SHRM, 0, 13),
+	DDRCRU_RESET_OFFSET(SRST_A_SHRM_NIU, 0, 14),
+	DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 0, 15),
+
+	/* DDR-->SOFTRST_CON01 */
+	DDRCRU_RESET_OFFSET(SRST_P_DDR_CRU, 1, 0),
+	DDRCRU_RESET_OFFSET(SRST_P_DDR_HWLP, 1, 2),
+	DDRCRU_RESET_OFFSET(SRST_P_DDRPHY, 1, 3),
+
+	/* SUBDDR-->SOFTRST_CON00 */
+	SUBDDRCRU_RESET_OFFSET(SRST_MSCH_BIU, 0, 0),
+	SUBDDRCRU_RESET_OFFSET(SRST_A_DDRC, 0, 1),
+	SUBDDRCRU_RESET_OFFSET(SRST_CORE_DDRC, 0, 3),
+	SUBDDRCRU_RESET_OFFSET(SRST_DDRMON, 0, 4),
+	SUBDDRCRU_RESET_OFFSET(SRST_DFICTRL, 0, 5),
+	SUBDDRCRU_RESET_OFFSET(SRST_DDR_PHY, 0, 6),
+};
+
+void rv1106_rst_init(struct device_node *np, void __iomem *reg_base)
+{
+	rockchip_register_softrst_lut(np,
+				      rv1106_register_offset,
+				      ARRAY_SIZE(rv1106_register_offset),
+				      reg_base + SOFTRST_CON(0),
+				      ROCKCHIP_SOFTRST_HIWORD_MASK);
+}
-- 
2.47.3

[PATCH 03/25] ARM: dts: rockchip: Add reset bindings to RV1106

[Vladislav Leonov]

Include the RV1106 CRU reset-ID header so device tree nodes can
reference reset lines by name, matching the reset controller support
added in the previous commit.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 70d3da6bd03e..fa5d0d7f4dcb 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/rockchip,rv1106-cru.h>
+#include <dt-bindings/reset/rockchip,rv1106-cru.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-- 
2.47.3

[PATCH 04/25] dt-bindings: net: rockchip-dwmac: add RV1106 compatible

[Vladislav Leonov]

Add compatible string for RV1106 gmac, and constrain it to
be compatible with Synopsys dwmac 4.20a.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 Documentation/devicetree/bindings/net/rockchip-dwmac.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
index 80c252845349..65eee45f7d7e 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
@@ -29,6 +29,7 @@ select:
           - rockchip,rk3568-gmac
           - rockchip,rk3576-gmac
           - rockchip,rk3588-gmac
+          - rockchip,rv1106-gmac
           - rockchip,rv1108-gmac
           - rockchip,rv1126-gmac
   required:
@@ -56,6 +57,7 @@ properties:
               - rockchip,rk3568-gmac
               - rockchip,rk3576-gmac
               - rockchip,rk3588-gmac
+              - rockchip,rv1106-gmac
               - rockchip,rv1126-gmac
           - const: snps,dwmac-4.20a
 
-- 
2.47.3

[PATCH 05/25] net: ethernet: stmicro: stmmac: dwmac-rk: Add RV1106 support

[Vladislav Leonov]

Rockchip RV1106 GMAC 10/100 ethernet controller.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 .../net/ethernet/stmicro/stmmac/dwmac-rk.c    | 55 +++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 8d7042e68926..a1bf545467cc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1034,6 +1034,60 @@ static const struct rk_gmac_ops rk3588_ops = {
 	},
 };
 
+#define RV1106_VOGRF_GMAC_CLK_CON		0X60004
+
+#define RV1106_VOGRF_MACPHY_RMII_MODE		GRF_BIT(0)
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV2		GRF_BIT(2)
+#define RV1106_VOGRF_GMAC_CLK_RMII_DIV20	GRF_CLR_BIT(2)
+
+#define RV1106_VOGRF_MACPHY_CON0		0X60028
+
+static void rv1106_set_to_rmii(struct rk_priv_data *bsp_priv)
+{
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON,
+		     RV1106_VOGRF_MACPHY_RMII_MODE |
+		     RV1106_VOGRF_GMAC_CLK_RMII_DIV2);
+}
+
+static int rv1106_set_speed(struct rk_priv_data *bsp_priv,
+			    phy_interface_t interface, int speed)
+{
+	unsigned int val;
+
+	if (interface != PHY_INTERFACE_MODE_RMII)
+		return 0;
+
+	if (speed == SPEED_10)
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV20;
+	else if (speed == SPEED_100)
+		val = RV1106_VOGRF_GMAC_CLK_RMII_DIV2;
+	else
+		return -EINVAL;
+
+	regmap_write(bsp_priv->grf, RV1106_VOGRF_GMAC_CLK_CON, val);
+
+	return 0;
+}
+
+static void rv1106_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
+{
+	rk_gmac_integrated_fephy_powerup(bsp_priv, RV1106_VOGRF_MACPHY_CON0);
+}
+
+static void rv1106_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
+{
+	rk_gmac_integrated_fephy_powerdown(bsp_priv, RV1106_VOGRF_MACPHY_CON0);
+}
+
+static const struct rk_gmac_ops rv1106_ops = {
+	.set_to_rmii = rv1106_set_to_rmii,
+	.set_speed = rv1106_set_speed,
+	.integrated_phy_powerup = rv1106_integrated_phy_powerup,
+	.integrated_phy_powerdown = rv1106_integrated_phy_powerdown,
+
+	.supports_rmii = true,
+};
+
 #define RV1108_GRF_GMAC_CON0		0X0900
 
 /* RV1108_GRF_GMAC_CON0 */
@@ -1628,6 +1682,7 @@ static const struct of_device_id rk_gmac_dwmac_match[] = {
 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
 	{ .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
 	{ .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
+	{ .compatible = "rockchip,rv1106-gmac", .data = &rv1106_ops },
 	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
 	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
 	{ }
-- 
2.47.3

[PATCH 06/25] ARM: dts: rockchip: Add Ethernet GMAC node for RV1106

[Vladislav Leonov]

Rockchip RV1106 has GMAC 10/100 ethernet controller.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 62 ++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index fa5d0d7f4dcb..71dd3dcc386c 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -19,6 +19,7 @@ / {
 	interrupt-parent = <&gic>;
 
 	aliases {
+		ethernet0 = &gmac;
 		gpio0 = &gpio0;
 		gpio1 = &gpio1;
 		gpio2 = &gpio2;
@@ -282,6 +283,67 @@ system_sram: sram@ff6c0000 {
 			ranges = <0 0xff6c0000 0x40000>;
 		};
 
+		gmac: ethernet@ffa80000 {
+			compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
+			reg = <0xffa80000 0x10000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_wake_irq";
+			rockchip,grf = <&grf>;
+			clocks = <&cru CLK_GMAC0_TX_50M_O>, <&cru CLK_GMAC0_REF_50M>,
+				<&cru ACLK_MAC>, <&cru PCLK_MAC>;
+			clock-names = "stmmaceth", "clk_mac_ref",
+					"aclk_mac", "pclk_mac";
+			resets = <&cru SRST_A_MAC>;
+			reset-names = "stmmaceth";
+
+			snps,mixed-burst;
+			snps,tso;
+
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,mtl-rx-config = <&mtl_rx_setup>;
+			snps,mtl-tx-config = <&mtl_tx_setup>;
+
+			phy-mode = "rmii";
+			clock_in_out = "input";
+			phy-handle = <&rmii_phy>;
+
+			status = "disabled";
+
+			mdio: mdio {
+				compatible = "snps,dwmac-mdio";
+				#address-cells = <0x1>;
+				#size-cells = <0x0>;
+				rmii_phy: ethernet-phy@2 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <2>;
+					clocks = <&cru CLK_MACPHY>;
+					resets = <&cru SRST_MACPHY>;
+					phy-is-integrated;
+				};
+			};
+
+			stmmac_axi_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <4>;
+				snps,rd_osr_lmt = <8>;
+				snps,blen = <0 0 0 0 16 8 4>;
+			};
+
+			mtl_rx_setup: rx-queues-config {
+				snps,rx-queues-to-use = <1>;
+				queue0 {
+					status = "okay";
+				};
+			};
+
+			mtl_tx_setup: tx-queues-config {
+				snps,tx-queues-to-use = <1>;
+				queue0 {
+					status = "okay";
+				};
+			};
+		};
+
 		emmc: mmc@ffa90000 {
 			compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
 			reg = <0xffa90000 0x4000>;
-- 
2.47.3

[PATCH 07/25] dt-bindings: phy: rockchip,inno-usb2phy: Add RV1106 compatible

[Vladislav Leonov]

The RV1106 has a single USB2 PHY with only an OTG port. Its OTG port
also exposes a "disconnect" interrupt in addition to the existing
otg-bvalid/otg-id/linestate, needed for reliable HS device unplug
detection, so allow up to 4 interrupts for that variant.

Add the "rockchip,rv1106-usb2phy" compatible and require
"rockchip,usbgrf" for it, matching the other Rockchip PHYs that need
GRF access.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 .../devicetree/bindings/phy/rockchip,inno-usb2phy.yaml   | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
index f50fc69fbbe4..4bc418376b18 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
@@ -25,6 +25,7 @@ properties:
       - rockchip,rk3568-usb2phy
       - rockchip,rk3576-usb2phy
       - rockchip,rk3588-usb2phy
+      - rockchip,rv1106-usb2phy
       - rockchip,rv1108-usb2phy
 
   reg:
@@ -121,7 +122,7 @@ properties:
 
       interrupts:
         minItems: 1
-        maxItems: 3
+        maxItems: 4
 
       interrupt-names:
         oneOf:
@@ -131,6 +132,11 @@ properties:
               - const: otg-bvalid
               - const: otg-id
               - const: linestate
+          - items:
+              - const: otg-bvalid
+              - const: otg-id
+              - const: linestate
+              - const: disconnect
 
       phy-supply:
         description:
@@ -160,6 +166,7 @@ allOf:
             enum:
               - rockchip,rk3528-usb2phy
               - rockchip,rk3568-usb2phy
+              - rockchip,rv1106-usb2phy
               - rockchip,rv1108-usb2phy
     then:
       required:
-- 
2.47.3

[PATCH 08/25] phy: rockchip: inno-usb2: Add support for RV1106

[Vladislav Leonov]

The RV1106 has a single USB2 PHY with only an OTG port, so add its
phy_cfgs entry with the OTG port's control/status/detect bit offsets
and charger-detection register layout.

Also add rv1106_usb2phy_tuning() to apply the vendor HS PHY tuning:
enable pre-emphasis in all line states, raise the Tx pre-emphasis
strength and eye height, increase the 45ohm HS ODT drive strength,
lower the Rx squelch trigger point, bypass squelch detector
calibration, disable the differential receiver to save power, and
switch the HS disconnect detector to single-ended mode (needed for
reliable unplug detection).

The register offsets and values are ported from the Rockchip vendor
BSP kernel; one difference is that the BSP driver additionally lowered
the Tx pre-emphasis strength on newer chip revisions via
rockchip_get_cpu_version(), which has no mainline equivalent, so only
the new revision's tuning value is kept here.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 7d8a533f24ae..ee24382a732a 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -1617,6 +1617,38 @@ static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
 	return ret;
 }
 
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+	int ret;
+
+	/* Always enable pre-emphasis in SOF & EOP & chirp & non-chirp state */
+	ret = regmap_update_bits(rphy->phy_base, 0x30, GENMASK(2, 0), 0x07);
+
+	/* Set Tx HS pre_emphasize strength to 3'b001 */
+	ret |= regmap_update_bits(rphy->phy_base, 0x40, GENMASK(5, 3), 0x01 << 3);
+
+	/* Set RX Squelch trigger point configure to 4'b0000 (112.5 mV) */
+	ret |= regmap_update_bits(rphy->phy_base, 0x64, GENMASK(6, 3), 0x00 << 3);
+
+	/* Turn off differential receiver by default to save power */
+	ret |= regmap_update_bits(rphy->phy_base, 0x100, BIT(6), 0);
+
+	/* Set 45ohm HS ODT value to 5'b10111 to increase driver strength */
+	ret |= regmap_update_bits(rphy->phy_base, 0x11c, GENMASK(4, 0), 0x17);
+
+	/* Set Tx HS eye height tuning to 3'b011 (462 mV) */
+	ret |= regmap_update_bits(rphy->phy_base, 0x124, GENMASK(4, 2), 0x03 << 2);
+
+	/* Bypass Squelch detector calibration */
+	ret |= regmap_update_bits(rphy->phy_base, 0x1a4, GENMASK(7, 4), 0x01 << 4);
+	ret |= regmap_update_bits(rphy->phy_base, 0x1b4, GENMASK(7, 4), 0x01 << 4);
+
+	/* Set HS disconnect detect mode to single ended detect mode */
+	ret |= regmap_update_bits(rphy->phy_base, 0x70, BIT(2), BIT(2));
+
+	return ret;
+}
+
 static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
 	{
 		.reg = 0x17c,
@@ -2324,6 +2356,49 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
 	{ /* sentinel */ }
 };
 
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
+	{
+		.reg = 0xff3e0000,
+		.num_ports	= 1,
+		.phy_tuning	= rv1106_usb2phy_tuning,
+		.clkout_ctl	= { 0x0058, 4, 4, 1, 0 },
+		.port_cfgs	= {
+			[USB2PHY_PORT_OTG] = {
+				.phy_sus	= { 0x0050, 8, 0, 0, 0x1d1 },
+				.bvalid_det_en	= { 0x0100, 2, 2, 0, 1 },
+				.bvalid_det_st	= { 0x0104, 2, 2, 0, 1 },
+				.bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
+				.idfall_det_en	= { 0x0100, 5, 5, 0, 1 },
+				.idfall_det_st	= { 0x0104, 5, 5, 0, 1 },
+				.idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
+				.idrise_det_en	= { 0x0100, 4, 4, 0, 1 },
+				.idrise_det_st	= { 0x0104, 4, 4, 0, 1 },
+				.idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
+				.ls_det_en	= { 0x0100, 0, 0, 0, 1 },
+				.ls_det_st	= { 0x0104, 0, 0, 0, 1 },
+				.ls_det_clr	= { 0x0108, 0, 0, 0, 1 },
+				.utmi_avalid	= { 0x0060, 10, 10, 0, 1 },
+				.utmi_bvalid	= { 0x0060, 9, 9, 0, 1 },
+				.utmi_id	= { 0x0060, 6, 6, 0, 1 },
+				.utmi_ls	= { 0x0060, 5, 4, 0, 1 },
+			},
+		},
+		.chg_det = {
+			.opmode		= { 0x0050, 8, 0, 0, 0x1d7 },
+			.cp_det		= { 0x0060, 13, 13, 0, 1 },
+			.dcp_det	= { 0x0060, 12, 12, 0, 1 },
+			.dp_det		= { 0x0060, 14, 14, 0, 1 },
+			.idm_sink_en	= { 0x0058, 8, 8, 0, 1 },
+			.idp_sink_en	= { 0x0058, 7, 7, 0, 1 },
+			.idp_src_en	= { 0x0058, 9, 9, 0, 1 },
+			.rdm_pdwn_en	= { 0x0058, 10, 10, 0, 1 },
+			.vdm_src_en	= { 0x0058, 12, 12, 0, 1 },
+			.vdp_src_en	= { 0x0058, 11, 11, 0, 1 },
+		},
+	},
+	{ /* sentinel */ }
+};
+
 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
 	{
 		.reg = 0x100,
@@ -2380,6 +2455,7 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
 	{ .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
 	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
+	{ .compatible = "rockchip,rv1106-usb2phy", .data = &rv1106_phy_cfgs },
 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
 	{}
 };
-- 
2.47.3

[PATCH 09/25] dt-bindings: usb: rockchip,dwc3: add RV1106 SoC support

[Vladislav Leonov]

Document the DWC3 USB controller found on the Rockchip RV1106 SoC.

The RV1106 has a USB2-only (high-speed) OTG controller. Unlike the
other supported SoCs it has no dedicated suspend clock: it only needs
the 24 MHz reference clock, the AXI bus clock and the UTMI clock.

Since the top-level clock-names list enforces a fixed order with
"suspend_clk" as the second entry, relax the second and third entries
to enums so that the RV1106 clock set (ref_clk, bus_clk, utmi) can be
expressed, and add a per-SoC clause constraining RV1106 to exactly
these three clocks. The relaxation is required rather than cosmetic:
every other compatible's own clause already agrees with the shared
tuple position-by-position, but RV1106 genuinely reorders it (bus_clk
before utmi, no suspend_clk), and allOf branches are ANDed, so without
loosening the shared entries the two clauses would be unsatisfiable
together.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 .../bindings/usb/rockchip,dwc3.yaml           | 35 ++++++++++++++++---
 1 file changed, 30 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 0554dbc4b854..86e00f251bdb 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -31,6 +31,7 @@ select:
           - rockchip,rk3568-dwc3
           - rockchip,rk3576-dwc3
           - rockchip,rk3588-dwc3
+          - rockchip,rv1106-dwc3
   required:
     - compatible
 
@@ -44,6 +45,7 @@ properties:
           - rockchip,rk3568-dwc3
           - rockchip,rk3576-dwc3
           - rockchip,rk3588-dwc3
+          - rockchip,rv1106-dwc3
       - const: snps,dwc3
 
   reg:
@@ -58,10 +60,11 @@ properties:
       - description:
           Controller reference clock, must to be 24 MHz
       - description:
-          Controller suspend clock, must to be 24 MHz or 32 KHz
+          Controller suspend clock (must to be 24 MHz or 32 KHz) or
+          Master/Core clock
       - description:
           Master/Core clock, must to be >= 62.5 MHz for SS
-          operation and >= 30MHz for HS operation
+          operation and >= 30MHz for HS operation, or UTMI clock
       - description:
           Controller grf clock OR UTMI clock
       - description:
@@ -71,8 +74,12 @@ properties:
     minItems: 3
     items:
       - const: ref_clk
-      - const: suspend_clk
-      - const: bus_clk
+      - enum:
+          - suspend_clk
+          - bus_clk
+      - enum:
+          - bus_clk
+          - utmi
       - enum:
           - grf_clk
           - utmi
@@ -145,7 +152,10 @@ allOf:
         clocks:
           maxItems: 3
         clock-names:
-          maxItems: 3
+          items:
+            - const: ref_clk
+            - const: suspend_clk
+            - const: bus_clk
   - if:
       properties:
         compatible:
@@ -161,6 +171,21 @@ allOf:
             - const: bus_clk
             - const: utmi
             - const: pipe
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: rockchip,rv1106-dwc3
+    then:
+      properties:
+        clocks:
+          minItems: 3
+          maxItems: 3
+        clock-names:
+          items:
+            - const: ref_clk
+            - const: bus_clk
+            - const: utmi
 
 examples:
   - |
-- 
2.47.3

[PATCH 10/25] ARM: dts: rockchip: Add USB2 PHY and USB3-OTG (DWC3) nodes for RV1106

[Vladislav Leonov]

Add the u2phy node with its otg-port child, using the disconnect
interrupt in addition to otg-bvalid/otg-id/linestate.

Also add the usbdrd/usbdrd_dwc3 nodes for the DWC3 controller behind
the PHY, reusing the "rockchip,rk3399-dwc3" glue compatible and the
snps quirks already used by other Rockchip DWC3 platforms, since
RV1106 does not need a dedicated glue driver.

Both nodes default to status = "disabled" and are enabled per-board.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 48 ++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 71dd3dcc386c..43db3b1dd4b8 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -180,6 +180,30 @@ saradc: adc@ff3c0000 {
 			status = "disabled";
 		};
 
+		u2phy: usb2-phy@ff3e0000 {
+			compatible = "rockchip,rv1106-usb2phy";
+			reg = <0xff3e0000 0x8000>;
+			clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+			clock-names = "phyclk", "pclk";
+			resets = <&cru SRST_USBPHY_POR>, <&cru SRST_P_USBPHY>;
+			reset-names = "phy", "apb";
+			rockchip,usbgrf = <&grf>;
+			#clock-cells = <0>;
+			clock-output-names = "usb480m_phy";
+			status = "disabled";
+
+			u2phy_otg: otg-port {
+				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "otg-bvalid", "otg-id",
+						"linestate", "disconnect";
+				#phy-cells = <0>;
+				status = "disabled";
+			};
+		};
+
 		uart0: serial@ff4a0000 {
 			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
 			reg = <0xff4a0000 0x100>;
@@ -378,6 +402,30 @@ sfc: spi@ffac0000 {
 			#size-cells = <0>;
 			status = "disabled";
 		};
+
+		usbdrd_dwc3: usb@ffb00000 {
+			compatible = "rockchip,rv1106-dwc3", "snps,dwc3";
+			reg = <0xffb00000 0x100000>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru CLK_REF_USBOTG>, <&cru ACLK_USBOTG>,
+				<&cru CLK_UTMI_USBOTG>;
+			clock-names = "ref_clk", "bus_clk", "utmi";
+			resets = <&cru SRST_A_USBOTG>;
+			dr_mode = "otg";
+			maximum-speed = "high-speed";
+			phys = <&u2phy_otg>;
+			phy-names = "usb2-phy";
+			phy_type = "utmi_wide";
+			snps,dis_enblslpm_quirk;
+			snps,dis-u2-freeclk-exists-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis-del-phy-power-chg-quirk;
+			snps,dis-tx-ipgap-linecheck-quirk;
+			snps,usb2-gadget-lpm-disable;
+			snps,usb2-lpm-disable;
+			snps,parkmode-disable-hs-quirk;
+			status = "disabled";
+		};
 	};
 };
 
-- 
2.47.3

[PATCH 11/25] dt-bindings: i2c: rk3x: Add RV1106 compatible

[Vladislav Leonov]

The RV1106 I2C controller is compatible with the one found on RK3399,
so add the "rockchip,rv1106-i2c" compatible to the list of variants
that fall back to "rockchip,rk3399-i2c".

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
index 91805fe8f393..725a58a35df7 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -43,6 +43,7 @@ properties:
               - rockchip,rk3568-i2c
               - rockchip,rk3576-i2c
               - rockchip,rk3588-i2c
+              - rockchip,rv1106-i2c
               - rockchip,rv1126-i2c
           - const: rockchip,rk3399-i2c
 
-- 
2.47.3

[PATCH 12/25] ARM: dts: rockchip: Add I2C nodes for RV1106

[Vladislav Leonov]

Rockchip RV1106 has five I2C controllers. Add the i2c0-i2c4 nodes
together with their aliases, using the m0 pinmux by default.

All nodes default to status = "disabled" and are enabled per-board.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 70 ++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 43db3b1dd4b8..43d992e3e2d6 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -25,6 +25,11 @@ aliases {
 		gpio2 = &gpio2;
 		gpio3 = &gpio3;
 		gpio4 = &gpio4;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
 	};
 
 	cpus {
@@ -155,6 +160,32 @@ gic: interrupt-controller@ff1f0000 {
 			#address-cells = <0>;
 		};
 
+		i2c0: i2c@ff310000 {
+			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+			reg = <0xff310000 0x1000>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+			clock-names = "i2c", "pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0m0_xfer>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@ff320000 {
+			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+			reg = <0xff320000 0x1000>;
+			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+			clock-names = "i2c", "pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c1m0_xfer>;
+			status = "disabled";
+		};
+
 		gpio0_ioc: syscon@ff388000 {
 			compatible = "rockchip,rv1106-gpio0-ioc", "syscon";
 			reg = <0xff388000 0x8000>;
@@ -204,6 +235,45 @@ u2phy_otg: otg-port {
 			};
 		};
 
+		i2c2: i2c@ff450000 {
+			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+			reg = <0xff450000 0x1000>;
+			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+			clock-names = "i2c", "pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c2m0_xfer>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@ff460000 {
+			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+			reg = <0xff460000 0x1000>;
+			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+			clock-names = "i2c", "pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c3m0_xfer>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@ff470000 {
+			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
+			reg = <0xff470000 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+			clock-names = "i2c", "pclk";
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c4m0_xfer>;
+			status = "disabled";
+		};
+
 		uart0: serial@ff4a0000 {
 			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
 			reg = <0xff4a0000 0x100>;
-- 
2.47.3

[PATCH 13/25] ARM: dts: rockchip: Add DMAC node for RV1106

[Vladislav Leonov]

Rockchip RV1106 has a single ARM PL330 DMA controller with 8 channels,
shared by the peripherals. Add the dmac node with its 8 event
interrupts plus the abort interrupt.

The controller needs arm,pl330-periph-burst to use burst transfers for
peripheral requests, as on the other Rockchip PL330 platforms.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 43d992e3e2d6..4abc333ab370 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -235,6 +235,24 @@ u2phy_otg: otg-port {
 			};
 		};
 
+		dmac: dma-controller@ff420000 {
+			compatible = "arm,pl330", "arm,primecell";
+			reg = <0xff420000 0x4000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			#dma-cells = <1>;
+			clocks = <&cru ACLK_DMAC>;
+			clock-names = "apb_pclk";
+			arm,pl330-periph-burst;
+		};
+
 		i2c2: i2c@ff450000 {
 			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
 			reg = <0xff450000 0x1000>;
-- 
2.47.3

[PATCH 14/25] ARM: dts: rockchip: Add DMA support to UART nodes

[Vladislav Leonov]

Add dmas/dma-names properties to uart0-uart5 so the dw-abp-uart
driver can use the RV1106 DMAC for TX/RX.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 4abc333ab370..58ac297e4d75 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -298,6 +298,8 @@ uart0: serial@ff4a0000 {
 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 7>, <&dmac 6>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
@@ -309,6 +311,8 @@ uart1: serial@ff4b0000 {
 			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 9>, <&dmac 8>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
@@ -320,6 +324,8 @@ uart2: serial@ff4c0000 {
 			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 11>, <&dmac 10>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
@@ -331,6 +337,8 @@ uart3: serial@ff4d0000 {
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 13>, <&dmac 12>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
@@ -342,6 +350,8 @@ uart4: serial@ff4e0000 {
 			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 15>, <&dmac 14>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
@@ -353,6 +363,8 @@ uart5: serial@ff4f0000 {
 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
+			dmas = <&dmac 17>, <&dmac 16>;
+			dma-names = "tx", "rx";
 			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 			clock-names = "baudclk", "apb_pclk";
 			status = "disabled";
-- 
2.47.3

[PATCH 15/25] dt-bindings: clock: rockchip: Add SCLK_IN_SPI1 for RV1106

[Vladislav Leonov]

Add the clock ID for SCLK_IN_SPI1. This gate exists per the RV1106 TRM
but is missing in the Rockchip BSP kernel. SCLK_IN_SPI0 already has
a binding, so add the SPI1 counterpart for consistency.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 include/dt-bindings/clock/rockchip,rv1106-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rockchip,rv1106-cru.h b/include/dt-bindings/clock/rockchip,rv1106-cru.h
index 80244988e139..ec6e7cd36f08 100644
--- a/include/dt-bindings/clock/rockchip,rv1106-cru.h
+++ b/include/dt-bindings/clock/rockchip,rv1106-cru.h
@@ -303,4 +303,6 @@
 #define PCLK_CPU_ROOT		286
 #define CLK_RTC32K_FRAC		287
 
+#define SCLK_IN_SPI1		288
+
 #endif
-- 
2.47.3

[PATCH 16/25] clk: rockchip: Add SCLK_IN_SPI1 gate for RV1106

[Vladislav Leonov]

Register the SCLK_IN_SPI1 clock gate (PERICLKGATE_CON3, bit 8),
mirroring the existing SCLK_IN_SPI0 gate. This clock is documented in
the RV1106 TRM but was missing in the Rockchip BSP kernel.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 drivers/clk/rockchip/clk-rv1106.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
index 1e3a110192bb..236159157c7e 100644
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -976,6 +976,8 @@ static struct rockchip_clk_branch rv1106_clk_branches[] __initdata = {
 			RV1106_VEPUCLKGATE_CON(0), 14, GFLAGS),
 	GATE(SCLK_IN_SPI0, "sclk_in_spi0", "sclk_in_spi0_io", 0,
 			RV1106_VEPUCLKGATE_CON(1), 4, GFLAGS),
+	GATE(SCLK_IN_SPI1, "sclk_in_spi1", "sclk_in_spi1_io", 0,
+			RV1106_PERICLKGATE_CON(3), 8, GFLAGS),
 
 	GATE(CLK_UTMI_USBOTG, "clk_utmi_usbotg", "clk_utmi_usbotg_io", 0,
 			RV1106_PERICLKGATE_CON(4), 9, GFLAGS),
-- 
2.47.3

[PATCH 17/25] dt-bindings: spi: rockchip: Add RV1106 compatible

[Vladislav Leonov]

The RV1106 SPI controller is compatible with the one found on RK3066,
so add the "rockchip,rv1106-spi" compatible to the list of variants
that fall back to "rockchip,rk3066-spi".

The RV1106 SPI controller also has an additional external slave clock
input (sclk_in), so extend clocks/clock-names with a third,
description/const entry for it.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 Documentation/devicetree/bindings/spi/spi-rockchip.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
index ce6762c92fda..159111d143f2 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.yaml
@@ -40,6 +40,7 @@ properties:
               - rockchip,rk3568-spi
               - rockchip,rk3576-spi
               - rockchip,rk3588-spi
+              - rockchip,rv1106-spi
               - rockchip,rv1126-spi
           - const: rockchip,rk3066-spi
 
@@ -50,14 +51,18 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 2
     items:
       - description: transfer-clock
       - description: peripheral clock
+      - description: slave clock
 
   clock-names:
+    minItems: 2
     items:
       - const: spiclk
       - const: apb_pclk
+      - const: sclk_in
 
   dmas:
     items:
-- 
2.47.3

[PATCH 18/25] spi: rockchip: Add support for RV1106

[Vladislav Leonov]

Add the "rockchip,rv1106-spi" compatible to the match table. No driver
changes are needed beyond that, since the controller behaves like the
other Rockchip variants already handled by the driver.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 drivers/spi/spi-rockchip.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 231fbcf0e7aa..447e6ff47c53 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -1021,6 +1021,7 @@ static const struct of_device_id rockchip_spi_dt_match[] = {
 	{ .compatible = "rockchip,rk3328-spi", },
 	{ .compatible = "rockchip,rk3368-spi", },
 	{ .compatible = "rockchip,rk3399-spi", },
+	{ .compatible = "rockchip,rv1106-spi", },
 	{ .compatible = "rockchip,rv1108-spi", },
 	{ .compatible = "rockchip,rv1126-spi", },
 	{ },
-- 
2.47.3

[PATCH 19/25] ARM: dts: rockchip: Add SPI nodes for RV1106

[Vladislav Leonov]

Rockchip RV1106 has two SPI controllers. Add the spi0 and spi1 nodes
together with their aliases, using the m0 pinmux and the DMA channels
of the single DMAC.

Compared to Rockchip BSP kernel add missing SCLK_IN_SPI1 to spi1 node.

Both nodes default to status = "disabled" and are enabled per-board.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 34 ++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 58ac297e4d75..ce2f169b1acd 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -30,6 +30,8 @@ aliases {
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		spi0 = &spi0;
+		spi1 = &spi1;
 	};
 
 	cpus {
@@ -370,6 +372,38 @@ uart5: serial@ff4f0000 {
 			status = "disabled";
 		};
 
+		spi0: spi@ff500000 {
+			compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
+			reg = <0xff500000 0x1000>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>;
+			clock-names = "spiclk", "apb_pclk", "sclk_in";
+			dmas = <&dmac 1>, <&dmac 0>;
+			dma-names = "tx", "rx";
+			num-cs = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
+			status = "disabled";
+		};
+
+		spi1: spi@ff510000 {
+			compatible = "rockchip,rv1106-spi", "rockchip,rk3066-spi";
+			reg = <0xff510000 0x1000>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>;
+			clock-names = "spiclk", "apb_pclk", "sclk_in";
+			dmas = <&dmac 3>, <&dmac 2>;
+			dma-names = "tx", "rx";
+			num-cs = <2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
+			status = "disabled";
+		};
+
 		gpio1_ioc: syscon@ff538000 {
 			compatible = "rockchip,rv1106-gpio1-ioc", "syscon";
 			reg = <0xff538000 0x8000>;
-- 
2.47.3

[PATCH 20/25] dt-bindings: rng: rockchip: Add RV1106 compatible

[Vladislav Leonov]

Add rockchip,rv1106-rng as a variant of rockchip,rk3588-rng, following
the pattern used for fallback compatibles in the schema (an items list
with an enum and a matching const fallback), so RV1106 can reuse the
existing rk3588-rng driver bindings.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 .../devicetree/bindings/rng/rockchip,rk3588-rng.yaml  | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
index fcc5be80142d..60ceac2697c0 100644
--- a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
@@ -13,10 +13,13 @@ maintainers:
 
 properties:
   compatible:
-    enum:
-      - rockchip,rk3576-rng
-      - rockchip,rk3588-rng
-
+    oneOf:
+      - const: rockchip,rk3576-rng
+      - const: rockchip,rk3588-rng
+      - items:
+          - enum:
+              - rockchip,rv1106-rng
+          - const: rockchip,rk3588-rng
   reg:
     maxItems: 1
 
-- 
2.47.3

[PATCH 21/25] ARM: dts: rockchip: Add RNG node for RV1106

[Vladislav Leonov]

Add the true random number generator (TRNG) node for RV1106,
compatible with rockchip,rk3588-rng. The node is left disabled
by default and can be enabled in board dts files.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index ce2f169b1acd..5db640a6ba90 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -255,6 +255,15 @@ dmac: dma-controller@ff420000 {
 			arm,pl330-periph-burst;
 		};
 
+		rng: rng@ff448000 {
+			compatible = "rockchip,rv1106-rng", "rockchip,rk3588-rng";
+			reg = <0xff448000 0x200>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru HCLK_TRNG_NS>;
+			resets = <&cru SRST_H_TRNG_NS>;
+			status = "disabled";
+		};
+
 		i2c2: i2c@ff450000 {
 			compatible = "rockchip,rv1106-i2c", "rockchip,rk3399-i2c";
 			reg = <0xff450000 0x1000>;
-- 
2.47.3

[PATCH 22/25] ARM: dts: rockchip: Add SDMMC1 node for RV1106

[Vladislav Leonov]

Add the SDMMC1 controller node, compatible with rockchip,rk3288-dw-mshc,
matching the existing eMMC and SD card controller nodes on this SoC.
The node is left disabled by default and can be enabled in board dts files.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 5db640a6ba90..b31cdb1c19d4 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -450,6 +450,18 @@ system_sram: sram@ff6c0000 {
 			ranges = <0 0xff6c0000 0x40000>;
 		};
 
+		sdmmc1: mmc@ff9a0000 {
+			compatible = "rockchip,rv1106-dw-mshc", "rockchip,rk3288-dw-mshc";
+			reg = <0xff9a0000 0x4000>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
+				<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+			fifo-depth = <0x100>;
+			max-frequency = <200000000>;
+			status = "disabled";
+		};
+
 		gmac: ethernet@ffa80000 {
 			compatible = "rockchip,rv1106-gmac", "snps,dwmac-4.20a";
 			reg = <0xffa80000 0x10000>;
-- 
2.47.3

[PATCH 23/25] ARM: dts: rockchip: add arm,cpu-registers-not-fw-configured to RV1106 timer node

[Vladislav Leonov]

The firmware on RV1106 does not initialize CNTVOFF, so the virtual
counter may have a bogus offset relative to the physical one.

Add the arm,cpu-registers-not-fw-configured property to the arch timer
node so the kernel does not trust firmware-configured timer registers
and uses the physical timer instead of the virtual one.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index b31cdb1c19d4..12e87d25c72b 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -57,6 +57,7 @@ timer {
 		clock-frequency = <24000000>;
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+		arm,cpu-registers-not-fw-configured;
 	};
 
 	xin24m: oscillator {
-- 
2.47.3

[PATCH 24/25] dt-bindings: pwm: rockchip: Add RV1106 compatible

[Vladislav Leonov]

Add the compatible for the PWM of the RV1106 which is compatible
with RK3328 vatiant.

RV1106 PWM channels also wire up an interrupt line each, with the
channel that supports capture mode using a second one for that.
Add "interrupts" to the schema to describe this.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>
---

 Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
index c8cdfb723336..8fa75cabf025 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.yaml
@@ -34,12 +34,20 @@ properties:
               - rockchip,rk3562-pwm
               - rockchip,rk3568-pwm
               - rockchip,rk3588-pwm
+              - rockchip,rv1106-pwm
               - rockchip,rv1126-pwm
           - const: rockchip,rk3328-pwm
 
   reg:
     maxItems: 1
 
+  interrupts:
+    minItems: 1
+    maxItems: 2
+    description:
+      Some PWM channels (e.g. on rockchip,rv1106-pwm) additionally
+      support capture mode and use a second interrupt for that.
+
   clocks:
     minItems: 1
     maxItems: 2
-- 
2.47.3

[PATCH 25/25] ARM: dts: rockchip: Add PWM nodes for RV1106

[Vladislav Leonov]

Add the 12 PWM controller nodes (pwm0-pwm11) for RV1106, along with
their aliases.

Signed-off-by: Vladislav Leonov <vlad@zlab.su>

---

 arch/arm/boot/dts/rockchip/rv1106.dtsi | 159 +++++++++++++++++++++++++
 1 file changed, 159 insertions(+)

diff --git a/arch/arm/boot/dts/rockchip/rv1106.dtsi b/arch/arm/boot/dts/rockchip/rv1106.dtsi
index 12e87d25c72b..d7959158f8a0 100644
--- a/arch/arm/boot/dts/rockchip/rv1106.dtsi
+++ b/arch/arm/boot/dts/rockchip/rv1106.dtsi
@@ -30,6 +30,18 @@ aliases {
 		i2c2 = &i2c2;
 		i2c3 = &i2c3;
 		i2c4 = &i2c4;
+		pwm0 = &pwm0;
+		pwm1 = &pwm1;
+		pwm2 = &pwm2;
+		pwm3 = &pwm3;
+		pwm4 = &pwm4;
+		pwm5 = &pwm5;
+		pwm6 = &pwm6;
+		pwm7 = &pwm7;
+		pwm8 = &pwm8;
+		pwm9 = &pwm9;
+		pwm10 = &pwm10;
+		pwm11 = &pwm11;
 		spi0 = &spi0;
 		spi1 = &spi1;
 	};
@@ -189,6 +201,104 @@ i2c1: i2c@ff320000 {
 			status = "disabled";
 		};
 
+		pwm0: pwm@ff350000 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff350000 0x10>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm0m0_pins>;
+			clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm1: pwm@ff350010 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff350010 0x10>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm1m0_pins>;
+			clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm2: pwm@ff350020 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff350020 0x10>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm2m0_pins>;
+			clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm3: pwm@ff350030 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff350030 0x10>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm3m0_pins>;
+			clocks = <&cru CLK_PWM0_PERI>, <&cru PCLK_PWM0_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm4: pwm@ff360000 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff360000 0x10>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm4m0_pins>;
+			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm5: pwm@ff360010 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff360010 0x10>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm5m0_pins>;
+			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm6: pwm@ff360020 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff360020 0x10>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm6m0_pins>;
+			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm7: pwm@ff360030 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff360030 0x10>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm7m0_pins>;
+			clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
 		gpio0_ioc: syscon@ff388000 {
 			compatible = "rockchip,rv1106-gpio0-ioc", "syscon";
 			reg = <0xff388000 0x8000>;
@@ -304,6 +414,55 @@ i2c4: i2c@ff470000 {
 			status = "disabled";
 		};
 
+		pwm8: pwm@ff490000 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff490000 0x10>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm8m0_pins>;
+			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm9: pwm@ff490010 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff490010 0x10>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm9m0_pins>;
+			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm10: pwm@ff490020 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff490020 0x10>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm10m0_pins>;
+			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
+		pwm11: pwm@ff490030 {
+			compatible = "rockchip,rv1106-pwm", "rockchip,rk3328-pwm";
+			reg = <0xff490030 0x10>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			#pwm-cells = <3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pwm11m0_pins>;
+			clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+			clock-names = "pwm", "pclk";
+			status = "disabled";
+		};
+
 		uart0: serial@ff4a0000 {
 			compatible = "rockchip,rv1106-uart", "snps,dw-apb-uart";
 			reg = <0xff4a0000 0x100>;
-- 
2.47.3

Re: [PATCH 17/25] dt-bindings: spi: rockchip: Add RV1106 compatible

[Mark Brown]

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On Mon, Aug 10, 2026 at 03:11:08PM +0300, Vladislav Leonov wrote:
> The RV1106 SPI controller is compatible with the one found on RK3066,
> so add the "rockchip,rv1106-spi" compatible to the list of variants
> that fall back to "rockchip,rk3066-spi".

Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.

[-- Attachment #2: signature.asc --]
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Re: [PATCH 00/25] ARM: rockchip: Add peripheral support for RV1106

[Jakub Kicinski]

On Mon, 10 Aug 2026 15:10:51 +0300 Vladislav Leonov wrote:
> Basic support for the Rockchip RV1106/RV1103 SoCs currently under review.
> This series builds on top of that and enables the peripherals needed to
> bring up a board beyond a serial console:

Don't expect maintainers to dig out patches for their subsystems
from a big series. This is not how upstream development works.
Repost 4+5 as a separate series to networking..