[PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition

[PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition

[Christian Marangi]

This small series adds all the nodes of what is currently supported
upstream for this SoC.

Christian Marangi (9):
  arm64: dts: airoha: en7581: reorder nodes following incremental regs
  arm64: dts: airoha: en7581: add CPU OPP and scaling nodes
  arm64: dts: airoha: en7581: add Chip-SCU accessor node
  arm64: dts: airoha: en7581: add thermal sensor nodes
  arm64: dts: airoha: en7581: add watchdog node
  arm64: dts: airoha: en7581: add PWM node
  arm64: dts: airoha: en7581: add nodes for all supported uart and
    hsuart
  arm64: dts: airoha: en7581: add crypto node
  arm64: dts: airoha: en7581: add integrated switch node

 arch/arm64/boot/dts/airoha/en7581.dtsi | 673 ++++++++++++++++++++-----
 1 file changed, 553 insertions(+), 120 deletions(-)

-- 
2.55.0

[PATCH 1/9] arm64: dts: airoha: en7581: reorder nodes following incremental regs

[Christian Marangi]

Reorder nods position following incremental register. This is to tidy
things up and no additional code is added.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 246 ++++++++++++-------------
 1 file changed, 123 insertions(+), 123 deletions(-)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index ff6908a76e8e..83b30a340950 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -173,18 +173,6 @@ spi_nand: nand@0 {
 			};
 		};
 
-		scuclk: clock-controller@1fb00000 {
-			compatible = "airoha,en7581-scu";
-			reg = <0x0 0x1fb00000 0x0 0x970>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
-		};
-
-		pbus_csr: syscon@1fbe3400 {
-			compatible = "airoha,en7581-pbus-csr", "syscon";
-			reg = <0x0 0x1fbe3400 0x0 0xff>;
-		};
-
 		pciephy: phy@1fa5a000 {
 			compatible = "airoha,en7581-pcie-phy";
 			reg = <0x0 0x1fa5a000 0x0 0xfff>,
@@ -199,6 +187,129 @@ pciephy: phy@1fa5a000 {
 			#phy-cells = <0>;
 		};
 
+		rng@1faa1000 {
+			compatible = "airoha,en7581-trng";
+			reg = <0x0 0x1faa1000 0x0 0xc04>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		scuclk: clock-controller@1fb00000 {
+			compatible = "airoha,en7581-scu";
+			reg = <0x0 0x1fb00000 0x0 0x970>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		eth: ethernet@1fb50000 {
+			compatible = "airoha,en7581-eth";
+			reg = <0 0x1fb50000 0 0x2600>,
+			      <0 0x1fb54000 0 0x2000>,
+			      <0 0x1fb56000 0 0x2000>;
+			reg-names = "fe", "qdma0", "qdma1";
+
+			resets = <&scuclk EN7581_FE_RST>,
+				 <&scuclk EN7581_FE_PDMA_RST>,
+				 <&scuclk EN7581_FE_QDMA_RST>,
+				 <&scuclk EN7581_XSI_MAC_RST>,
+				 <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
+				 <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
+				 <&scuclk EN7581_HSI_MAC_RST>,
+				 <&scuclk EN7581_XFP_MAC_RST>;
+			reset-names = "fe", "pdma", "qdma",
+				      "xsi-mac", "hsi0-mac", "hsi1-mac",
+				      "hsi-mac", "xfp-mac";
+
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gdm1: ethernet@1 {
+				compatible = "airoha,eth-mac";
+				reg = <1>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <10000>;
+					full-duplex;
+					pause;
+				};
+			};
+		};
+
+		pbus_csr: syscon@1fbe3400 {
+			compatible = "airoha,en7581-pbus-csr", "syscon";
+			reg = <0x0 0x1fbe3400 0x0 0xff>;
+		};
+
+		uart1: serial@1fbf0000 {
+			compatible = "ns16550";
+			reg = <0x0 0x1fbf0000 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <1843200>;
+		};
+
+		system-controller@1fbf0200 {
+			compatible = "airoha,en7581-gpio-sysctl", "syscon",
+				     "simple-mfd";
+			reg = <0x0 0x1fbf0200 0x0 0xc0>;
+
+			en7581_pinctrl: pinctrl {
+				compatible = "airoha,en7581-pinctrl";
+
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+		};
+
+		i2c0: i2c@1fbf8000 {
+			compatible = "mediatek,mt7621-i2c";
+			reg = <0x0 0x1fbf8000 0x0 0x100>;
+
+			resets = <&scuclk EN7581_I2C2_RST>;
+
+			clocks = <&clk20m>;
+			clock-frequency = <100000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c@1fbf8100 {
+			compatible = "mediatek,mt7621-i2c";
+			reg = <0x0 0x1fbf8100 0x0 0x100>;
+
+			resets = <&scuclk EN7581_I2C_MASTER_RST>;
+
+			clocks = <&clk20m>;
+			clock-frequency = <100000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
 		pcie0: pcie@1fc00000 {
 			compatible = "airoha,en7581-pcie";
 			device_type = "pci";
@@ -284,116 +395,5 @@ pcie_intc1: interrupt-controller {
 				#interrupt-cells = <1>;
 			};
 		};
-
-		uart1: serial@1fbf0000 {
-			compatible = "ns16550";
-			reg = <0x0 0x1fbf0000 0x0 0x30>;
-			reg-io-width = <4>;
-			reg-shift = <2>;
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-			clock-frequency = <1843200>;
-		};
-
-		rng@1faa1000 {
-			compatible = "airoha,en7581-trng";
-			reg = <0x0 0x1faa1000 0x0 0xc04>;
-			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-		};
-
-		system-controller@1fbf0200 {
-			compatible = "airoha,en7581-gpio-sysctl", "syscon",
-				     "simple-mfd";
-			reg = <0x0 0x1fbf0200 0x0 0xc0>;
-
-			en7581_pinctrl: pinctrl {
-				compatible = "airoha,en7581-pinctrl";
-
-				interrupt-parent = <&gic>;
-				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-
-				gpio-controller;
-				#gpio-cells = <2>;
-
-				interrupt-controller;
-				#interrupt-cells = <2>;
-			};
-		};
-
-		i2c0: i2c@1fbf8000 {
-			compatible = "mediatek,mt7621-i2c";
-			reg = <0x0 0x1fbf8000 0x0 0x100>;
-
-			resets = <&scuclk EN7581_I2C2_RST>;
-
-			clocks = <&clk20m>;
-			clock-frequency = <100000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			status = "disabled";
-		};
-
-		i2c1: i2c@1fbf8100 {
-			compatible = "mediatek,mt7621-i2c";
-			reg = <0x0 0x1fbf8100 0x0 0x100>;
-
-			resets = <&scuclk EN7581_I2C_MASTER_RST>;
-
-			clocks = <&clk20m>;
-			clock-frequency = <100000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			status = "disabled";
-		};
-
-		eth: ethernet@1fb50000 {
-			compatible = "airoha,en7581-eth";
-			reg = <0 0x1fb50000 0 0x2600>,
-			      <0 0x1fb54000 0 0x2000>,
-			      <0 0x1fb56000 0 0x2000>;
-			reg-names = "fe", "qdma0", "qdma1";
-
-			resets = <&scuclk EN7581_FE_RST>,
-				 <&scuclk EN7581_FE_PDMA_RST>,
-				 <&scuclk EN7581_FE_QDMA_RST>,
-				 <&scuclk EN7581_XSI_MAC_RST>,
-				 <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
-				 <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
-				 <&scuclk EN7581_HSI_MAC_RST>,
-				 <&scuclk EN7581_XFP_MAC_RST>;
-			reset-names = "fe", "pdma", "qdma",
-				      "xsi-mac", "hsi0-mac", "hsi1-mac",
-				      "hsi-mac", "xfp-mac";
-
-			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-
-			status = "disabled";
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			gdm1: ethernet@1 {
-				compatible = "airoha,eth-mac";
-				reg = <1>;
-				phy-mode = "internal";
-				status = "disabled";
-
-				fixed-link {
-					speed = <10000>;
-					full-duplex;
-					pause;
-				};
-			};
-		};
 	};
 };
-- 
2.55.0

[PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes

[Christian Marangi]

Add required CPU OPP and PD nodes to support CPU frequency scaling.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 177 ++++++++++++++++++++++++-
 1 file changed, 173 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 83b30a340950..c5a335086741 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -74,8 +74,12 @@ cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x0>;
+			operating-points-v2 = <&cpu_opp_table>;
 			enable-method = "psci";
-			clock-frequency = <80000000>;
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
 			next-level-cache = <&l2>;
 		};
 
@@ -83,8 +87,12 @@ cpu1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x1>;
+			operating-points-v2 = <&cpu_opp_table>;
 			enable-method = "psci";
-			clock-frequency = <80000000>;
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
 			next-level-cache = <&l2>;
 		};
 
@@ -92,8 +100,12 @@ cpu2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x2>;
+			operating-points-v2 = <&cpu_opp_table>;
 			enable-method = "psci";
-			clock-frequency = <80000000>;
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
 			next-level-cache = <&l2>;
 		};
 
@@ -101,8 +113,12 @@ cpu3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0x3>;
+			operating-points-v2 = <&cpu_opp_table>;
 			enable-method = "psci";
-			clock-frequency = <80000000>;
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
 			next-level-cache = <&l2>;
 		};
 
@@ -115,6 +131,159 @@ l2: l2-cache {
 		};
 	};
 
+	cpufreq: cpufreq {
+		compatible = "airoha,en7581-cpufreq";
+
+		operating-points-v2 = <&cpu_smcc_opp_table>;
+
+		#power-domain-cells = <0>;
+		#clock-cells = <0>;
+	};
+
+	cpu_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			required-opps = <&smcc_opp0>;
+		};
+
+		opp-550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			required-opps = <&smcc_opp1>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			required-opps = <&smcc_opp2>;
+		};
+
+		opp-650000000 {
+			opp-hz = /bits/ 64 <650000000>;
+			required-opps = <&smcc_opp3>;
+		};
+
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			required-opps = <&smcc_opp4>;
+		};
+
+		opp-750000000 {
+			opp-hz = /bits/ 64 <750000000>;
+			required-opps = <&smcc_opp5>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			required-opps = <&smcc_opp6>;
+		};
+
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			required-opps = <&smcc_opp7>;
+		};
+
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			required-opps = <&smcc_opp8>;
+		};
+
+		opp-950000000 {
+			opp-hz = /bits/ 64 <950000000>;
+			required-opps = <&smcc_opp9>;
+		};
+
+		opp-1000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			required-opps = <&smcc_opp10>;
+		};
+
+		opp-1050000000 {
+			opp-hz = /bits/ 64 <1050000000>;
+			required-opps = <&smcc_opp11>;
+		};
+
+		opp-1100000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			required-opps = <&smcc_opp12>;
+		};
+
+		opp-1150000000 {
+			opp-hz = /bits/ 64 <1150000000>;
+			required-opps = <&smcc_opp13>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			required-opps = <&smcc_opp14>;
+		};
+	};
+
+	cpu_smcc_opp_table: opp-table-smcc {
+		compatible = "operating-points-v2";
+
+		smcc_opp0: opp-0 {
+			opp-level = <0>;
+		};
+
+		smcc_opp1: opp-1 {
+			opp-level = <1>;
+		};
+
+		smcc_opp2: opp-2 {
+			opp-level = <2>;
+		};
+
+		smcc_opp3: opp-3 {
+			opp-level = <3>;
+		};
+
+		smcc_opp4: opp-4 {
+			opp-level = <4>;
+		};
+
+		smcc_opp5: opp-5 {
+			opp-level = <5>;
+		};
+
+		smcc_opp6: opp-6 {
+			opp-level = <6>;
+		};
+
+		smcc_opp7: opp-7 {
+			opp-level = <7>;
+		};
+
+		smcc_opp8: opp-8 {
+			opp-level = <8>;
+		};
+
+		smcc_opp9: opp-9 {
+			opp-level = <9>;
+		};
+
+		smcc_opp10: opp-10 {
+			opp-level = <10>;
+		};
+
+		smcc_opp11: opp-11 {
+			opp-level = <11>;
+		};
+
+		smcc_opp12: opp-12 {
+			opp-level = <12>;
+		};
+
+		smcc_opp13: opp-13 {
+			opp-level = <13>;
+		};
+
+		smcc_opp14: opp-14 {
+			opp-level = <14>;
+		};
+	};
+
 	timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-- 
2.55.0

[PATCH 3/9] arm64: dts: airoha: en7581: add Chip-SCU accessor node

[Christian Marangi]

Add Chip-SCU accessor node as a companion of the SCU node to permit
additional configuration for clock, MUX and thermal related registers.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index c5a335086741..fbc5ee47523c 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -342,6 +342,11 @@ spi_nand: nand@0 {
 			};
 		};
 
+		chip_scu: syscon@1fa20000 {
+			compatible = "airoha,en7581-chip-scu", "syscon";
+			reg = <0x0 0x1fa20000 0x0 0x388>;
+		};
+
 		pciephy: phy@1fa5a000 {
 			compatible = "airoha,en7581-pcie-phy";
 			reg = <0x0 0x1fa5a000 0x0 0xfff>,
-- 
2.55.0

[PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes

[Christian Marangi]

Add thermal sensor nodes and attach them to the CPU node to control passive
throttle and define critical temperature of the SoC.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 47 ++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index fbc5ee47523c..58bd8b318910 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/en7523-clk.h>
 #include <dt-bindings/reset/airoha,en7581-reset.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -81,6 +82,7 @@ cpu0: cpu@0 {
 			power-domains = <&cpufreq>;
 			power-domain-names = "perf";
 			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {
@@ -94,6 +96,7 @@ cpu1: cpu@1 {
 			power-domains = <&cpufreq>;
 			power-domain-names = "perf";
 			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {
@@ -107,6 +110,7 @@ cpu2: cpu@2 {
 			power-domains = <&cpufreq>;
 			power-domain-names = "perf";
 			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {
@@ -120,6 +124,7 @@ cpu3: cpu@3 {
 			power-domains = <&cpufreq>;
 			power-domain-names = "perf";
 			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
 		};
 
 		l2: l2-cache {
@@ -293,6 +298,39 @@ timer {
 			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	thermal-zones {
+		cpu_thermal: cpu-thermal {
+			polling-delay-passive = <0>;
+			polling-delay = <0>;
+
+			thermal-sensors = <&thermal 0>;
+
+			trips {
+				cpu_hot: cpu-hot {
+					temperature = <95000>;
+					hysteresis = <1000>;
+					type = "hot";
+				};
+
+				cpu-critical {
+					temperature = <120000>;
+					hysteresis = <1000>;
+					type = "critical";
+				};
+			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu_hot>;
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
 	clk20m: clock-20000000 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -319,6 +357,15 @@ gic: interrupt-controller@9000000 {
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 
+		thermal: thermal-sensor@1efbd000 {
+			compatible = "airoha,en7581-thermal";
+			reg = <0x0 0x1efbd000 0x0 0xd5c>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			airoha,chip-scu = <&chip_scu>;
+
+			#thermal-sensor-cells = <0>;
+		};
+
 		spi@1fa10000 {
 			compatible = "airoha,en7581-snand";
 			reg = <0x0 0x1fa10000 0x0 0x140>,
-- 
2.55.0

[PATCH 5/9] arm64: dts: airoha: en7581: add watchdog node

[Christian Marangi]

Add watchdog node to catch stall and correctly reboot the system.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 58bd8b318910..3a4a4fb0eba9 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -484,6 +484,14 @@ uart1: serial@1fbf0000 {
 			clock-frequency = <1843200>;
 		};
 
+		watchdog@1fbf0100 {
+			compatible = "airoha,en7581-wdt";
+			reg = <0x0 0x1fbf0100 0x0 0x38>;
+
+			clocks = <&scuclk EN7523_CLK_BUS>;
+			clock-names = "bus";
+		};
+
 		system-controller@1fbf0200 {
 			compatible = "airoha,en7581-gpio-sysctl", "syscon",
 				     "simple-mfd";
-- 
2.55.0

[PATCH 6/9] arm64: dts: airoha: en7581: add PWM node

[Christian Marangi]

Add PWM node to control all status leds generally attached to Vendor
boards.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 3a4a4fb0eba9..760f0c3e6090 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -509,6 +509,12 @@ en7581_pinctrl: pinctrl {
 				interrupt-controller;
 				#interrupt-cells = <2>;
 			};
+
+			en7581_pwm: pwm {
+				compatible = "airoha,en7581-pwm";
+
+				#pwm-cells = <3>;
+			};
 		};
 
 		i2c0: i2c@1fbf8000 {
-- 
2.55.0

[PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart

[Christian Marangi]

Add all the nodes to support the existing uart and hsuart present on the
SoC. Also update the compatible for the already defined uart to use the
more specific UART configuration.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 46 +++++++++++++++++++++++++-
 1 file changed, 45 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 760f0c3e6090..ee1633f01068 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -470,13 +470,24 @@ fixed-link {
 			};
 		};
 
+		serial@1fbe1000 {
+			compatible = "airoha,an7581-hsuart";
+			reg = <0x0 0x1fbe1000 0x0 0x40>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <7372800>;
+
+			status = "disabled";
+		};
+
 		pbus_csr: syscon@1fbe3400 {
 			compatible = "airoha,en7581-pbus-csr", "syscon";
 			reg = <0x0 0x1fbe3400 0x0 0xff>;
 		};
 
 		uart1: serial@1fbf0000 {
-			compatible = "ns16550";
+			compatible = "airoha,en7523-uart";
 			reg = <0x0 0x1fbf0000 0x0 0x30>;
 			reg-io-width = <4>;
 			reg-shift = <2>;
@@ -517,6 +528,39 @@ en7581_pwm: pwm {
 			};
 		};
 
+		serial@1fbf0300 {
+			compatible = "airoha,en7523-uart";
+			reg = <0x0 0x1fbf0300 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <7372800>;
+
+			status = "disabled";
+		};
+
+		serial@1fbf0600 {
+			compatible = "airoha,en7523-uart";
+			reg = <0x0 0x1fbf0600 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <7372800>;
+
+			status = "disabled";
+		};
+
+		serial@1fbf0700 {
+			compatible = "airoha,en7523-uart";
+			reg = <0x0 0x1fbf0700 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <7372800>;
+
+			status = "disabled";
+		};
+
 		i2c0: i2c@1fbf8000 {
 			compatible = "mediatek,mt7621-i2c";
 			reg = <0x0 0x1fbf8000 0x0 0x100>;
-- 
2.55.0

[PATCH 8/9] arm64: dts: airoha: en7581: add crypto node

[Christian Marangi]

Add crypto node to support the integrated Inside Secure SafeXcel EIP93.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index ee1633f01068..f214fa3a3e2b 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -470,6 +470,13 @@ fixed-link {
 			};
 		};
 
+		crypto@1fb70000 {
+			compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
+			reg = <0x0 0x1fb70000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		serial@1fbe1000 {
 			compatible = "airoha,an7581-hsuart";
 			reg = <0x0 0x1fbe1000 0x0 0x40>;
-- 
2.55.0

[PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node

[Christian Marangi]

Add the integrated switch node complete of the internal PHY with the PHY
address and the supported leds attached.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
 arch/arm64/boot/dts/airoha/en7581.dtsi | 147 +++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index f214fa3a3e2b..83ae41271f96 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -4,6 +4,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/en7523-clk.h>
 #include <dt-bindings/reset/airoha,en7581-reset.h>
+#include <dt-bindings/leds/common.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -470,6 +471,152 @@ fixed-link {
 			};
 		};
 
+		switch: switch@1fb58000 {
+			compatible = "airoha,en7581-switch";
+			reg = <0 0x1fb58000 0 0x8000>;
+			resets = <&scuclk EN7581_GSW_RST>;
+
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gsw_port1: port@1 {
+					reg = <1>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy1>;
+				};
+
+				gsw_port2: port@2 {
+					reg = <2>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy2>;
+				};
+
+				gsw_port3: port@3 {
+					reg = <3>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy3>;
+				};
+
+				gsw_port4: port@4 {
+					reg = <4>;
+					phy-mode = "internal";
+					phy-handle = <&gsw_phy4>;
+				};
+
+				port@6 {
+					reg = <6>;
+					ethernet = <&gdm1>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <10000>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+
+			mdio: mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				gsw_phy1: ethernet-phy@9 {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <9>;
+					phy-mode = "internal";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy1_led0: led@0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy1_led1: led@1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy2: ethernet-phy@a {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <10>;
+					phy-mode = "internal";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy2_led0: led@0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy2_led1: led@1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy3: ethernet-phy@b {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <11>;
+					phy-mode = "internal";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy3_led0: led@0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy3_led1: led@1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+
+				gsw_phy4: ethernet-phy@c {
+					compatible = "ethernet-phy-ieee802.3-c22";
+					reg = <12>;
+					phy-mode = "internal";
+
+					leds {
+						#address-cells = <1>;
+						#size-cells = <0>;
+
+						gsw_phy4_led0: led@0 {
+							reg = <0>;
+							status = "disabled";
+						};
+
+						gsw_phy4_led1: led@1 {
+							reg = <1>;
+							status = "disabled";
+						};
+					};
+				};
+			};
+		};
+
 		crypto@1fb70000 {
 			compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
 			reg = <0x0 0x1fb70000 0x0 0x1000>;
-- 
2.55.0

Re: [PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] cpufreq: airoha: positive return from dev_pm_domain_attach_list() mishandled
- [Medium] arm64: dts: airoha: en7581: zero opp-level in smcc_opp0 conflicts with genpd
--

commit ade97d9a263f63e320dd00b49d71387b254adb06
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add CPU OPP and scaling nodes

This commit adds the cpufreq node, CPU OPP tables, and CPU clock and power
domain references to arch/arm64/boot/dts/airoha/en7581.dtsi to enable CPU
frequency scaling on Airoha EN7581.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index 83b30a340950f..c5a3350867410 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -74,8 +74,12 @@ cpu0: cpu@0 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a53";
>  			reg = <0x0>;
> +			operating-points-v2 = <&cpu_opp_table>;
>  			enable-method = "psci";
> -			clock-frequency = <80000000>;
> +			clocks = <&cpufreq>;
> +			clock-names = "cpu";
> +			power-domains = <&cpufreq>;
> +			power-domain-names = "perf";
>  			next-level-cache = <&l2>;
>  		};

[Severity: High]
Does adding the cpu clock and perf power domain to cpu0 cause
airoha_cpufreq_probe() to fail and leak priv->pd_list on boot?

Prior to this change, airoha_cpufreq_probe() in
drivers/cpufreq/airoha-cpufreq.c returned early at dev_pm_opp_set_config()
with -ENOENT because cpu0 did not have the clock and power domain properties.
With these properties now present, probe reaches dev_pm_domain_attach_list():

drivers/cpufreq/airoha-cpufreq.c:airoha_cpufreq_probe() {
	...
	/* Attach PM for OPP */
	ret = dev_pm_domain_attach_list(cpu_dev, &attach_data,
					&priv->pd_list);
	if (ret)
		goto clear_opp_config;
	...
}

In drivers/base/power/common.c, dev_pm_domain_attach_list() returns the
positive number of attached power domains on success:

drivers/base/power/common.c:dev_pm_domain_attach_list() {
	...
	pds->num_pds = num_pds;
	*list = pds;
	return num_pds;
}

When attaching the single perf domain succeeds, dev_pm_domain_attach_list()
returns 1. Because airoha_cpufreq_probe() checks if (ret) rather than
if (ret < 0), it treats the successful attach as an error, jumps to
clear_opp_config without calling dev_pm_domain_detach_list(priv->pd_list),
leaks priv->pd_list along with the virtual genpd device and device link, and
returns 1 from probe so cpufreq-dt is never registered.

[ ... ]

> @@ -115,6 +131,159 @@ l2: l2-cache {
>  		};
>  	};
>  
> +	cpufreq: cpufreq {
> +		compatible = "airoha,en7581-cpufreq";
> +
> +		operating-points-v2 = <&cpu_smcc_opp_table>;
> +
> +		#power-domain-cells = <0>;
> +		#clock-cells = <0>;
> +	};
> +
> +	cpu_opp_table: opp-table {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			required-opps = <&smcc_opp0>;
> +		};

[ ... ]

> +	cpu_smcc_opp_table: opp-table-smcc {
> +		compatible = "operating-points-v2";
> +
> +		smcc_opp0: opp-0 {
> +			opp-level = <0>;
> +		};

[Severity: Medium]
Can setting opp-level = <0> in smcc_opp0 cause the first transition to
500 MHz (opp-500000000) to be silently skipped by the generic PM domain core?

In drivers/pmdomain/core.c, performance state 0 represents the initial
unconstrained state, and both gpd_data->performance_state and
genpd->performance_state are zero-initialized when the domain is registered
and attached.

If the CPU boots at a frequency above 500 MHz and the first cpufreq
transition targets opp-500000000, the call chain
dev_pm_opp_set_rate() -> _set_opp() -> _set_required_opps() ->
_set_opp_level() -> dev_pm_domain_set_performance_state() invokes
genpd_set_performance_state() with state = 0:

drivers/pmdomain/core.c:genpd_set_performance_state() {
	...
	prev_state = gpd_data->performance_state;
	if (prev_state == state)
		return 0;
	...
}

Because prev_state is already 0 (and genpd->performance_state in
_genpd_set_performance_state() is also 0), genpd_set_performance_state()
returns 0 immediately without calling
airoha_cpu_pmdomain_set_performance_state() in
drivers/pmdomain/mediatek/airoha-cpu-pmdomain.c, leaving the hardware at the
boot frequency while cpufreq and OPP record 500 MHz as active.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=2

Re: [PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] arm64: dts: airoha: en7581: cpu-hot trip type prevents passive CPU throttling
- [Medium] arm64: dts: airoha: en7581: thermal-sensors cell count mismatch in cpu-thermal
- [Medium] arm64: dts: airoha: en7581: thermal-sensor reg size smaller than driver offsets
--

commit 32580fdfac9a302b9b8e002dc32934288d0d3428
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add thermal sensor nodes

This commit adds the thermal-sensor node and cpu-thermal zone to the Airoha
EN7581 device tree and links the CPUs as cooling devices.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index fbc5ee47523ca..58bd8b318910e 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi

[ ... ]

> @@ -293,6 +298,39 @@ timer {
>  			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>  	};
>  
> +	thermal-zones {
> +		cpu_thermal: cpu-thermal {
> +			polling-delay-passive = <0>;
> +			polling-delay = <0>;
> +
> +			thermal-sensors = <&thermal 0>;

[Severity: Medium]
Should thermal-sensors in cpu_thermal be <&thermal> without the trailing 0
cell?

Below, the thermal node declares #thermal-sensor-cells = <0>, matching
Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml:

  '#thermal-sensor-cells':
    const: 0

When of_thermal_zone_find() in drivers/thermal/thermal_of.c parses
thermal-sensors = <&thermal 0> with #thermal-sensor-cells = <0>,
of_count_phandle_with_args() consumes 0 argument cells for &thermal and
treats the trailing 0 as a second phandle entry, returning count = 2:

	count = of_count_phandle_with_args(child, "thermal-sensors",
					   "#thermal-sensor-cells");
	if (count <= 0) {
		pr_err("%pOFP: missing thermal sensor\n", child);
		return ERR_PTR(-EINVAL);
	}

	for (i = 0; i < count; i++) {

		int ret;

		ret = of_parse_phandle_with_args(child, "thermal-sensors",
						 "#thermal-sensor-cells",
						 i, &sensor_specs);

This fails dtbs_check against thermal-zones.yaml (where thermal-sensors has
maxItems: 1) as well as dtc's thermal_sensors_property check, and causes
of_parse_phandle_with_args() at index 1 to return -ENOENT if
of_thermal_zone_find() iterates past index 0.

> +
> +			trips {
> +				cpu_hot: cpu-hot {
> +					temperature = <95000>;
> +					hysteresis = <1000>;
> +					type = "hot";
> +				};
> +
> +				cpu-critical {
> +					temperature = <120000>;
> +					hysteresis = <1000>;
> +					type = "critical";
> +				};
> +			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu_hot>;
> +					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};

[Severity: High]
With cpu_hot configured as type = "hot" and polling-delay-passive = <0>, can
passive CPU frequency throttling ever activate at 95 C?

In drivers/thermal/thermal_core.c, thermal_trip_crossed() handles
THERMAL_TRIP_HOT via handle_critical_trips() (which only calls tz->ops.hot()
if implemented, whereas en7581_thdev_ops in drivers/thermal/airoha_thermal.c
does not define .hot) without incrementing tz->passive, and
thermal_governor_trip_crossed() returns early:

	if (trip->type == THERMAL_TRIP_HOT || trip->type == THERMAL_TRIP_CRITICAL)
		return;

All in-kernel thermal governors also skip THERMAL_TRIP_HOT trips, such as
step_wise_manage() in drivers/thermal/gov_step_wise.c:

		if (trip->temperature == THERMAL_TEMP_INVALID ||
		    trip->type == THERMAL_TRIP_CRITICAL ||
		    trip->type == THERMAL_TRIP_HOT)
			continue;

As a result, the cooling devices (&cpu0 through &cpu3) mapped to &cpu_hot in
map0 are never throttled when the sensor crosses 95000 mC.

In addition, even if cpu_hot is changed to type = "passive", setting
polling-delay-passive = <0> leaves tz->passive_delay_jiffies at 0 in
monitor_thermal_zone() in drivers/thermal/thermal_core.c:

static void monitor_thermal_zone(struct thermal_zone_device *tz)
{
	if (tz->passive > 0 && tz->passive_delay_jiffies)
		thermal_zone_device_set_polling(tz, tz->passive_delay_jiffies);
	else if (tz->polling_delay_jiffies)
		thermal_zone_device_set_polling(tz, tz->polling_delay_jiffies);
}

Once the 95000 mC trip is crossed, en7581_thermal_set_trips() in
drivers/thermal/airoha_thermal.c sets the hardware interrupt thresholds to
low = 93999 mC and high = 120000 mC, so no further interrupts fire between
95 C and 120 C; without a non-zero polling-delay-passive, an incremental
governor like step_wise will only step down by a single OPP upon crossing
95 C and will not throttle further as temperature rises toward 120 C.

Should cpu_hot use type = "passive" along with a non-zero
polling-delay-passive?

> +		};
> +	};
> +
>  	clk20m: clock-20000000 {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
> @@ -319,6 +357,15 @@ gic: interrupt-controller@9000000 {
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>  		};
>  
> +		thermal: thermal-sensor@1efbd000 {
> +			compatible = "airoha,en7581-thermal";
> +			reg = <0x0 0x1efbd000 0x0 0xd5c>;

[Severity: Medium]
Is the reg size of 0xd5c large enough for all registers accessed by the
airoha_thermal driver?

In drivers/thermal/airoha_thermal.c, the driver defines calibration
registers up to offset 0xf28:

#define EN7581_EFUSE_TEMP_OFFSET_REG		0xf20 /* PTPSPARE0 */
#define   EN7581_EFUSE_TEMP_OFFSET		GENMASK(31, 16)
#define EN7581_PTPSPARE1			0xf24 /* PTPSPARE1 */
#define EN7581_EFUSE_TEMP_CPU_SENSOR_REG	0xf28 /* PTPSPARE2 */

During probe, en7581_thermal_probe() maps resource 0 via
devm_platform_ioremap_resource(pdev, 0) and calls
en7581_thermal_setup_adc_val(), which reads offsets 0xf20 and 0xf28 from
priv->map:

	regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info);
	if (efuse_calib_info) {
		priv->default_offset = FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib_info);
		/* Different slope are applied if the sensor is used for CPU or for package */
		regmap_read(priv->map, EN7581_EFUSE_TEMP_CPU_SENSOR_REG, &cpu_sensor);

Since 0xf28..0xf2b lies beyond the declared 0xd5c region size, should reg
have a size of at least 0xf2c (as in the binding example in
Documentation/devicetree/bindings/thermal/airoha,en7581-thermal.yaml)?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=4

Re: [PATCH 5/9] arm64: dts: airoha: en7581: add watchdog node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: airoha: watchdog reg size 0x38 excludes WDT_RELOAD at 0x38
--

commit 285873958d4bd82b85e9f3812fdf852db2de2884
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add watchdog node

This commit adds the watchdog device tree node to en7581.dtsi to handle
system stalls and reboots.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index 58bd8b318910e..3a4a4fb0eba9b 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -484,6 +484,14 @@ uart1: serial@1fbf0000 {
>  			clock-frequency = <1843200>;
>  		};
>  
> +		watchdog@1fbf0100 {
> +			compatible = "airoha,en7581-wdt";
> +			reg = <0x0 0x1fbf0100 0x0 0x38>;

[Severity: Medium]
Should the reg size in watchdog@1fbf0100 be 0x3c instead of 0x38?

In drivers/watchdog/airoha_wdt.c, WDT_RELOAD is defined at offset 0x38 and is
accessed as a 32-bit register in airoha_wdt_ping() when pinging or resuming
the watchdog:

#define WDT_RELOAD			0x38
#define   WDT_RLD			BIT(0)
...
static int airoha_wdt_ping(struct watchdog_device *wdd)
{
	struct airoha_wdt_desc *airoha_wdt = watchdog_get_drvdata(wdd);
	u32 val;

	val = readl(airoha_wdt->base + WDT_RELOAD);
	val |= WDT_RLD;
	writel(val, airoha_wdt->base + WDT_RELOAD);

	return 0;
}

With a size of 0x38, the resource mapped via devm_platform_ioremap_resource()
in airoha_wdt_probe() only covers offsets 0x00 through 0x37, leaving the
4-byte WDT_RELOAD register at 0x38..0x3b outside the declared MMIO resource
region (and the binding example in
Documentation/devicetree/bindings/watchdog/airoha,en7581-wdt.yaml also uses
0x3c).

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=5

Re: [PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] arm64: dts: airoha: undocumented UART compatibles break serial console
- [Medium] arm64: dts: airoha: uart1 retains ns16550 workaround clock-frequency
--

commit 6e4317a9ed5754fa0011125ce3517c077746d85a
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart

This commit adds Device Tree nodes for the HSUART and additional UART
controllers on the Airoha EN7581 SoC, and updates the compatible string
on the existing uart1 node from "ns16550" to "airoha,en7523-uart".

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index 760f0c3e60904..ee1633f01068e 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -470,13 +470,24 @@ fixed-link {
>  			};
>  		};
>  
> +		serial@1fbe1000 {
> +			compatible = "airoha,an7581-hsuart";
> +			reg = <0x0 0x1fbe1000 0x0 0x40>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <7372800>;
> +
> +			status = "disabled";
> +		};
> +
>  		pbus_csr: syscon@1fbe3400 {
>  			compatible = "airoha,en7581-pbus-csr", "syscon";
>  			reg = <0x0 0x1fbe3400 0x0 0xff>;
>  		};
>  
>  		uart1: serial@1fbf0000 {
> -			compatible = "ns16550";
> +			compatible = "airoha,en7523-uart";
>  			reg = <0x0 0x1fbf0000 0x0 0x30>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;

[Severity: High]
Does replacing compatible = "ns16550" with "airoha,en7523-uart" on uart1
(serial@1fbf0000) without a fallback compatible break earlycon and the
serial console on EN7581 boards?

In arch/arm64/boot/dts/airoha/en7581-evb.dts, uart1 is selected as the
console via stdout-path:

	aliases {
		serial0 = &uart1;
	};

	chosen {
		stdout-path = "serial0:115200n8";

Neither "airoha,en7523-uart" (used in uart1, serial@1fbf0300,
serial@1fbf0600, and serial@1fbf0700) nor "airoha,an7581-hsuart" (used in
serial@1fbe1000) is documented in Documentation/devicetree/bindings/serial/
or matched by any driver in the tree, such as of_platform_serial_table in
drivers/tty/serial/8250/8250_of.c:

static const struct of_device_id of_platform_serial_table[] = {
	{ .compatible = "ns8250",   .data = (void *)PORT_8250, },
	{ .compatible = "ns16450",  .data = (void *)PORT_16450, },
	{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
	{ .compatible = "ns16550",  .data = (void *)PORT_16550, },

Without corresponding binding schemas, driver support, or a fallback
compatible on uart1, won't dtbs_check fail on all five serial nodes and
leave uart1 unable to bind during early_init_dt_scan_chosen_stdout() and
of_platform_serial_driver probing?

> @@ -517,6 +528,39 @@ en7581_pwm: pwm {
>  			};
>  		};
>  
> +		serial@1fbf0300 {
> +			compatible = "airoha,en7523-uart";
> +			reg = <0x0 0x1fbf0300 0x0 0x30>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <7372800>;
> +
> +			status = "disabled";
> +		};

[Severity: Medium]
Should uart1 (serial@1fbf0000) also have its clock-frequency updated to
7372800 when switching its compatible to "airoha,en7523-uart"?

The three new "airoha,en7523-uart" nodes (serial@1fbf0300, serial@1fbf0600,
and serial@1fbf0700) all use clock-frequency = <7372800>, whereas uart1 in
arch/arm64/boot/dts/airoha/en7581.dtsi keeps clock-frequency = <1843200>:

		uart1: serial@1fbf0000 {
			compatible = "airoha,en7523-uart";
			reg = <0x0 0x1fbf0000 0x0 0x30>;
			reg-io-width = <4>;
			reg-shift = <2>;
			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <1843200>;
		};

As noted in arch/mips/boot/dts/econet/en751221.dtsi for serial@1fbf0000,
1843200 was a workaround for the generic "ns16550" driver to fix the port
at 115200 baud:

	uart: serial@1fbf0000 {
		compatible = "ns16550";
		...
		/*
		 * Conversion of baud rate to clock frequency requires a
		 * computation that is not in the ns16550 driver, so this
		 * uart is fixed at 115200 baud.
		 */
		clock-frequency = <1843200>;
	};

If a driver matching "airoha,en7523-uart" computes baud-rate divisors from
clock-frequency, won't keeping 1843200 on uart1 cause a 4x baud-rate
mismatch compared to the other "airoha,en7523-uart" nodes?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=7

Re: [PATCH 8/9] arm64: dts: airoha: en7581: add crypto node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] arm64: dts: airoha: unbound UART compatibles break EN7581 serial console
- [Medium] arm64: dts: airoha: watchdog@1fbf0100 reg size 0x38 excludes WDT_RELOAD
- [Medium] arm64: dts: airoha: thermal@1efbd000 reg size 0xd5c excludes 0xf20..0xf28
- [Low] arm64: dts: airoha: undocumented airoha,en7581-chip-scu syscon compatible
--

commit 4273f644e034fd0b9c1514ce767c400e4a6f58a5
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add crypto node

This series reorders and extends the Airoha EN7581 device tree with CPU OPP,
Chip-SCU, thermal sensor, watchdog, PWM, UART/HSUART, and EIP93 crypto nodes.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index ff6908a76e8eb..f214fa3a3e2bb 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi

[ ... ]

> @@ -150,6 +357,15 @@ gic: interrupt-controller@9000000 {
>  			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>  		};
>  
> +		thermal: thermal-sensor@1efbd000 {
> +			compatible = "airoha,en7581-thermal";
> +			reg = <0x0 0x1efbd000 0x0 0xd5c>;

[Severity: Medium]
Is the register region size of 0xd5c on thermal-sensor@1efbd000 (added in
commit 32580fdfac9a ("arm64: dts: airoha: en7581: add thermal sensor nodes"))
large enough for the registers accessed by the thermal driver?

During probe, en7581_thermal_probe() -> en7581_thermal_setup_adc_val() in
drivers/thermal/airoha_thermal.c reads calibration registers at offsets 0xf20
(EN7581_EFUSE_TEMP_OFFSET_REG) and 0xf28 (EN7581_EFUSE_TEMP_CPU_SENSOR_REG):

    regmap_read(priv->map, EN7581_EFUSE_TEMP_OFFSET_REG, &efuse_calib_info);
    if (efuse_calib_info) {
        priv->default_offset = FIELD_GET(EN7581_EFUSE_TEMP_OFFSET, efuse_calib_info);
        /* Different slope are applied if the sensor is used for CPU or for package */
        regmap_read(priv->map, EN7581_EFUSE_TEMP_CPU_SENSOR_REG, &cpu_sensor);

Since both offsets exceed 0xd5c, should the reg size be at least 0xf2c so
these reads stay within the declared resource bounds?

[ ... ]

> @@ -173,16 +389,9 @@ spi_nand: nand@0 {
>  			};
>  		};
>  
> -		scuclk: clock-controller@1fb00000 {
> -			compatible = "airoha,en7581-scu";
> -			reg = <0x0 0x1fb00000 0x0 0x970>;
> -			#clock-cells = <1>;
> -			#reset-cells = <1>;
> -		};
> -
> -		pbus_csr: syscon@1fbe3400 {
> -			compatible = "airoha,en7581-pbus-csr", "syscon";
> -			reg = <0x0 0x1fbe3400 0x0 0xff>;
> +		chip_scu: syscon@1fa20000 {
> +			compatible = "airoha,en7581-chip-scu", "syscon";
> +			reg = <0x0 0x1fa20000 0x0 0x388>;
>  		};

[Severity: Low]
Does chip_scu: syscon@1fa20000 (added in commit bb621c4a83bc ("arm64: dts:
airoha: en7581: add Chip-SCU accessor node")) pass dtbs_check?

In Documentation/devicetree/bindings/mfd/syscon.yaml, the compatible enum
includes "airoha,en7581-pbus-csr" and "econet,en751221-chip-scu", but
"airoha,en7581-chip-scu" is not listed in that schema or any other binding.
Should "airoha,en7581-chip-scu" be documented in the syscon binding schema?

[ ... ]

> +		serial@1fbe1000 {
> +			compatible = "airoha,an7581-hsuart";
> +			reg = <0x0 0x1fbe1000 0x0 0x40>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <7372800>;
> +
> +			status = "disabled";
> +		};
> +
> +		pbus_csr: syscon@1fbe3400 {
> +			compatible = "airoha,en7581-pbus-csr", "syscon";
> +			reg = <0x0 0x1fbe3400 0x0 0xff>;
> +		};
> +
> +		uart1: serial@1fbf0000 {
> +			compatible = "airoha,en7523-uart";
> +			reg = <0x0 0x1fbf0000 0x0 0x30>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <1843200>;
> +		};

[Severity: High]
Can the serial driver still bind to uart1 (serial@1fbf0000) or the newly
added serial@1fbe1000, serial@1fbf0300, serial@1fbf0600, and serial@1fbf0700
nodes after commit 6e4317a9ed57 ("arm64: dts: airoha: en7581: add nodes for
all supported uart and hsuart")?

Previously, uart1: serial@1fbf0000 used compatible = "ns16550", which matched
of_platform_serial_table in drivers/tty/serial/8250/8250_of.c:

    static const struct of_device_id of_platform_serial_table[] = {
        { .compatible = "ns8250",   .data = (void *)PORT_8250, },
        { .compatible = "ns16450",  .data = (void *)PORT_16450, },
        { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
        { .compatible = "ns16550",  .data = (void *)PORT_16550, },

Replacing "ns16550" with "airoha,en7523-uart" (and using
"airoha,an7581-hsuart" on serial@1fbe1000) without a fallback compatible leaves
these nodes unmatched by any driver under drivers/tty/serial/ and undocumented
in Documentation/devicetree/bindings/serial/8250.yaml. On en7581-evb.dts,
where serial0 aliases uart1 for stdout-path, won't this regression break the
serial console on boot?

> +
> +		watchdog@1fbf0100 {
> +			compatible = "airoha,en7581-wdt";
> +			reg = <0x0 0x1fbf0100 0x0 0x38>;

[Severity: Medium]
Does the reg size of 0x38 on watchdog@1fbf0100 (added in commit 285873958d4b
("arm64: dts: airoha: en7581: add watchdog node")) exclude the WDT_RELOAD
register at offset 0x38?

In drivers/watchdog/airoha_wdt.c, WDT_RELOAD is defined at offset 0x38, and
airoha_wdt_ping() performs 32-bit accesses at 0x38..0x3b:

    val = readl(airoha_wdt->base + WDT_RELOAD);
    val |= WDT_RLD;
    writel(val, airoha_wdt->base + WDT_RELOAD);

The binding example in
Documentation/devicetree/bindings/watchdog/airoha,en7581-wdt.yaml also lists:

    watchdog@1fbf0100 {
        compatible = "airoha,en7581-wdt";
        reg = <0x1fbf0100 0x3c>;

Should the reg size in en7581.dtsi be 0x3c instead of 0x38?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=8

Re: [PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [Medium] arm64: dts: airoha: missing interrupts property on en7581 internal switch PHYs
- [Low] arm64: dts: airoha: invalid #address-cells/#size-cells on en7581 switch node
- [Low] arm64: dts: airoha: misplaced phy-mode property on en7581 ethernet-phy nodes
--

commit f50b3495d44d1f59372ccf1eb2beb38da392948c
Author: Christian Marangi <ansuelsmth@gmail.com>

arm64: dts: airoha: en7581: add integrated switch node

This patch adds the integrated switch node for the Airoha EN7581 SoC,
including its ports, internal MDIO bus, internal PHY nodes, and PHY LED
subnodes.

> diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
> index f214fa3a3e2bb..83ae41271f96f 100644
> --- a/arch/arm64/boot/dts/airoha/en7581.dtsi
> +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
> @@ -4,6 +4,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/clock/en7523-clk.h>
>  #include <dt-bindings/reset/airoha,en7581-reset.h>
> +#include <dt-bindings/leds/common.h>
>  #include <dt-bindings/thermal/thermal.h>
>  
>  / {
> @@ -470,6 +471,152 @@ fixed-link {
>  			};
>  		};
>  
> +		switch: switch@1fb58000 {
> +			compatible = "airoha,en7581-switch";
> +			reg = <0 0x1fb58000 0 0x8000>;
> +			resets = <&scuclk EN7581_GSW_RST>;
> +
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			status = "disabled";
> +
> +			#address-cells = <1>;
> +			#size-cells = <1>;

[Severity: Low]
Should #address-cells and #size-cells be dropped from switch@1fb58000?

The binding schema in
Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml sets
unevaluatedProperties: false and only allows #address-cells and #size-cells
inside the ports and mdio child nodes, not on the top-level switch node.

In addition, because switch@1fb58000 has no ranges or dma-ranges property and
its direct children (ports and mdio) do not use reg or ranges,
check_avoid_unnecessary_addr_size() in scripts/dtc/checks.c warns about
unnecessary #address-cells/#size-cells when building with W=1.

> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				gsw_port1: port@1 {
> +					reg = <1>;
> +					phy-mode = "internal";
> +					phy-handle = <&gsw_phy1>;
> +				};

[ ... ]

> +			mdio: mdio {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				gsw_phy1: ethernet-phy@9 {
> +					compatible = "ethernet-phy-ieee802.3-c22";
> +					reg = <9>;

[Severity: Medium]
Are gsw_phy1 through gsw_phy4 missing interrupts properties referencing the
switch interrupt controller?

Above, switch@1fb58000 is configured as an interrupt-controller wired to
GIC_SPI 31, and mt7530_setup_irq() registers the switch regmap_irq_chip
domain. However, in drivers/net/dsa/mt7530.c:mt7530_setup_mdio():

	if (priv->irq_domain && !mnp)
		mt7530_setup_mdio_irq(priv);

	ret = devm_of_mdiobus_register(dev, bus, mnp);

when an explicit mdio child node (mnp) is present in the device tree,
mt7530_setup_mdio_irq() is skipped (and only covers PHY addresses 0..4 in any
case). Instead, devm_of_mdiobus_register() calls
fwnode_mdiobus_phy_device_register() -> fwnode_irq_get(child, 0) on each
ethernet-phy node.

Without interrupts properties on gsw_phy1, gsw_phy2, gsw_phy3, and gsw_phy4,
fwnode_irq_get() fails and all four internal PHYs fall back to PHY_POLL
instead of using the switch's link-change interrupts.

> +					phy-mode = "internal";

[Severity: Low]
Is phy-mode = "internal" intended on the ethernet-phy@9 through
ethernet-phy@c nodes (gsw_phy1..gsw_phy4)?

The phy-mode property is a MAC/DSA port property defined in
Documentation/devicetree/bindings/net/ethernet-controller.yaml and is already
present on the corresponding switch port nodes gsw_port1..gsw_port4, whereas
Documentation/devicetree/bindings/net/ethernet-phy.yaml does not define
phy-mode on PHY nodes.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261026095727.31708-1-ansuelsmth@gmail.com?part=9