Re: [PATCH v3 05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support

[Jie Luo <jie.luo@oss.qualcomm.com>]

On 9/3/2026 7:56 PM, Konrad Dybcio wrote:
> On 8/14/26 2:48 PM, Luo Jie wrote:
>> The NSS (network subsystem) clock's parent is cmn_pll_div2 (CMN PLL
>> rate / 2); it is then further divided by a configurable 6-bit divider.
>>
>> Register the NSS clock through a new ipq_cmn_pll_regmap_div_register()
>> helper, built as a plain struct clk_regmap_div instance instead of
>> hand-rolling recalc_rate/set_rate. The helper takes the register field
>> mask and clock name as parameters so that the upcoming PPE clock, which
>> shares the same register with a different field, can reuse it.
>>
>> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
>> ---
> 
> [...]
> 
>> +static struct clk_hw *ipq_cmn_pll_regmap_div_register(struct platform_device *pdev,
>> +						      struct regmap *regmap,
>> +						      struct clk_hw *parent_hw,
>> +						      const char *name,
>> +						      u32 field_mask)
> 
> Since we're doing clk_regmap now, you can just use the clk/qcom/common.c
> infrastructure instead of NIH-ing it..
> 
> Konrad

Thanks for taking a look. To clarify, this helper is already built on
struct clk_regmap_div from clk-regmap-divider.h, using .ops =
&clk_regmap_div_ops; it does not implement its own recalc_rate or
set_rate operations.

The wrapper only derives the shift and width from field_mask and calls
devm_clk_register_regmap(). Since the NSS and PPE clocks use different
fields within the same register, this avoids duplicating the
registration boilerplate.