Re: [PATCH v3 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 8/14/26 2:48 PM, Luo Jie wrote:
> Some CMN PLL output clocks require a hardware gate in addition to a
> fixed rate. The gate control bits reside in the register
> CMN_PLL_OUTPUT_RELATED_1 (0x79c). Each such clock is registered via a
> new struct clk_fixed_gate and clk_fixed_gate_ops, combining a fixed
> rate with enable/disable/is_enabled gate control through the shared
> regmap for CMN_PLL_OUTPUT_RELATED_1.

[...]

> +static int clk_fixed_gate_enable(struct clk_hw *hw)
> +{
> +	struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw);
> +
> +	return regmap_set_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1,
> +			       BIT(gate_clk->enable_bit));
> +}
> +
> +static void clk_fixed_gate_disable(struct clk_hw *hw)
> +{
> +	struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw);
> +
> +	regmap_clear_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1,
> +			  BIT(gate_clk->enable_bit));
> +}
> +
> +static int clk_fixed_gate_is_enabled(struct clk_hw *hw)
> +{
> +	struct clk_fixed_gate *gate_clk = to_clk_fixed_gate(hw);
> +
> +	return regmap_test_bits(gate_clk->regmap, CMN_PLL_OUTPUT_RELATED_1,
> +				BIT(gate_clk->enable_bit));
> +}

This is also all just clk_regmap / clk_branch

Konrad