Re: [PATCH v3 07/12] clk: qcom: ipq-cmn-pll: Add PON reference clock support

[Jie Luo <jie.luo@oss.qualcomm.com>]

On 9/3/2026 7:57 PM, Konrad Dybcio wrote:
> On 8/14/26 2:48 PM, Luo Jie wrote:
>> The PON (Passive Optical Network) reference clock's parent is
>> cmn_pll_div2 (CMN PLL rate / 2); it is then further divided by a
>> configurable 8-bit divider (1-255). The clock supports two modes:
> 
> [...]
> 
>> +static const struct clk_ops clk_pon_clk_ops = {
>> +	.enable = clk_pon_clk_enable,
> 
> clk_enable_regmap
>> +	.disable = clk_pon_clk_disable,
> 
> clk_disable_regmap
> 
>> +	.is_enabled = clk_pon_clk_is_enabled,
> 
> clk_is_enabled_regmap
> 
>> +	.recalc_rate = clk_pon_clk_recalc_rate,
>> +	.determine_rate = clk_pon_clk_determine_rate,
>> +	.set_rate = clk_pon_clk_set_rate,
> 
> These seem genuinely new
> 
> Konrad

Thanks. I’ll fix this by converting the PON clock to struct clk_regmap,
setting enable_reg and enable_mask, and using clk_enable_regmap,
clk_disable_regmap, and clk_is_enabled_regmap for the corresponding
operations. I’ll retain the custom recalc_rate, determine_rate, and
set_rate implementations as suggested.