From: Jie Luo <jie.luo@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com,
quic_leiwei@quicinc.com, quic_suruchia@quicinc.com
Subject: Re: [PATCH v3 04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock
Date: Thu, 3 Sep 2026 23:02:26 +0800 [thread overview]
Message-ID: <a032745b-e4d1-409d-865c-49e7cd408906@oss.qualcomm.com> (raw)
In-Reply-To: <219ad037-ff37-40fa-babd-21276ff23f50@oss.qualcomm.com>
On 9/3/2026 7:55 PM, Konrad Dybcio wrote:
> On 8/14/26 2:48 PM, Luo Jie wrote:
>> Most CMN PLL output clocks are derived from the 12 GHz PLL output
>> through a shared, physical /2 stage, ahead of any further per-clock
>> processing: a gated fixed rate (PCS/ETH0/ETH1/ETH2/EPHY/ETH), a
>> configurable divider (NSS/PPE/PON), or a rate-select bit (EPHY-RAW).
>> This /2 stage is present in the CMN PLL block on every SoC supported
>> by this driver, not just IPQ5210.
>
> I'm not sure how the mention of IPQ5210 here is significant
>
> Konrad
The /2 stage is common to all SoCs supported by this driver. I will
remove the platform-specific mention and keep the explanation generic.
next prev parent reply other threads:[~2026-09-03 15:02 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-14 12:48 [PATCH v3 00/12] clk: qcom: ipq-cmn-pll: Add IPQ5210 CMN PLL support Luo Jie
2026-08-14 12:48 ` [PATCH v3 01/12] clk: qcom: ipq-cmn-pll: Use devm_clk_hw_register_fixed_rate_parent_data Luo Jie
2026-09-03 13:02 ` Abel Vesa
2026-08-14 12:48 ` [PATCH v3 02/12] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoC Luo Jie
2026-08-14 12:48 ` [PATCH v3 03/12] clk: qcom: clk-regmap-divider: Support CLK_DIVIDER_* flags Luo Jie
2026-08-14 12:59 ` sashiko-bot
2026-09-03 13:10 ` Abel Vesa
2026-08-14 12:48 ` [PATCH v3 04/12] clk: qcom: ipq-cmn-pll: Register CMN PLL /2 clock Luo Jie
2026-09-03 11:55 ` Konrad Dybcio
2026-09-03 15:02 ` Jie Luo [this message]
2026-09-03 13:18 ` Abel Vesa
2026-09-03 15:06 ` Jie Luo
2026-08-14 12:48 ` [PATCH v3 05/12] clk: qcom: ipq-cmn-pll: Add NSS clock support Luo Jie
2026-09-03 11:56 ` Konrad Dybcio
2026-09-03 15:14 ` Jie Luo
2026-09-03 13:23 ` Abel Vesa
2026-08-14 12:48 ` [PATCH v3 06/12] clk: qcom: ipq-cmn-pll: Add PPE " Luo Jie
2026-09-03 13:03 ` Abel Vesa
2026-08-14 12:48 ` [PATCH v3 07/12] clk: qcom: ipq-cmn-pll: Add PON reference " Luo Jie
2026-09-03 11:57 ` Konrad Dybcio
2026-09-03 15:21 ` Jie Luo
2026-09-03 13:27 ` Abel Vesa
2026-08-14 12:48 ` [PATCH v3 08/12] clk: qcom: ipq-cmn-pll: Add EPHY-RAW " Luo Jie
2026-09-03 13:08 ` Abel Vesa
2026-09-03 15:31 ` Jie Luo
2026-08-14 12:48 ` [PATCH v3 09/12] clk: qcom: ipq-cmn-pll: Add clock gate support for fixed clocks Luo Jie
2026-09-03 11:59 ` Konrad Dybcio
2026-09-03 15:36 ` Jie Luo
2026-08-14 12:48 ` [PATCH v3 10/12] clk: qcom: ipq-cmn-pll: Add all output clocks for IPQ5210 Luo Jie
2026-08-14 12:48 ` [PATCH v3 11/12] arm64: dts: qcom: ipq5210: Add CMN PLL device node Luo Jie
2026-08-14 13:01 ` sashiko-bot
2026-08-14 12:48 ` [PATCH v3 12/12] arm64: dts: qcom: Update IPQ5210 xo_board to use fixed factor clock Luo Jie
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