From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/7] gpio: pl061: use cleanup helpers for locks
Date: Tue, 13 Oct 2026 10:12:10 +0300 [thread overview]
Message-ID: <as3ZyjCdMRYpTbPP@ashevche-desk.local> (raw)
In-Reply-To: <20261009-cv75-gpio-v1-5-5836bd438423@ambarella.com>
On Fri, Oct 09, 2026 at 06:57:58PM +0800, Long Zhao via B4 Relay wrote:
> Convert raw_spinlock critical sections to guard() from cleanup.h.
...
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> - unsigned long flags;
>
> - raw_spin_lock_irqsave(&pl061->lock, flags);
> + guard(raw_spinlock_irqsave)(&pl061->lock);
+ blank line. I guess I already pointed out to this.
> regmap_clear_bits(pl061->regmap, GPIODIR, BIT(offset));
> - raw_spin_unlock_irqrestore(&pl061->lock, flags);
>
> return 0;
> }
...
> int value)
> {
> struct pl061 *pl061 = gpiochip_get_data(gc);
> - unsigned long flags;
> unsigned int mask = BIT(offset);
>
> - raw_spin_lock_irqsave(&pl061->lock, flags);
> + guard(raw_spinlock_irqsave)(&pl061->lock);
Ditto and so on...
> regmap_write(pl061->regmap, BIT(offset + PL061_DATA_OFFSET),
> !!value << offset);
...
> static int pl061_irq_type(struct irq_data *d, unsigned trigger)
> }
>
>
While at it, drop the redundant blank line here.
> - raw_spin_lock_irqsave(&pl061->lock, flags);
> + guard(raw_spinlock_irqsave)(&pl061->lock);
>
> regmap_read(pl061->regmap, GPIOIEV, &gpioiev);
> regmap_read(pl061->regmap, GPIOIS, &gpiois);
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-13 7:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 10:57 [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-09 11:32 ` Krzysztof Kozlowski
2026-10-09 10:57 ` [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-09 11:17 ` Michael Walle
2026-10-09 11:27 ` sashiko-bot
2026-10-09 10:57 ` [PATCH 3/7] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-13 7:10 ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 4/7] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 5/7] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-13 7:12 ` Andy Shevchenko [this message]
2026-10-09 10:57 ` [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-09 11:50 ` sashiko-bot
2026-10-13 7:15 ` Andy Shevchenko
2026-10-13 8:56 ` zl020895
2026-10-13 9:50 ` Andy Shevchenko
2026-10-13 10:41 ` zl020895
2026-10-09 10:58 ` [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-09 12:03 ` sashiko-bot
2026-10-13 7:17 ` Andy Shevchenko
2026-10-13 8:59 ` zl020895
2026-10-13 9:46 ` Andy Shevchenko
2026-10-09 11:32 ` [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Krzysztof Kozlowski
2026-10-13 12:58 ` Bartosz Golaszewski
2026-10-13 14:10 ` zl020895
2026-10-13 15:09 ` Bartosz Golaszewski
2026-10-13 15:36 ` zl020895
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