From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap
Date: Tue, 13 Oct 2026 10:15:37 +0300 [thread overview]
Message-ID: <as3amWxGvbUdwE7k@ashevche-desk.local> (raw)
In-Reply-To: <20261009-cv75-gpio-v1-6-5836bd438423@ambarella.com>
On Fri, Oct 09, 2026 at 06:57:59PM +0800, Long Zhao via B4 Relay wrote:
> Move get, set and direction onto gpio-regmap. ARM PL061 sets
> GPIO_REGMAP_QUIRK_SET_AFTER_DIR so the output value is written
> after the direction change.
>
> Keep a custom irqchip and irq domain. Create the domain with
> the PL061 private data and let gpio-regmap attach it.
>
> Check the chained-handler regmap_read() return and always run
> chained_irq_exit(). irq_type still ignores MMIO write returns.
>
> irq_set_parent() nests the GPIO irq_desc under the AMBA parent
> for irq_set_wake() and lockdep; checked with PROVE_LOCKING on
> CV75.
...
> -static bool pl061_is_data_reg(unsigned int reg)
> -{
> - return is_power_of_2(reg) &&
> - reg >= BIT(PL061_DATA_OFFSET) &&
> - reg <= BIT(PL061_DATA_OFFSET + PL061_GPIO_NR - 1);
> -}
> -
> -static bool pl061_volatile_reg(struct device *dev, unsigned int reg)
> -{
> - switch (reg) {
> - case GPIOMIS:
> - case GPIOIC:
> - return true;
> - default:
> - return pl061_is_data_reg(reg);
> - }
> -}
> -
> -static const struct regmap_config pl061_regmap_config = {
> - .reg_bits = 16,
> - .val_bits = 8,
> - .reg_stride = 4,
> - .max_register = GPIOIC,
> - .volatile_reg = pl061_volatile_reg,
> - .fast_io = true,
> - .use_raw_spinlock = true,
> -};
No, I have already told you do not move these. If you need to rename, just make
sure it's named accordingly in the previous patch that introduced this.
...
I have a feeling that you ignored my last review. I stop it here, you need to
carefully read *all* the comments and act accordingly.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-13 7:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 10:57 [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 1/7] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-09 11:32 ` Krzysztof Kozlowski
2026-10-09 10:57 ` [PATCH 2/7] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-09 11:17 ` Michael Walle
2026-10-09 11:27 ` sashiko-bot
2026-10-09 10:57 ` [PATCH 3/7] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-13 7:10 ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 4/7] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-09 10:57 ` [PATCH 5/7] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-13 7:12 ` Andy Shevchenko
2026-10-09 10:57 ` [PATCH 6/7] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-09 11:50 ` sashiko-bot
2026-10-13 7:15 ` Andy Shevchenko [this message]
2026-10-13 8:56 ` zl020895
2026-10-13 9:50 ` Andy Shevchenko
2026-10-13 10:41 ` zl020895
2026-10-09 10:58 ` [PATCH 7/7] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-09 12:03 ` sashiko-bot
2026-10-13 7:17 ` Andy Shevchenko
2026-10-13 8:59 ` zl020895
2026-10-13 9:46 ` Andy Shevchenko
2026-10-09 11:32 ` [PATCH 0/7] gpio: add Ambarella CV75 PL061 support Krzysztof Kozlowski
2026-10-13 12:58 ` Bartosz Golaszewski
2026-10-13 14:10 ` zl020895
2026-10-13 15:09 ` Bartosz Golaszewski
2026-10-13 15:36 ` zl020895
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