[PATCH v2 00/15] Add support for MT8195/88 DPI, HDMIv2 and DDCv2

[PATCH v2 00/15] Add support for MT8195/88 DPI, HDMIv2 and DDCv2

[AngeloGioacchino Del Regno]

Changes in v2:
 - Merged series "Add support for MT8195/8188 and Pattern Generator"
   and "drm/mediatek: Add support for HDMIv2 and DDCv2 IPs" in one
   as they are directly related, as requested by CK Hu
 - More commonization: moved some audio functions to mtk_hdmi_common
 - Fixed a bug in DDCv2 driver to allow sending a message with len=1
 - Renamed some functions in HDMIv2 to consistently use the prefix
   mtk_hdmi_v2_ across the driver
 - Added .mode_valid() callback to HDMIv2
 - Added .atomic_check() callback to HDMIv2
 - Reordered drm_bridge_funcs in HDMIv2 driver
 - Rewritten .edid_read() callback in HDMIv2 to move checking audio
   availability to bridge_pre_enable() stage, and to stop using the
   drm_edid_read_ddc() in favor of drm_edid_read()
 - Added support for API provided HDMI Helpers
 - Added .tmds_char_rate_valid() callback to HDMIv2 for HDMI helpers
 - Added .hdmi_{read,write}_infoframe() callback to HDMIv2 for helpers
 - Added support for Vendor infoframes in HDMIv2
 - Added missing audio-dai-cells to HDMIv2 binding to fix check error
 - Added more information to the HDMIv2 binding for clocks and PHY
 - Added some comments to the HDMIv2 code to clarify why the controller
   is preconfigured in bridge_pre_enable() instead of bridge_enable()
 - Added a mention of the differences in HPD between v1 and v2 to the
   commit introducing the v2 driver (v2 is not using CEC for HPD)
 - ...and tested again on HW! :-)


This series adds support for the HDMI-TX v2 Encoder and DDCv2, and for
the direct connection DPI as found in MT8195, MT8188 and their variants.

Tested on Genio 700 EVK:
 - ABIST ON: ok, pattern generated internally from HDMI is shown on
   HDMI screen at the correct resolution;
 - ABIST OFF + DPI Pattern Generator ON: ok, pattern coming from DPI is
   shown on HDMI screen at the correct resolution;
 - Can negotiate up to 4k60

and on MT8395 Radxa NIO 12L:
 - ABIST ON: ok, pattern generated internally from HDMI is shown on
   HDMI screen at the correct resolution;
 - ABIST OFF + DPI Pattern Generator ON: ok, pattern coming from DPI is
   shown on HDMI screen at the correct resolution;
 - Dual screen usecase validated (DSI + HDMI 3840x2160p 60Hz)
 - Can negotiate up to 4k60

Please note that this submission does *not* include support for HDCP
nor for CECv2, as I want this to be upstream before implementing
additional features which are not strictly required for simple
HDMI output.

Bonus in this series is the addition of support for the Pattern Generator
found in the DPI HW: since I needed this for debugging during development,
I had to code in the actual support bits and it looked like a waste of
time to just remove it.
I instead decided to clean it up and upstream it, as this will anyway come
handy for multiple things, of which the most important (imo) are:
 - Adding support for new SoCs in the future will be less time consuming
   as this driver already has the pattern generator in;
 - CI Testing might be able to make use of this to validate that the
   data that comes out is not garbled (so, to help testing display
   support in an automated manner).

AngeloGioacchino Del Regno (14):
  dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat
  drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs
  drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation
  drm/mediatek: mtk_dpi: Move pixel clock setting flow to function
  drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence
  drm/mediatek: Add support for MT8195 Digital Parallel Interface
  dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2
  drm/mediatek: mtk_cec: Switch to register as module_platform_driver
  drm/mediatek: mtk_hdmi_ddc: Switch to register as
    module_platform_driver
  drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member
  drm/mediatek: mtk_hdmi: Split driver and add common probe function
  drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge
  drm/mediatek: mtk_hdmi_common: Add OP_HDMI, vendor and product strings
  drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

Guillaume Ranquet (1):
  drm/mediatek: hdmi: Use regmap instead of iomem for main registers

 .../display/mediatek/mediatek,dpi.yaml        |    5 +
 .../mediatek/mediatek,mt8195-hdmi.yaml        |  154 ++
 drivers/gpu/drm/mediatek/Kconfig              |   19 +-
 drivers/gpu/drm/mediatek/Makefile             |    5 +
 drivers/gpu/drm/mediatek/mtk_cec.c            |    5 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c            |  311 +++-
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h       |   10 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |    2 +
 drivers/gpu/drm/mediatek/mtk_hdmi.c           |  896 ++--------
 drivers/gpu/drm/mediatek/mtk_hdmi.h           |   14 -
 drivers/gpu/drm/mediatek/mtk_hdmi_common.c    |  438 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_common.h    |  204 +++
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c       |    4 +-
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c    |  403 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h   |  263 +++
 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c        | 1488 +++++++++++++++++
 16 files changed, 3384 insertions(+), 837 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
 delete mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

-- 
2.47.0

[PATCH v2 01/15] dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat

[AngeloGioacchino Del Regno]

Add compatibles for the Digital Parallel Interface (DPI) block
found in the MT8195 and MT8188 SoCs: inside of the chip, this one
is directly connected to the HDMI block.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml   | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
index 0f1e556dc8ef..5670715efa5c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
@@ -27,6 +27,7 @@ properties:
           - mediatek,mt8188-dp-intf
           - mediatek,mt8192-dpi
           - mediatek,mt8195-dp-intf
+          - mediatek,mt8195-dpi
       - items:
           - enum:
               - mediatek,mt6795-dpi
@@ -35,6 +36,10 @@ properties:
           - enum:
               - mediatek,mt8365-dpi
           - const: mediatek,mt8192-dpi
+      - items:
+          - enum:
+              - mediatek,mt8188-dpi
+          - const: mediatek,mt8195-dpi
 
   reg:
     maxItems: 1
-- 
2.47.0

[PATCH v2 02/15] drm/mediatek: mtk_dpi: Add support for Pattern Generator in debugfs

[AngeloGioacchino Del Regno]

This IP includes a Pattern Generator which is useful for debugging
and testing purposes: add the relevant register and bits to the
mtk_dpi_regs.h header, and implement support for it in mtk_dpi.

Adding this required to introduce a .debugfs_init() callback for
the DPI bridge, which creates a "dpi_test_pattern" file in the
directory of the appropriate connector.

The pattern generator can generate various internal patterns and
this submission includes support for:
 - 256 or 1024 shades of gray in a Vertical or Horizontal Pattern
 - Vertical Color Bars
 - Frame border
 - Dot Moire

This generator also supports filling the entire screen with one
custom color, but support for that is not included in this commit.

Enabling and disabling this generator can be done by sending a
string to the dpi_test_pattern debugfs file; the pattern is
expected to be formatted as follows:

         <enable (1) or disable (0)> <pattern number>

where the pattern number can be a number from 0 to 7, excluding 5.

Of course 5 is excluded because that activates custom color fill
which, again, is not supported in this commit.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 107 ++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |   4 +
 2 files changed, 111 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 20a9d589fd75..c7143184e5de 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -6,6 +6,7 @@
 
 #include <linux/clk.h>
 #include <linux/component.h>
+#include <linux/debugfs.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>
 #include <linux/media-bus-format.h>
@@ -166,6 +167,18 @@ static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
 	writel(tmp, dpi->regs + offset);
 }
 
+static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool enable)
+{
+	u32 val;
+
+	if (enable)
+		val = FIELD_PREP(DPI_PAT_SEL, type) | DPI_PAT_EN;
+	else
+		val = 0;
+
+	mtk_dpi_mask(dpi, DPI_PATTERN0, val, DPI_PAT_SEL | DPI_PAT_EN);
+}
+
 static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
 {
 	mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
@@ -767,6 +780,99 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge,
 	return MODE_OK;
 }
 
+static int mtk_dpi_debug_tp_show(struct seq_file *m, void *arg)
+{
+	struct mtk_dpi *dpi = m->private;
+	bool en;
+	u32 val;
+
+	if (!dpi)
+		return -EINVAL;
+
+	val = readl(dpi->regs + DPI_PATTERN0);
+	en = val & DPI_PAT_EN;
+	val = FIELD_GET(DPI_PAT_SEL, val);
+
+	seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled");
+
+	if (en) {
+		seq_printf(m, "Internal pattern %d: ", val);
+		switch (val) {
+		case 0:
+			seq_puts(m, "256 Vertical Gray\n");
+			break;
+		case 1:
+			seq_puts(m, "1024 Vertical Gray\n");
+			break;
+		case 2:
+			seq_puts(m, "256 Horizontal Gray\n");
+			break;
+		case 3:
+			seq_puts(m, "1024 Horizontal Gray\n");
+			break;
+		case 4:
+			seq_puts(m, "Vertical Color bars\n");
+			break;
+		case 6:
+			seq_puts(m, "Frame border\n");
+			break;
+		case 7:
+			seq_puts(m, "Dot moire\n");
+			break;
+		default:
+			seq_puts(m, "Invalid selection\n");
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user *ubuf,
+				      size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	u32 en, type;
+	char buf[6];
+
+	if (!m || !m->private || *offp || len > sizeof(buf) - 1)
+		return -EINVAL;
+
+	memset(buf, 0, sizeof(buf));
+	if (copy_from_user(buf, ubuf, len))
+		return -EFAULT;
+
+	if (sscanf(buf, "%u %u", &en, &type) != 2)
+		return -EINVAL;
+
+	if (en < 0 || en > 1 || type < 0 || type > 7)
+		return -EINVAL;
+
+	mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en);
+	return len;
+}
+
+static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mtk_dpi_debug_tp_show, inode->i_private);
+}
+
+static const struct file_operations mtk_dpi_debug_tp_fops = {
+	.owner = THIS_MODULE,
+	.open = mtk_dpi_debug_tp_open,
+	.read = seq_read,
+	.write = mtk_dpi_debug_tp_write,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static void mtk_dpi_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
+{
+	struct mtk_dpi *dpi = bridge_to_dpi(bridge);
+
+	debugfs_create_file("dpi_test_pattern", 0640, root, dpi, &mtk_dpi_debug_tp_fops);
+}
+
 static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
 	.attach = mtk_dpi_bridge_attach,
 	.mode_set = mtk_dpi_bridge_mode_set,
@@ -779,6 +885,7 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.debugfs_init = mtk_dpi_debugfs_init,
 };
 
 void mtk_dpi_start(struct device *dev)
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index 62bd4931b344..a0b1d18bbbf7 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -235,4 +235,8 @@
 #define MATRIX_SEL_RGB_TO_JPEG		0
 #define MATRIX_SEL_RGB_TO_BT601		2
 
+#define DPI_PATTERN0		0xf00
+#define DPI_PAT_EN			BIT(0)
+#define DPI_PAT_SEL			GENMASK(6, 4)
+
 #endif /* __MTK_DPI_REGS_H */
-- 
2.47.0

[PATCH v2 03/15] drm/mediatek: mtk_dpi: Use an array for pixclk factor calculation

[AngeloGioacchino Del Regno]

Setting the TVD PLL clock requires to multiply the target pixel
clock by a specific constant factor to achieve the target PLL
frequency, and this is done to reduce jitter to acceptable levels.

On all MediaTek SoCs, the factor is not retrieved by any real kind
of calculation but rather by checking if the target pixel clock
is less than a specified frequency, hence assigning a function
pointer for just a bunch of if branches does enlarge the code
size for little reason.

Remove all SoC-specific functions, add a structure `mtk_dpi_factor`
that holds a clock frequency and corresponding PLL factor, and
declare the constraints for each SoC in form of an array of said
structure.
Instead of function pointers, this structure (and its size) is then
assigned to each SoC's platform data.

The "calculation" is then performed with a new static function
mtk_dpi_calculate_factor(dpi, mode_clk) that iterates through all
of the entries of the aforementioned array and returns the right
factor.

If no factor is found, the lowest possible factor is returned,
mimicking the same flow as all of the old per-SoC calculation
functions.

This commit brings no functional change.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 103 +++++++++++++++--------------
 1 file changed, 52 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index c7143184e5de..9f59ee679ce1 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -117,9 +117,15 @@ struct mtk_dpi_yc_limit {
 	u16 c_bottom;
 };
 
+struct mtk_dpi_factor {
+	u32 clock;
+	u8 factor;
+};
+
 /**
  * struct mtk_dpi_conf - Configuration of mediatek dpi.
- * @cal_factor: Callback function to calculate factor value.
+ * @dpi_factor: SoC-specific pixel clock PLL factor values.
+ * @num_dpi_factor: Number of pixel clock PLL factor values.
  * @reg_h_fre_con: Register address of frequency control.
  * @max_clock_khz: Max clock frequency supported for this SoCs in khz units.
  * @edge_sel_en: Enable of edge selection.
@@ -140,7 +146,8 @@ struct mtk_dpi_yc_limit {
  * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
  */
 struct mtk_dpi_conf {
-	unsigned int (*cal_factor)(int clock);
+	const struct mtk_dpi_factor *dpi_factor;
+	const u8 num_dpi_factor;
 	u32 reg_h_fre_con;
 	u32 max_clock_khz;
 	bool edge_sel_en;
@@ -515,6 +522,20 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 	return ret;
 }
 
+static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
+{
+	const struct mtk_dpi_factor *dpi_factor = dpi->conf->dpi_factor;
+	int i;
+
+	for (i = 0; i < dpi->conf->num_dpi_factor; i++) {
+		if (mode_clk <= dpi_factor[i].clock)
+			return dpi_factor[i].factor;
+	}
+
+	/* If no match try the lowest possible factor */
+	return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
+}
+
 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 				    struct drm_display_mode *mode)
 {
@@ -529,7 +550,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	unsigned int factor;
 
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
-	factor = dpi->conf->cal_factor(mode->clock);
+	factor = mtk_dpi_calculate_factor(dpi, mode_clk);
 	drm_display_mode_to_videomode(mode, &vm);
 	pll_rate = vm.pixelclock * factor;
 
@@ -964,48 +985,6 @@ static const struct component_ops mtk_dpi_component_ops = {
 	.unbind = mtk_dpi_unbind,
 };
 
-static unsigned int mt8173_calculate_factor(int clock)
-{
-	if (clock <= 27000)
-		return 3 << 4;
-	else if (clock <= 84000)
-		return 3 << 3;
-	else if (clock <= 167000)
-		return 3 << 2;
-	else
-		return 3 << 1;
-}
-
-static unsigned int mt2701_calculate_factor(int clock)
-{
-	if (clock <= 64000)
-		return 4;
-	else if (clock <= 128000)
-		return 2;
-	else
-		return 1;
-}
-
-static unsigned int mt8183_calculate_factor(int clock)
-{
-	if (clock <= 27000)
-		return 8;
-	else if (clock <= 167000)
-		return 4;
-	else
-		return 2;
-}
-
-static unsigned int mt8195_dpintf_calculate_factor(int clock)
-{
-	if (clock < 70000)
-		return 4;
-	else if (clock < 200000)
-		return 2;
-	else
-		return 1;
-}
-
 static const u32 mt8173_output_fmts[] = {
 	MEDIA_BUS_FMT_RGB888_1X24,
 };
@@ -1020,8 +999,25 @@ static const u32 mt8195_output_fmts[] = {
 	MEDIA_BUS_FMT_YUYV8_1X16,
 };
 
+static const struct mtk_dpi_factor dpi_factor_mt2701[] = {
+	{ 64000, 4 }, { 128000, 2 }, { U32_MAX, 1 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8173[] = {
+	{ 27000, 48 }, { 84000, 24 }, { 167000, 12 }, { U32_MAX, 6 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8183[] = {
+	{ 27000, 8 }, { 167000, 4 }, { U32_MAX, 2 }
+};
+
+static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
+	{ 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
+};
+
 static const struct mtk_dpi_conf mt8173_conf = {
-	.cal_factor = mt8173_calculate_factor,
+	.dpi_factor = dpi_factor_mt8173,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
 	.reg_h_fre_con = 0xe0,
 	.max_clock_khz = 300000,
 	.output_fmts = mt8173_output_fmts,
@@ -1038,7 +1034,8 @@ static const struct mtk_dpi_conf mt8173_conf = {
 };
 
 static const struct mtk_dpi_conf mt2701_conf = {
-	.cal_factor = mt2701_calculate_factor,
+	.dpi_factor = dpi_factor_mt2701,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt2701),
 	.reg_h_fre_con = 0xb0,
 	.edge_sel_en = true,
 	.max_clock_khz = 150000,
@@ -1056,7 +1053,8 @@ static const struct mtk_dpi_conf mt2701_conf = {
 };
 
 static const struct mtk_dpi_conf mt8183_conf = {
-	.cal_factor = mt8183_calculate_factor,
+	.dpi_factor = dpi_factor_mt8183,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
 	.reg_h_fre_con = 0xe0,
 	.max_clock_khz = 100000,
 	.output_fmts = mt8183_output_fmts,
@@ -1073,7 +1071,8 @@ static const struct mtk_dpi_conf mt8183_conf = {
 };
 
 static const struct mtk_dpi_conf mt8186_conf = {
-	.cal_factor = mt8183_calculate_factor,
+	.dpi_factor = dpi_factor_mt8183,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
 	.reg_h_fre_con = 0xe0,
 	.max_clock_khz = 150000,
 	.output_fmts = mt8183_output_fmts,
@@ -1091,7 +1090,8 @@ static const struct mtk_dpi_conf mt8186_conf = {
 };
 
 static const struct mtk_dpi_conf mt8192_conf = {
-	.cal_factor = mt8183_calculate_factor,
+	.dpi_factor = dpi_factor_mt8183,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8183),
 	.reg_h_fre_con = 0xe0,
 	.max_clock_khz = 150000,
 	.output_fmts = mt8183_output_fmts,
@@ -1108,7 +1108,8 @@ static const struct mtk_dpi_conf mt8192_conf = {
 };
 
 static const struct mtk_dpi_conf mt8195_dpintf_conf = {
-	.cal_factor = mt8195_dpintf_calculate_factor,
+	.dpi_factor = dpi_factor_mt8195_dp_intf,
+	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
 	.max_clock_khz = 600000,
 	.output_fmts = mt8195_output_fmts,
 	.num_output_fmts = ARRAY_SIZE(mt8195_output_fmts),
-- 
2.47.0

[PATCH v2 04/15] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function

[AngeloGioacchino Del Regno]

In preparation for adding support for the DPI IP found in MT8195
and in MT8188 used for HDMI, move the code flow for calculation
and setting of the DPI pixel clock to a separate function called
mtk_dpi_set_pixel_clk().

This was done because, on those platforms, the DPI instance that
is used for HDMI will get its pixel clock from the HDMI clock,
hence it is not necessary, nor desirable, to calculate or set
the pixel clock in DPI.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++-------------
 1 file changed, 24 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 9f59ee679ce1..378b49b6bdfb 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -536,26 +536,17 @@ static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
 	return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
 }
 
-static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
-				    struct drm_display_mode *mode)
+static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk)
 {
-	struct mtk_dpi_polarities dpi_pol;
-	struct mtk_dpi_sync_param hsync;
-	struct mtk_dpi_sync_param vsync_lodd = { 0 };
-	struct mtk_dpi_sync_param vsync_leven = { 0 };
-	struct mtk_dpi_sync_param vsync_rodd = { 0 };
-	struct mtk_dpi_sync_param vsync_reven = { 0 };
-	struct videomode vm = { 0 };
 	unsigned long pll_rate;
 	unsigned int factor;
 
 	/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
 	factor = mtk_dpi_calculate_factor(dpi, mode_clk);
-	drm_display_mode_to_videomode(mode, &vm);
-	pll_rate = vm.pixelclock * factor;
+	pll_rate = vm->pixelclock * factor;
 
 	dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
-		pll_rate, vm.pixelclock);
+		pll_rate, vm->pixelclock);
 
 	clk_set_rate(dpi->tvd_clk, pll_rate);
 	pll_rate = clk_get_rate(dpi->tvd_clk);
@@ -565,20 +556,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	 * pixels for each iteration: divide the clock by this number and
 	 * adjust the display porches accordingly.
 	 */
-	vm.pixelclock = pll_rate / factor;
-	vm.pixelclock /= dpi->conf->pixels_per_iter;
+	vm->pixelclock = pll_rate / factor;
+	vm->pixelclock /= dpi->conf->pixels_per_iter;
 
 	if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
 	    (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
-		clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
+		clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2);
 	else
-		clk_set_rate(dpi->pixel_clk, vm.pixelclock);
+		clk_set_rate(dpi->pixel_clk, vm->pixelclock);
 
-
-	vm.pixelclock = clk_get_rate(dpi->pixel_clk);
+	vm->pixelclock = clk_get_rate(dpi->pixel_clk);
 
 	dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
-		pll_rate, vm.pixelclock);
+		pll_rate, vm->pixelclock);
+}
+
+static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
+				    struct drm_display_mode *mode)
+{
+	struct mtk_dpi_polarities dpi_pol;
+	struct mtk_dpi_sync_param hsync;
+	struct mtk_dpi_sync_param vsync_lodd = { 0 };
+	struct mtk_dpi_sync_param vsync_leven = { 0 };
+	struct mtk_dpi_sync_param vsync_rodd = { 0 };
+	struct mtk_dpi_sync_param vsync_reven = { 0 };
+	struct videomode vm = { 0 };
+
+	drm_display_mode_to_videomode(mode, &vm);
+	mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
 
 	dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
 	dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
-- 
2.47.0

[PATCH v2 05/15] drm/mediatek: mtk_dpi: Add checks for reg_h_fre_con existence

[AngeloGioacchino Del Regno]

In preparation for adding support for newer DPI instances which
do support direct-pin but do not have any H_FRE_CON register,
like the one found in MT8195 and MT8188, add a branch to check
if the reg_h_fre_con variable was declared in the mtk_dpi_conf
structure for the probed SoC DPI version.

As a note, this is useful specifically only for cases in which
the support_direct_pin variable is true, so mt8195-dpintf is
not affected by any issue.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 378b49b6bdfb..79923d1bfbc9 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -430,12 +430,13 @@ static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
 
 static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
 {
-	mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
+	if (dpi->conf->reg_h_fre_con)
+		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
 }
 
 static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
 {
-	if (dpi->conf->edge_sel_en)
+	if (dpi->conf->edge_sel_en && dpi->conf->reg_h_fre_con)
 		mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
 }
 
-- 
2.47.0

[PATCH v2 06/15] drm/mediatek: Add support for MT8195 Digital Parallel Interface

[AngeloGioacchino Del Regno]

Add support for the DPI block found in the MT8195 and MT8188 SoCs.
Inside of the SoC, this block is directly connected to the HDMI IP.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 55 ++++++++++++++++++++++---
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  6 +++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 +
 3 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 79923d1bfbc9..f76d1c5b68bd 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -144,6 +144,7 @@ struct mtk_dpi_factor {
  * @csc_enable_bit: Enable bit of CSC.
  * @pixels_per_iter: Quantity of transferred pixels per iteration.
  * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
+ * @is_internal_hdmi: Specifies whether the DPI is internally connected to the HDMI block
  */
 struct mtk_dpi_conf {
 	const struct mtk_dpi_factor *dpi_factor;
@@ -164,6 +165,7 @@ struct mtk_dpi_conf {
 	u32 csc_enable_bit;
 	u32 pixels_per_iter;
 	bool edge_cfg_in_mmsys;
+	bool is_internal_hdmi;
 };
 
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
@@ -492,6 +494,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
 
 	mtk_dpi_disable(dpi);
 	clk_disable_unprepare(dpi->pixel_clk);
+	clk_disable_unprepare(dpi->tvd_clk);
 	clk_disable_unprepare(dpi->engine_clk);
 }
 
@@ -508,6 +511,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 		goto err_refcount;
 	}
 
+	ret = clk_prepare_enable(dpi->tvd_clk);
+	if (ret) {
+		dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
+		goto err_engine;
+	}
+
 	ret = clk_prepare_enable(dpi->pixel_clk);
 	if (ret) {
 		dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
@@ -517,6 +526,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
 	return 0;
 
 err_pixel:
+	clk_disable_unprepare(dpi->tvd_clk);
+err_engine:
 	clk_disable_unprepare(dpi->engine_clk);
 err_refcount:
 	dpi->refcount--;
@@ -584,7 +595,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	struct videomode vm = { 0 };
 
 	drm_display_mode_to_videomode(mode, &vm);
-	mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
+
+	if (!dpi->conf->is_internal_hdmi)
+		mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
 
 	dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
 	dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
@@ -647,10 +660,18 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
 	if (dpi->conf->support_direct_pin) {
 		mtk_dpi_config_yc_map(dpi, dpi->yc_map);
 		mtk_dpi_config_2n_h_fre(dpi);
-		mtk_dpi_dual_edge(dpi);
+		/* DPI can connect to either an external bridge or the internal HDMI encoder */
+		if (dpi->conf->is_internal_hdmi) {
+			mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
+			mtk_dpi_mask(dpi, DPI_CON,
+				     dpi->conf->input_2pixel ? DPI_INPUT_2P_EN : 0,
+				     DPI_INPUT_2P_EN);
+		} else {
+			mtk_dpi_dual_edge(dpi);
+		}
 		mtk_dpi_config_disable_edge(dpi);
 	}
-	if (dpi->conf->input_2pixel) {
+	if (dpi->conf->input_2pixel && !dpi->conf->is_internal_hdmi) {
 		mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
 			     DPINTF_INPUT_2P_EN);
 	}
@@ -919,14 +940,16 @@ void mtk_dpi_start(struct device *dev)
 {
 	struct mtk_dpi *dpi = dev_get_drvdata(dev);
 
-	mtk_dpi_power_on(dpi);
+	if (!dpi->conf->is_internal_hdmi)
+		mtk_dpi_power_on(dpi);
 }
 
 void mtk_dpi_stop(struct device *dev)
 {
 	struct mtk_dpi *dpi = dev_get_drvdata(dev);
 
-	mtk_dpi_power_off(dpi);
+	if (!dpi->conf->is_internal_hdmi)
+		mtk_dpi_power_off(dpi);
 }
 
 unsigned int mtk_dpi_encoder_index(struct device *dev)
@@ -1021,6 +1044,8 @@ static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
 	{ 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
 };
 
+static const struct mtk_dpi_factor dpi_factor_mt8195_dpi = { U32_MAX, 1 };
+
 static const struct mtk_dpi_conf mt8173_conf = {
 	.dpi_factor = dpi_factor_mt8173,
 	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
@@ -1113,6 +1138,25 @@ static const struct mtk_dpi_conf mt8192_conf = {
 	.csc_enable_bit = CSC_ENABLE,
 };
 
+static const struct mtk_dpi_conf mt8195_conf = {
+	.dpi_factor = &dpi_factor_mt8195_dpi,
+	.num_dpi_factor = 1,
+	.max_clock_khz = 594000,
+	.output_fmts = mt8183_output_fmts,
+	.num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
+	.pixels_per_iter = 1,
+	.is_ck_de_pol = true,
+	.swap_input_support = true,
+	.support_direct_pin = true,
+	.dimension_mask = HPW_MASK,
+	.hvsize_mask = HSIZE_MASK,
+	.channel_swap_shift = CH_SWAP,
+	.yuv422_en_bit = YUV422_EN,
+	.csc_enable_bit = CSC_ENABLE,
+	.is_internal_hdmi = true,
+	.input_2pixel = true,
+};
+
 static const struct mtk_dpi_conf mt8195_dpintf_conf = {
 	.dpi_factor = dpi_factor_mt8195_dp_intf,
 	.num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
@@ -1216,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
 	{ .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
 	{ .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
 	{ .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
+	{ .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
index a0b1d18bbbf7..3c24d9e9f241 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -40,6 +40,12 @@
 #define FAKE_DE_LEVEN			BIT(21)
 #define FAKE_DE_RODD			BIT(22)
 #define FAKE_DE_REVEN			BIT(23)
+
+/* DPI_CON: DPI instances */
+#define DPI_OUTPUT_1T1P_EN		BIT(24)
+#define DPI_INPUT_2P_EN			BIT(25)
+
+/* DPI_CON: DPINTF instances */
 #define DPINTF_YUV422_EN		BIT(24)
 #define DPINTF_CSC_ENABLE		BIT(26)
 #define DPINTF_INPUT_2P_EN		BIT(29)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9a8ef8558da9..ba4539150f52 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -807,6 +807,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt8195-dp-intf",
 	  .data = (void *)MTK_DP_INTF },
+	{ .compatible = "mediatek,mt8195-dpi",
+	  .data = (void *)MTK_DPI },
 	{ .compatible = "mediatek,mt2701-dsi",
 	  .data = (void *)MTK_DSI },
 	{ .compatible = "mediatek,mt8173-dsi",
-- 
2.47.0

Re: [PATCH v2 06/15] drm/mediatek: Add support for MT8195 Digital Parallel Interface

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the DPI block found in the MT8195 and MT8188 SoCs.
> Inside of the SoC, this block is directly connected to the HDMI IP.

Note: there is discussion in [1].

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20241120124420.133914-7-angelogioacchino.delregno@collabora.com/

Regards,
CK

> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c      | 55 ++++++++++++++++++++++---
>  drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  6 +++
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 +
>  3 files changed, 58 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 79923d1bfbc9..f76d1c5b68bd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -144,6 +144,7 @@ struct mtk_dpi_factor {
>   * @csc_enable_bit: Enable bit of CSC.
>   * @pixels_per_iter: Quantity of transferred pixels per iteration.
>   * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to be set in MMSYS.
> + * @is_internal_hdmi: Specifies whether the DPI is internally connected to the HDMI block
>   */
>  struct mtk_dpi_conf {
>         const struct mtk_dpi_factor *dpi_factor;
> @@ -164,6 +165,7 @@ struct mtk_dpi_conf {
>         u32 csc_enable_bit;
>         u32 pixels_per_iter;
>         bool edge_cfg_in_mmsys;
> +       bool is_internal_hdmi;
>  };
> 
>  static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
> @@ -492,6 +494,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi)
> 
>         mtk_dpi_disable(dpi);
>         clk_disable_unprepare(dpi->pixel_clk);
> +       clk_disable_unprepare(dpi->tvd_clk);
>         clk_disable_unprepare(dpi->engine_clk);
>  }
> 
> @@ -508,6 +511,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
>                 goto err_refcount;
>         }
> 
> +       ret = clk_prepare_enable(dpi->tvd_clk);
> +       if (ret) {
> +               dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret);
> +               goto err_engine;
> +       }
> +
>         ret = clk_prepare_enable(dpi->pixel_clk);
>         if (ret) {
>                 dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
> @@ -517,6 +526,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi)
>         return 0;
> 
>  err_pixel:
> +       clk_disable_unprepare(dpi->tvd_clk);
> +err_engine:
>         clk_disable_unprepare(dpi->engine_clk);
>  err_refcount:
>         dpi->refcount--;
> @@ -584,7 +595,9 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>         struct videomode vm = { 0 };
> 
>         drm_display_mode_to_videomode(mode, &vm);
> -       mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
> +
> +       if (!dpi->conf->is_internal_hdmi)
> +               mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
> 
>         dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
>         dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
> @@ -647,10 +660,18 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>         if (dpi->conf->support_direct_pin) {
>                 mtk_dpi_config_yc_map(dpi, dpi->yc_map);
>                 mtk_dpi_config_2n_h_fre(dpi);
> -               mtk_dpi_dual_edge(dpi);
> +               /* DPI can connect to either an external bridge or the internal HDMI encoder */
> +               if (dpi->conf->is_internal_hdmi) {
> +                       mtk_dpi_mask(dpi, DPI_CON, DPI_OUTPUT_1T1P_EN, DPI_OUTPUT_1T1P_EN);
> +                       mtk_dpi_mask(dpi, DPI_CON,
> +                                    dpi->conf->input_2pixel ? DPI_INPUT_2P_EN : 0,
> +                                    DPI_INPUT_2P_EN);
> +               } else {
> +                       mtk_dpi_dual_edge(dpi);
> +               }
>                 mtk_dpi_config_disable_edge(dpi);
>         }
> -       if (dpi->conf->input_2pixel) {
> +       if (dpi->conf->input_2pixel && !dpi->conf->is_internal_hdmi) {
>                 mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN,
>                              DPINTF_INPUT_2P_EN);
>         }
> @@ -919,14 +940,16 @@ void mtk_dpi_start(struct device *dev)
>  {
>         struct mtk_dpi *dpi = dev_get_drvdata(dev);
> 
> -       mtk_dpi_power_on(dpi);
> +       if (!dpi->conf->is_internal_hdmi)
> +               mtk_dpi_power_on(dpi);
>  }
> 
>  void mtk_dpi_stop(struct device *dev)
>  {
>         struct mtk_dpi *dpi = dev_get_drvdata(dev);
> 
> -       mtk_dpi_power_off(dpi);
> +       if (!dpi->conf->is_internal_hdmi)
> +               mtk_dpi_power_off(dpi);
>  }
> 
>  unsigned int mtk_dpi_encoder_index(struct device *dev)
> @@ -1021,6 +1044,8 @@ static const struct mtk_dpi_factor dpi_factor_mt8195_dp_intf[] = {
>         { 70000 - 1, 4 }, { 200000 - 1, 2 }, { U32_MAX, 1 }
>  };
> 
> +static const struct mtk_dpi_factor dpi_factor_mt8195_dpi = { U32_MAX, 1 };
> +
>  static const struct mtk_dpi_conf mt8173_conf = {
>         .dpi_factor = dpi_factor_mt8173,
>         .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8173),
> @@ -1113,6 +1138,25 @@ static const struct mtk_dpi_conf mt8192_conf = {
>         .csc_enable_bit = CSC_ENABLE,
>  };
> 
> +static const struct mtk_dpi_conf mt8195_conf = {
> +       .dpi_factor = &dpi_factor_mt8195_dpi,
> +       .num_dpi_factor = 1,
> +       .max_clock_khz = 594000,
> +       .output_fmts = mt8183_output_fmts,
> +       .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts),
> +       .pixels_per_iter = 1,
> +       .is_ck_de_pol = true,
> +       .swap_input_support = true,
> +       .support_direct_pin = true,
> +       .dimension_mask = HPW_MASK,
> +       .hvsize_mask = HSIZE_MASK,
> +       .channel_swap_shift = CH_SWAP,
> +       .yuv422_en_bit = YUV422_EN,
> +       .csc_enable_bit = CSC_ENABLE,
> +       .is_internal_hdmi = true,
> +       .input_2pixel = true,
> +};
> +
>  static const struct mtk_dpi_conf mt8195_dpintf_conf = {
>         .dpi_factor = dpi_factor_mt8195_dp_intf,
>         .num_dpi_factor = ARRAY_SIZE(dpi_factor_mt8195_dp_intf),
> @@ -1216,6 +1260,7 @@ static const struct of_device_id mtk_dpi_of_ids[] = {
>         { .compatible = "mediatek,mt8188-dp-intf", .data = &mt8195_dpintf_conf },
>         { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf },
>         { .compatible = "mediatek,mt8195-dp-intf", .data = &mt8195_dpintf_conf },
> +       { .compatible = "mediatek,mt8195-dpi", .data = &mt8195_conf },
>         { /* sentinel */ },
>  };
>  MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids);
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> index a0b1d18bbbf7..3c24d9e9f241 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
> @@ -40,6 +40,12 @@
>  #define FAKE_DE_LEVEN                  BIT(21)
>  #define FAKE_DE_RODD                   BIT(22)
>  #define FAKE_DE_REVEN                  BIT(23)
> +
> +/* DPI_CON: DPI instances */
> +#define DPI_OUTPUT_1T1P_EN             BIT(24)
> +#define DPI_INPUT_2P_EN                        BIT(25)
> +
> +/* DPI_CON: DPINTF instances */
>  #define DPINTF_YUV422_EN               BIT(24)
>  #define DPINTF_CSC_ENABLE              BIT(26)
>  #define DPINTF_INPUT_2P_EN             BIT(29)
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 9a8ef8558da9..ba4539150f52 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -807,6 +807,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
>           .data = (void *)MTK_DPI },
>         { .compatible = "mediatek,mt8195-dp-intf",
>           .data = (void *)MTK_DP_INTF },
> +       { .compatible = "mediatek,mt8195-dpi",
> +         .data = (void *)MTK_DPI },
>         { .compatible = "mediatek,mt2701-dsi",
>           .data = (void *)MTK_DSI },
>         { .compatible = "mediatek,mt8173-dsi",
> --
> 2.47.0
> 

[PATCH v2 07/15] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2

[AngeloGioacchino Del Regno]

Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
and MT8188 SoCs.

This fully supports the HDMI Specification 2.0b, hence it provides
support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
xvYCC, with output resolutions up to 3840x2160p@60Hz.

Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate
(VRR) and Consumer Electronics Control (CEC).

This IP also includes support for HDMI Audio, including IEC60958
and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio
according to HDMI 2.0.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../mediatek/mediatek,mt8195-hdmi.yaml        | 154 ++++++++++++++++++
 1 file changed, 154 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
new file mode 100644
index 000000000000..73b1dfaa1adb
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek HDMI-TX v2 Encoder
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+  - CK Hu <ck.hu@mediatek.com>
+
+description:
+  The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
+  the HDMI Specification 2.0b.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8188-hdmi-tx
+      - mediatek,mt8195-hdmi-tx
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: HDMI Peripheral Bus (APB) clock
+      - description: HDCP and HDMI_TOP clock
+      - description: HDCP and HDMI_TOP reference clock
+      - description: VPP HDMI Split clock
+
+  clock-names:
+    items:
+      - const: bus
+      - const: hdcp
+      - const: hdcp24m
+      - const: hdmi-split
+
+  i2c:
+    type: object
+    $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
+    unevaluatedProperties: false
+    description: HDMI DDC I2C controller
+
+  phys:
+    maxItems: 1
+    description: PHY providing clocking TMDS and pixel to controller
+
+  phy-names:
+    items:
+      - const: hdmi
+
+  pinctrl-0: true
+
+  pinctrl-names:
+    items:
+      - const: default
+
+  power-domains:
+    maxItems: 1
+
+  '#sound-dai-cells':
+    const: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Input port, usually connected to the output port of a DPI
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output port that must be connected either to the input port of
+          a HDMI connector node containing a ddc-i2c-bus, or to the input
+          port of an attached bridge chip, such as a SlimPort transmitter.
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - power-domains
+  - phys
+  - phy-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8195-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/mt8195-power.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        hdmi-tx@1c300000 {
+            compatible = "mediatek,mt8195-hdmi-tx";
+            reg = <0 0x1c300000 0 0x1000>;
+            clocks = <&topckgen CLK_TOP_HDMI_APB>,
+                     <&topckgen CLK_TOP_HDCP>,
+                     <&topckgen CLK_TOP_HDCP_24M>,
+                     <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+            clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
+            interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
+            phys = <&hdmi_phy>;
+            phy-names = "hdmi";
+            power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
+            pinctrl-names = "default";
+            pinctrl-0 = <&hdmi_pins>;
+            #sound-dai-cells = <1>;
+
+            hdmitx_ddc: i2c {
+                compatible = "mediatek,mt8195-hdmi-ddc";
+                clocks = <&clk26m>;
+            };
+
+            ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                    reg = <0>;
+
+                    hdmi_in: endpoint {
+                        remote-endpoint = <&dpi1_out>;
+                    };
+                };
+
+                port@1 {
+                    reg = <1>;
+
+                    hdmi_out: endpoint {
+                        remote-endpoint = <&hdmi_connector_in>;
+                    };
+                };
+            };
+        };
+    };
-- 
2.47.0

Re: [PATCH v2 07/15] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2

[Rob Herring (Arm)]

On Thu, 05 Dec 2024 12:45:09 +0100, AngeloGioacchino Del Regno wrote:
> Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
> and MT8188 SoCs.
> 
> This fully supports the HDMI Specification 2.0b, hence it provides
> support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
> color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
> xvYCC, with output resolutions up to 3840x2160p@60Hz.
> 
> Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate
> (VRR) and Consumer Electronics Control (CEC).
> 
> This IP also includes support for HDMI Audio, including IEC60958
> and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio
> according to HDMI 2.0.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../mediatek/mediatek,mt8195-hdmi.yaml        | 154 ++++++++++++++++++
>  1 file changed, 154 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml:
Error in referenced schema matching $id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.example.dtb: hdmi-tx@1c300000: i2c: False schema does not allow {'compatible': ['mediatek,mt8195-hdmi-ddc'], 'clocks': [[4294967295]]}
	from schema $id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.example.dtb: hdmi-tx@1c300000: i2c: Unevaluated properties are not allowed ('clocks', 'compatible' were unexpected)
	from schema $id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml#
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.example.dtb: /example-0/soc/hdmi-tx@1c300000/i2c: failed to match any schema with compatible: ['mediatek,mt8195-hdmi-ddc']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20241205114518.53527-8-angelogioacchino.delregno@collabora.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 07/15] dt-bindings: display: mediatek: Add binding for MT8195 HDMI-TX v2

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195
> and MT8188 SoCs.
> 
> This fully supports the HDMI Specification 2.0b, hence it provides
> support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color,
> color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and
> xvYCC, with output resolutions up to 3840x2160p@60Hz.
> 
> Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate
> (VRR) and Consumer Electronics Control (CEC).
> 
> This IP also includes support for HDMI Audio, including IEC60958
> and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio
> according to HDMI 2.0.

NOTE: There is discussion in [1].

[1] https://patchwork.kernel.org/project/linux-mediatek/patch/20241205114518.53527-8-angelogioacchino.delregno@collabora.com/

Regards,
CK

> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  .../mediatek/mediatek,mt8195-hdmi.yaml        | 154 ++++++++++++++++++
>  1 file changed, 154 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> new file mode 100644
> index 000000000000..73b1dfaa1adb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml
> @@ -0,0 +1,154 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!kB8f630CUolqkpX3ipvy1_HEGMcwQWXsfpv2JWDnW8CZckULvtoH-VsWFxMXeT035x4ETMcswV81yMrCH3cRsXiprSpF$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!kB8f630CUolqkpX3ipvy1_HEGMcwQWXsfpv2JWDnW8CZckULvtoH-VsWFxMXeT035x4ETMcswV81yMrCH3cRsfC96NsG$
> +
> +title: MediaTek HDMI-TX v2 Encoder
> +
> +maintainers:
> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +  - CK Hu <ck.hu@mediatek.com>
> +
> +description:
> +  The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on
> +  the HDMI Specification 2.0b.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - mediatek,mt8188-hdmi-tx
> +      - mediatek,mt8195-hdmi-tx
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: HDMI Peripheral Bus (APB) clock
> +      - description: HDCP and HDMI_TOP clock
> +      - description: HDCP and HDMI_TOP reference clock
> +      - description: VPP HDMI Split clock
> +
> +  clock-names:
> +    items:
> +      - const: bus
> +      - const: hdcp
> +      - const: hdcp24m
> +      - const: hdmi-split
> +
> +  i2c:
> +    type: object
> +    $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml
> +    unevaluatedProperties: false
> +    description: HDMI DDC I2C controller
> +
> +  phys:
> +    maxItems: 1
> +    description: PHY providing clocking TMDS and pixel to controller
> +
> +  phy-names:
> +    items:
> +      - const: hdmi
> +
> +  pinctrl-0: true
> +
> +  pinctrl-names:
> +    items:
> +      - const: default
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  '#sound-dai-cells':
> +    const: 1
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Input port, usually connected to the output port of a DPI
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Output port that must be connected either to the input port of
> +          a HDMI connector node containing a ddc-i2c-bus, or to the input
> +          port of an attached bridge chip, such as a SlimPort transmitter.
> +
> +    required:
> +      - port@0
> +      - port@1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - power-domains
> +  - phys
> +  - phy-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8195-clk.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/power/mt8195-power.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        hdmi-tx@1c300000 {
> +            compatible = "mediatek,mt8195-hdmi-tx";
> +            reg = <0 0x1c300000 0 0x1000>;
> +            clocks = <&topckgen CLK_TOP_HDMI_APB>,
> +                     <&topckgen CLK_TOP_HDCP>,
> +                     <&topckgen CLK_TOP_HDCP_24M>,
> +                     <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
> +            clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split";
> +            interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>;
> +            phys = <&hdmi_phy>;
> +            phy-names = "hdmi";
> +            power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
> +            pinctrl-names = "default";
> +            pinctrl-0 = <&hdmi_pins>;
> +            #sound-dai-cells = <1>;
> +
> +            hdmitx_ddc: i2c {
> +                compatible = "mediatek,mt8195-hdmi-ddc";
> +                clocks = <&clk26m>;
> +            };
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port@0 {
> +                    reg = <0>;
> +
> +                    hdmi_in: endpoint {
> +                        remote-endpoint = <&dpi1_out>;
> +                    };
> +                };
> +
> +                port@1 {
> +                    reg = <1>;
> +
> +                    hdmi_out: endpoint {
> +                        remote-endpoint = <&hdmi_connector_in>;
> +                    };
> +                };
> +            };
> +        };
> +    };
> --
> 2.47.0
> 

[PATCH v2 08/15] drm/mediatek: mtk_cec: Switch to register as module_platform_driver

[AngeloGioacchino Del Regno]

In preparation for splitting out the common bits from the HDMI
driver, change the mtk_cec driver from being registered from the
HDMI driver itself to be a module_platform_driver of its own.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_cec.c  | 5 ++++-
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 1 -
 drivers/gpu/drm/mediatek/mtk_hdmi.h | 1 -
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c
index 2de248443147..263ae3b4c4df 100644
--- a/drivers/gpu/drm/mediatek/mtk_cec.c
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -12,7 +12,6 @@
 #include <linux/platform_device.h>
 
 #include "mtk_cec.h"
-#include "mtk_hdmi.h"
 #include "mtk_drm_drv.h"
 
 #define TR_CONFIG		0x00
@@ -247,3 +246,7 @@ struct platform_driver mtk_cec_driver = {
 		.of_match_table = mtk_cec_of_ids,
 	},
 };
+module_platform_driver(mtk_cec_driver);
+
+MODULE_DESCRIPTION("MediaTek HDMI CEC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 7687f673964e..73ab88015d7f 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1805,7 +1805,6 @@ static struct platform_driver mtk_hdmi_driver = {
 
 static struct platform_driver * const mtk_hdmi_drivers[] = {
 	&mtk_hdmi_ddc_driver,
-	&mtk_cec_driver,
 	&mtk_hdmi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
index 472bf141c92b..e40bc4651995 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.h
@@ -8,7 +8,6 @@
 
 struct platform_driver;
 
-extern struct platform_driver mtk_cec_driver;
 extern struct platform_driver mtk_hdmi_ddc_driver;
 
 #endif /* _MTK_HDMI_CTRL_H */
-- 
2.47.0

[PATCH v2 09/15] drm/mediatek: mtk_hdmi_ddc: Switch to register as module_platform_driver

[AngeloGioacchino Del Regno]

In preparation for splitting out the common bits from the HDMI
driver, change the mtk_cec driver from being registered from the
HDMI driver itself to be a module_platform_driver of its own.

With this change, there are no more users of the mtk_hdmi.h header
so, while at it, also remove it.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c     |  2 --
 drivers/gpu/drm/mediatek/mtk_hdmi.h     | 13 -------------
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c |  4 ++--
 3 files changed, 2 insertions(+), 17 deletions(-)
 delete mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi.h

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 73ab88015d7f..bacb1a5289cb 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -31,7 +31,6 @@
 #include <drm/drm_probe_helper.h>
 
 #include "mtk_cec.h"
-#include "mtk_hdmi.h"
 #include "mtk_hdmi_regs.h"
 
 #define NCTS_BYTES	7
@@ -1804,7 +1803,6 @@ static struct platform_driver mtk_hdmi_driver = {
 };
 
 static struct platform_driver * const mtk_hdmi_drivers[] = {
-	&mtk_hdmi_ddc_driver,
 	&mtk_hdmi_driver,
 };
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.h b/drivers/gpu/drm/mediatek/mtk_hdmi.h
deleted file mode 100644
index e40bc4651995..000000000000
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2014 MediaTek Inc.
- * Author: Jie Qiu <jie.qiu@mediatek.com>
- */
-#ifndef _MTK_HDMI_CTRL_H
-#define _MTK_HDMI_CTRL_H
-
-struct platform_driver;
-
-extern struct platform_driver mtk_hdmi_ddc_driver;
-
-#endif /* _MTK_HDMI_CTRL_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
index 8e60631d4cd2..6358e1af69b4 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc.c
@@ -20,7 +20,6 @@
 #include <linux/of_platform.h>
 
 #include "mtk_drm_drv.h"
-#include "mtk_hdmi.h"
 
 #define SIF1_CLOK		(288)
 #define DDC_DDCMCTL0		(0x0)
@@ -331,12 +330,13 @@ MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_match);
 
 struct platform_driver mtk_hdmi_ddc_driver = {
 	.probe = mtk_hdmi_ddc_probe,
-	.remove_new = mtk_hdmi_ddc_remove,
+	.remove = mtk_hdmi_ddc_remove,
 	.driver = {
 		.name = "mediatek-hdmi-ddc",
 		.of_match_table = mtk_hdmi_ddc_match,
 	},
 };
+module_platform_driver(mtk_hdmi_ddc_driver);
 
 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
 MODULE_DESCRIPTION("MediaTek HDMI DDC Driver");
-- 
2.47.0

[PATCH v2 10/15] drm/mediatek: hdmi: Use regmap instead of iomem for main registers

[AngeloGioacchino Del Regno]

From: Guillaume Ranquet <granquet@baylibre.com>

In preparation for the addition of a new version of the HDMI IP
which will need to share its iospace between multiple subdrivers,
and in preparation for moving out the common bits between the two,
migrate this driver to fully use regmap.

Signed-off-by: Guillaume Ranquet <granquet@baylibre.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 173 +++++++++++-----------------
 1 file changed, 65 insertions(+), 108 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index bacb1a5289cb..9e8d9144cf86 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -170,7 +170,7 @@ struct mtk_hdmi {
 	u32 ibias_up;
 	struct regmap *sys_regmap;
 	unsigned int sys_offset;
-	void __iomem *regs;
+	struct regmap *regs;
 	enum hdmi_colorspace csp;
 	struct hdmi_audio_param aud_param;
 	bool audio_enable;
@@ -186,50 +186,10 @@ static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
 	return container_of(b, struct mtk_hdmi, bridge);
 }
 
-static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
-{
-	return readl(hdmi->regs + offset);
-}
-
-static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
-{
-	writel(val, hdmi->regs + offset);
-}
-
-static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
-{
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp &= ~bits;
-	writel(tmp, reg);
-}
-
-static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
-{
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp |= bits;
-	writel(tmp, reg);
-}
-
-static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
-{
-	void __iomem *reg = hdmi->regs + offset;
-	u32 tmp;
-
-	tmp = readl(reg);
-	tmp = (tmp & ~mask) | (val & mask);
-	writel(tmp, reg);
-}
-
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 {
-	mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
-		      VIDEO_SOURCE_SEL);
+	regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
+			   VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH);
 }
 
 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
@@ -264,12 +224,12 @@ static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
 
 static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
 {
-	mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
+	regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
 }
 
 static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
 {
-	mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
+	regmap_clear_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);
 }
 
 static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
@@ -278,25 +238,25 @@ static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
 			   HDMI_RST, HDMI_RST);
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 			   HDMI_RST, 0);
-	mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
+	regmap_clear_bits(hdmi->regs, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
 			   ANLG_ON, ANLG_ON);
 }
 
 static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
 {
-	mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
-		      CFG2_NOTICE_EN);
+	regmap_update_bits(hdmi->regs, GRL_CFG2, CFG2_NOTICE_EN,
+			   enable_notice ? CFG2_NOTICE_EN : 0);
 }
 
 static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
 {
-	mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
+	regmap_write(hdmi->regs, GRL_INT_MASK, int_mask);
 }
 
 static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
 {
-	mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
+	regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0);
 }
 
 static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
@@ -342,22 +302,22 @@ static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
 		dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
 		return;
 	}
-	mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
-	mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
-	mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
-	mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
+	regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
+	regmap_write(hdmi->regs, GRL_INFOFRM_TYPE, frame_type);
+	regmap_write(hdmi->regs, GRL_INFOFRM_VER, frame_ver);
+	regmap_write(hdmi->regs, GRL_INFOFRM_LNG, frame_len);
 
-	mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
+	regmap_write(hdmi->regs, GRL_IFM_PORT, checksum);
 	for (i = 0; i < frame_len; i++)
-		mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
+		regmap_write(hdmi->regs, GRL_IFM_PORT, frame_data[i]);
 
-	mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
+	regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);
 }
 
 static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
 {
-	mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
-		      AUDIO_PACKET_OFF);
+	regmap_update_bits(hdmi->regs, AUDIO_PACKET_OFF,
+			   GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF);
 }
 
 static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
@@ -378,44 +338,44 @@ static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
 
 static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
 {
-	mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
+	regmap_clear_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
 	usleep_range(2000, 4000);
-	mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
+	regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);
 }
 
 static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
 {
-	mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
-		      CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
+	regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
+			   CFG4_AV_UNMUTE_EN);
 	usleep_range(2000, 4000);
-	mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
-		      CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
+	regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,
+			   CFG4_AV_UNMUTE_SET);
 }
 
 static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
 {
-	mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
-		      CTS_CTRL_SOFT);
+	regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, CTS_CTRL_SOFT,
+			   on ? 0 : CTS_CTRL_SOFT);
 }
 
 static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
 					       bool enable)
 {
-	mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
-		      NCTS_WRI_ANYTIME);
+	regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, NCTS_WRI_ANYTIME,
+			   enable ? NCTS_WRI_ANYTIME : 0);
 }
 
 static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
 				     struct drm_display_mode *mode)
 {
-	mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
+	regmap_clear_bits(hdmi->regs, GRL_CFG4, CFG4_MHL_MODE);
 
 	if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
 	    mode->clock == 74250 &&
 	    mode->vdisplay == 1080)
-		mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
+		regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
 	else
-		mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
+		regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);
 }
 
 static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
@@ -443,7 +403,7 @@ static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
 		swap_bit = LFE_CC_SWAP;
 		break;
 	}
-	mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
+	regmap_update_bits(hdmi->regs, GRL_CH_SWAP, 0xff, swap_bit);
 }
 
 static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
@@ -464,7 +424,7 @@ static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
 		break;
 	}
 
-	mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
+	regmap_update_bits(hdmi->regs, GRL_AOUT_CFG, AOUT_BNUM_SEL_MASK, val);
 }
 
 static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
@@ -472,7 +432,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG0);
+	regmap_read(hdmi->regs, GRL_CFG0, &val);
 	val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
 
 	switch (i2s_fmt) {
@@ -496,7 +456,7 @@ static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
 		val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
 		break;
 	}
-	mtk_hdmi_write(hdmi, GRL_CFG0, val);
+	regmap_write(hdmi->regs, GRL_CFG0, val);
 }
 
 static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
@@ -505,14 +465,14 @@ static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
 	u8 val;
 
 	/* Disable high bitrate, set DST packet normal/double */
-	mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
+	regmap_clear_bits(hdmi->regs, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
 
 	if (dst)
 		val = DST_NORMAL_DOUBLE | SACD_DST;
 	else
 		val = 0;
 
-	mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
+	regmap_update_bits(hdmi->regs, GRL_AUDIO_CFG, mask, val);
 }
 
 static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
@@ -553,10 +513,10 @@ static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
 		i2s_uv = I2S_UV_CH_EN(0);
 	}
 
-	mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
-	mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
-	mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
-	mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
+	regmap_write(hdmi->regs, GRL_CH_SW0, ch_switch & 0xff);
+	regmap_write(hdmi->regs, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
+	regmap_write(hdmi->regs, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
+	regmap_write(hdmi->regs, GRL_I2S_UV, i2s_uv);
 }
 
 static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
@@ -564,7 +524,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG1);
+	regmap_read(hdmi->regs, GRL_CFG1, &val);
 	if (input_type == HDMI_AUD_INPUT_I2S &&
 	    (val & CFG1_SPDIF) == CFG1_SPDIF) {
 		val &= ~CFG1_SPDIF;
@@ -572,7 +532,7 @@ static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
 		(val & CFG1_SPDIF) == 0) {
 		val |= CFG1_SPDIF;
 	}
-	mtk_hdmi_write(hdmi, GRL_CFG1, val);
+	regmap_write(hdmi->regs, GRL_CFG1, val);
 }
 
 static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
@@ -581,13 +541,13 @@ static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
 	int i;
 
 	for (i = 0; i < 5; i++) {
-		mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
-		mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
-		mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
+		regmap_write(hdmi->regs, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
+		regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, channel_status[i]);
+		regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, channel_status[i]);
 	}
 	for (; i < 24; i++) {
-		mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
-		mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
+		regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, 0);
+		regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, 0);
 	}
 }
 
@@ -595,13 +555,13 @@ static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
 	if (val & MIX_CTRL_SRC_EN) {
 		val &= ~MIX_CTRL_SRC_EN;
-		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
+		regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
 		usleep_range(255, 512);
 		val |= MIX_CTRL_SRC_EN;
-		mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
+		regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
 	}
 }
 
@@ -609,10 +569,10 @@ static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
+	regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);
 	val &= ~MIX_CTRL_SRC_EN;
-	mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
-	mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
+	regmap_write(hdmi->regs, GRL_MIX_CTRL, val);
+	regmap_write(hdmi->regs, GRL_SHIFT_L1, 0x00);
 }
 
 static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
@@ -620,7 +580,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 {
 	u32 val;
 
-	val = mtk_hdmi_read(hdmi, GRL_CFG5);
+	regmap_read(hdmi->regs, GRL_CFG5, &val);
 	val &= CFG5_CD_RATIO_MASK;
 
 	switch (mclk) {
@@ -643,7 +603,7 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 		val |= CFG5_FS256;
 		break;
 	}
-	mtk_hdmi_write(hdmi, GRL_CFG5, val);
+	regmap_write(hdmi->regs, GRL_CFG5, val);
 }
 
 struct hdmi_acr_n {
@@ -727,9 +687,9 @@ static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 	unsigned char val[NCTS_BYTES];
 	int i;
 
-	mtk_hdmi_write(hdmi, GRL_NCTS, 0);
-	mtk_hdmi_write(hdmi, GRL_NCTS, 0);
-	mtk_hdmi_write(hdmi, GRL_NCTS, 0);
+	regmap_write(hdmi->regs, GRL_NCTS, 0);
+	regmap_write(hdmi->regs, GRL_NCTS, 0);
+	regmap_write(hdmi->regs, GRL_NCTS, 0);
 	memset(val, 0, sizeof(val));
 
 	val[0] = (cts >> 24) & 0xff;
@@ -742,7 +702,7 @@ static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 	val[6] = n & 0xff;
 
 	for (i = 0; i < NCTS_BYTES; i++)
-		mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
+		regmap_write(hdmi->regs, GRL_NCTS, val[i]);
 }
 
 static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
@@ -757,8 +717,7 @@ static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 	dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 		__func__, sample_rate, clock, n, cts);
 
-	mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
-		      AUDIO_I2S_NCTS_SEL);
+	regmap_update_bits(hdmi->regs, DUMMY_304, AUDIO_I2S_NCTS_SEL, AUDIO_I2S_NCTS_SEL_64);
 	do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
 }
 
@@ -878,7 +837,7 @@ static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 	bool dst;
 
 	mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
-	mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
+	regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT);
 
 	if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
 	    hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
@@ -910,7 +869,7 @@ static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
 
 	mtk_hdmi_hw_ncts_enable(hdmi, false);
 	mtk_hdmi_hw_aud_src_disable(hdmi);
-	mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
+	regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_ACLK_INV);
 
 	if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
 		switch (sample_rate) {
@@ -1424,7 +1383,6 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	struct device_node *cec_np, *remote, *i2c_np;
 	struct platform_device *cec_pdev;
 	struct regmap *regmap;
-	struct resource *mem;
 	int ret;
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
@@ -1470,8 +1428,7 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 	}
 	hdmi->sys_regmap = regmap;
 
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	hdmi->regs = devm_ioremap_resource(dev, mem);
+	hdmi->regs = device_node_to_regmap(dev->of_node);
 	if (IS_ERR(hdmi->regs)) {
 		ret = PTR_ERR(hdmi->regs);
 		goto put_device;
-- 
2.47.0

[PATCH v2 11/15] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member

[AngeloGioacchino Del Regno]

Rename member aud_sampe_size of struct hdmi_audio_param to
aud_sample_size to fix a typo and enhance readability.

This commit brings no functional changes.

Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 9e8d9144cf86..7808141526fa 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -136,7 +136,7 @@ enum hdmi_aud_channel_swap_type {
 
 struct hdmi_audio_param {
 	enum hdmi_audio_coding_type aud_codec;
-	enum hdmi_audio_sample_size aud_sampe_size;
+	enum hdmi_audio_sample_size aud_sample_size;
 	enum hdmi_aud_input_type aud_input_type;
 	enum hdmi_aud_i2s_fmt aud_i2s_fmt;
 	enum hdmi_aud_mclk aud_mclk;
@@ -1032,7 +1032,7 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
 
 	hdmi->csp = HDMI_COLORSPACE_RGB;
 	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-	aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
 	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
 	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
 	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
@@ -1528,14 +1528,14 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
 	switch (daifmt->fmt) {
 	case HDMI_I2S:
 		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
 		hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
 		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
 		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
 		break;
 	case HDMI_SPDIF:
 		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-		hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
 		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
 		break;
 	default:
-- 
2.47.0

Re: [PATCH v2 11/15] drm/mediatek: mtk_hdmi: Fix typo for aud_sampe_size member

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Rename member aud_sampe_size of struct hdmi_audio_param to
> aud_sample_size to fix a typo and enhance readability.
> 
> This commit brings no functional changes.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 9e8d9144cf86..7808141526fa 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -136,7 +136,7 @@ enum hdmi_aud_channel_swap_type {
> 
>  struct hdmi_audio_param {
>         enum hdmi_audio_coding_type aud_codec;
> -       enum hdmi_audio_sample_size aud_sampe_size;
> +       enum hdmi_audio_sample_size aud_sample_size;
>         enum hdmi_aud_input_type aud_input_type;
>         enum hdmi_aud_i2s_fmt aud_i2s_fmt;
>         enum hdmi_aud_mclk aud_mclk;
> @@ -1032,7 +1032,7 @@ static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
> 
>         hdmi->csp = HDMI_COLORSPACE_RGB;
>         aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -       aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +       aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
>         aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
>         aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>         aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> @@ -1528,14 +1528,14 @@ static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
>         switch (daifmt->fmt) {
>         case HDMI_I2S:
>                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -               hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +               hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
>                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
>                 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>                 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
>                 break;
>         case HDMI_SPDIF:
>                 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -               hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +               hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
>                 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
>                 break;
>         default:
> --
> 2.47.0
> 

[PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[AngeloGioacchino Del Regno]

In preparation for adding a new driver for the HDMI TX v2 IP,
split out the functions that will be common between the already
present mtk_hdmi (v1) driver and the new one.

Since the probe flow for both drivers is 90% similar, add a common
probe function that will be called from each driver's .probe()
callback, avoiding lots of code duplication.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/Kconfig           |  11 +-
 drivers/gpu/drm/mediatek/Makefile          |   1 +
 drivers/gpu/drm/mediatek/mtk_hdmi.c        | 724 +++------------------
 drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 425 ++++++++++++
 drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 203 ++++++
 5 files changed, 729 insertions(+), 635 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h

diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index f496e6cfdfe0..73459f07dae3 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -34,10 +34,19 @@ config DRM_MEDIATEK_DP
 	help
 	  DRM/KMS Display Port driver for MediaTek SoCs.
 
+config DRM_MEDIATEK_HDMI_COMMON
+	tristate
+	depends on DRM_MEDIATEK
+	select DRM_DISPLAY_HDMI_HELPER
+	select DRM_DISPLAY_HELPER
+	select SND_SOC_HDMI_CODEC if SND_SOC
+	help
+	  MediaTek SoC HDMI common library
+
 config DRM_MEDIATEK_HDMI
 	tristate "DRM HDMI Support for Mediatek SoCs"
 	depends on DRM_MEDIATEK
-	select SND_SOC_HDMI_CODEC if SND_SOC
+	select DRM_MEDIATEK_HDMI_COMMON
 	select PHY_MTK_HDMI
 	help
 	  DRM/KMS HDMI driver for Mediatek SoCs
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 32a2ed6c0cfe..8973d7ba37d3 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -25,6 +25,7 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
 			  mtk_hdmi.o \
 			  mtk_hdmi_ddc.o
 
+obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
 obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
 
 obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 7808141526fa..44b2bc55afa3 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -31,6 +31,7 @@
 #include <drm/drm_probe_helper.h>
 
 #include "mtk_cec.h"
+#include "mtk_hdmi_common.h"
 #include "mtk_hdmi_regs.h"
 
 #define NCTS_BYTES	7
@@ -43,149 +44,13 @@ enum mtk_hdmi_clk_id {
 	MTK_HDMI_CLK_COUNT
 };
 
-enum hdmi_aud_input_type {
-	HDMI_AUD_INPUT_I2S = 0,
-	HDMI_AUD_INPUT_SPDIF,
-};
-
-enum hdmi_aud_i2s_fmt {
-	HDMI_I2S_MODE_RJT_24BIT = 0,
-	HDMI_I2S_MODE_RJT_16BIT,
-	HDMI_I2S_MODE_LJT_24BIT,
-	HDMI_I2S_MODE_LJT_16BIT,
-	HDMI_I2S_MODE_I2S_24BIT,
-	HDMI_I2S_MODE_I2S_16BIT
-};
-
-enum hdmi_aud_mclk {
-	HDMI_AUD_MCLK_128FS,
-	HDMI_AUD_MCLK_192FS,
-	HDMI_AUD_MCLK_256FS,
-	HDMI_AUD_MCLK_384FS,
-	HDMI_AUD_MCLK_512FS,
-	HDMI_AUD_MCLK_768FS,
-	HDMI_AUD_MCLK_1152FS,
-};
-
-enum hdmi_aud_channel_type {
-	HDMI_AUD_CHAN_TYPE_1_0 = 0,
-	HDMI_AUD_CHAN_TYPE_1_1,
-	HDMI_AUD_CHAN_TYPE_2_0,
-	HDMI_AUD_CHAN_TYPE_2_1,
-	HDMI_AUD_CHAN_TYPE_3_0,
-	HDMI_AUD_CHAN_TYPE_3_1,
-	HDMI_AUD_CHAN_TYPE_4_0,
-	HDMI_AUD_CHAN_TYPE_4_1,
-	HDMI_AUD_CHAN_TYPE_5_0,
-	HDMI_AUD_CHAN_TYPE_5_1,
-	HDMI_AUD_CHAN_TYPE_6_0,
-	HDMI_AUD_CHAN_TYPE_6_1,
-	HDMI_AUD_CHAN_TYPE_7_0,
-	HDMI_AUD_CHAN_TYPE_7_1,
-	HDMI_AUD_CHAN_TYPE_3_0_LRS,
-	HDMI_AUD_CHAN_TYPE_3_1_LRS,
-	HDMI_AUD_CHAN_TYPE_4_0_CLRS,
-	HDMI_AUD_CHAN_TYPE_4_1_CLRS,
-	HDMI_AUD_CHAN_TYPE_6_1_CS,
-	HDMI_AUD_CHAN_TYPE_6_1_CH,
-	HDMI_AUD_CHAN_TYPE_6_1_OH,
-	HDMI_AUD_CHAN_TYPE_6_1_CHR,
-	HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
-	HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
-	HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
-	HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
-	HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
-	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
-	HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
-	HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
-	HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
-	HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
-	HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
-	HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
-	HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
-	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
-	HDMI_AUD_CHAN_TYPE_6_0_CS,
-	HDMI_AUD_CHAN_TYPE_6_0_CH,
-	HDMI_AUD_CHAN_TYPE_6_0_OH,
-	HDMI_AUD_CHAN_TYPE_6_0_CHR,
-	HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
-	HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
-	HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
-	HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
-	HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
-	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
-	HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
-	HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
-	HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
-	HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
-	HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
-	HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
-	HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
-	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
-	HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
-	HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
-};
-
-enum hdmi_aud_channel_swap_type {
-	HDMI_AUD_SWAP_LR,
-	HDMI_AUD_SWAP_LFE_CC,
-	HDMI_AUD_SWAP_LSRS,
-	HDMI_AUD_SWAP_RLS_RRS,
-	HDMI_AUD_SWAP_LR_STATUS,
-};
-
-struct hdmi_audio_param {
-	enum hdmi_audio_coding_type aud_codec;
-	enum hdmi_audio_sample_size aud_sample_size;
-	enum hdmi_aud_input_type aud_input_type;
-	enum hdmi_aud_i2s_fmt aud_i2s_fmt;
-	enum hdmi_aud_mclk aud_mclk;
-	enum hdmi_aud_channel_type aud_input_chan_type;
-	struct hdmi_codec_params codec_params;
-};
-
-struct mtk_hdmi_conf {
-	bool tz_disabled;
-	bool cea_modes_only;
-	unsigned long max_mode_clock;
-};
-
-struct mtk_hdmi {
-	struct drm_bridge bridge;
-	struct drm_bridge *next_bridge;
-	struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
-	struct device *dev;
-	const struct mtk_hdmi_conf *conf;
-	struct phy *phy;
-	struct device *cec_dev;
-	struct i2c_adapter *ddc_adpt;
-	struct clk *clk[MTK_HDMI_CLK_COUNT];
-	struct drm_display_mode mode;
-	bool dvi_mode;
-	u32 min_clock;
-	u32 max_clock;
-	u32 max_hdisplay;
-	u32 max_vdisplay;
-	u32 ibias;
-	u32 ibias_up;
-	struct regmap *sys_regmap;
-	unsigned int sys_offset;
-	struct regmap *regs;
-	enum hdmi_colorspace csp;
-	struct hdmi_audio_param aud_param;
-	bool audio_enable;
-	bool powered;
-	bool enabled;
-	hdmi_codec_plugged_cb plugged_cb;
-	struct device *codec_dev;
-	struct mutex update_plugged_status_lock;
+const char * const mtk_hdmi_clk_names_v1[MTK_HDMI_CLK_COUNT] = {
+	[MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
+	[MTK_HDMI_CLK_HDMI_PLL] = "pll",
+	[MTK_HDMI_CLK_AUD_BCLK] = "bclk",
+	[MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
 };
 
-static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
-{
-	return container_of(b, struct mtk_hdmi, bridge);
-}
-
 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
 {
 	regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
@@ -606,81 +471,6 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
 	regmap_write(hdmi->regs, GRL_CFG5, val);
 }
 
-struct hdmi_acr_n {
-	unsigned int clock;
-	unsigned int n[3];
-};
-
-/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
-static const struct hdmi_acr_n hdmi_rec_n_table[] = {
-	/* Clock, N: 32kHz 44.1kHz 48kHz */
-	{  25175, {  4576,  7007,  6864 } },
-	{  74176, { 11648, 17836, 11648 } },
-	{ 148352, { 11648,  8918,  5824 } },
-	{ 296703, {  5824,  4459,  5824 } },
-	{ 297000, {  3072,  4704,  5120 } },
-	{      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
-};
-
-/**
- * hdmi_recommended_n() - Return N value recommended by HDMI specification
- * @freq: audio sample rate in Hz
- * @clock: rounded TMDS clock in kHz
- */
-static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
-{
-	const struct hdmi_acr_n *recommended;
-	unsigned int i;
-
-	for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
-		if (clock == hdmi_rec_n_table[i].clock)
-			break;
-	}
-	recommended = hdmi_rec_n_table + i;
-
-	switch (freq) {
-	case 32000:
-		return recommended->n[0];
-	case 44100:
-		return recommended->n[1];
-	case 48000:
-		return recommended->n[2];
-	case 88200:
-		return recommended->n[1] * 2;
-	case 96000:
-		return recommended->n[2] * 2;
-	case 176400:
-		return recommended->n[1] * 4;
-	case 192000:
-		return recommended->n[2] * 4;
-	default:
-		return (128 * freq) / 1000;
-	}
-}
-
-static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
-{
-	switch (clock) {
-	case 25175:
-		return 25174825;	/* 25.2/1.001 MHz */
-	case 74176:
-		return 74175824;	/* 74.25/1.001 MHz */
-	case 148352:
-		return 148351648;	/* 148.5/1.001 MHz */
-	case 296703:
-		return 296703297;	/* 297/1.001 MHz */
-	default:
-		return clock * 1000;
-	}
-}
-
-static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
-				      unsigned int tmds_clock, unsigned int n)
-{
-	return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
-				     128 * audio_sample_rate);
-}
-
 static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
 				    unsigned int cts)
 {
@@ -710,9 +500,13 @@ static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
 				     unsigned int clock)
 {
 	unsigned int n, cts;
+	int ret;
 
-	n = hdmi_recommended_n(sample_rate, clock);
-	cts = hdmi_expected_cts(sample_rate, clock, n);
+	ret = mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
+	if (ret) {
+		dev_err(hdmi->dev, "Invalid sample rate: %u\n", sample_rate);
+		return;
+	}
 
 	dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
 		__func__, sample_rate, clock, n, cts);
@@ -829,7 +623,6 @@ static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
 	mtk_hdmi_hw_msic_setting(hdmi, mode);
 }
 
-
 static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
 {
 	enum hdmi_aud_channel_type chan_type;
@@ -920,53 +713,46 @@ static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
 	return 0;
 }
 
-static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
+static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, size_t bufsz,
 					struct drm_display_mode *mode)
 {
 	struct hdmi_avi_infoframe frame;
-	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 	ssize_t err;
 
-	err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
-						       hdmi->curr_conn, mode);
+	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, hdmi->curr_conn, mode);
 	if (err < 0) {
 		dev_err(hdmi->dev,
 			"Failed to get AVI infoframe from mode: %zd\n", err);
 		return err;
 	}
 
-	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
+	err = hdmi_avi_infoframe_pack(&frame, buffer, bufsz);
 	if (err < 0) {
 		dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
 		return err;
 	}
 
-	mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 	return 0;
 }
 
-static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
-					const char *vendor,
-					const char *product)
+static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, size_t bufsz,
+					const char *vendor, const char *product)
 {
 	struct hdmi_spd_infoframe frame;
-	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
 	ssize_t err;
 
 	err = hdmi_spd_infoframe_init(&frame, vendor, product);
 	if (err < 0) {
-		dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
-			err);
+		dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", err);
 		return err;
 	}
 
-	err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
+	err = hdmi_spd_infoframe_pack(&frame, buffer, bufsz);
 	if (err < 0) {
 		dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
 		return err;
 	}
 
-	mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
 	return 0;
 }
 
@@ -1026,19 +812,12 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
 	return 0;
 }
 
-static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
+static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, u8 *buffer_spd, size_t bufsz_spd,
+				    u8 *buffer_avi, size_t bufsz_avi,
+				    struct drm_display_mode *mode)
 {
-	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
-
-	hdmi->csp = HDMI_COLORSPACE_RGB;
-	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
-	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
-	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
-	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
-	aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
-
-	return 0;
+	mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, bufsz_avi, mode);
+	mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd, "mediatek", "On-chip HDMI");
 }
 
 static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
@@ -1053,20 +832,6 @@ static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
 	hdmi->audio_enable = false;
 }
 
-static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
-				    struct hdmi_audio_param *param)
-{
-	if (!hdmi->audio_enable) {
-		dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
-		return -EINVAL;
-	}
-	dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
-		param->aud_codec, param->aud_input_type,
-		param->aud_input_chan_type, param->codec_params.sample_rate);
-	memcpy(&hdmi->aud_param, param, sizeof(*param));
-	return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
-}
-
 static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
 					    struct drm_display_mode *mode)
 {
@@ -1095,27 +860,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
 	return 0;
 }
 
-static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
-	[MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
-	[MTK_HDMI_CLK_HDMI_PLL] = "pll",
-	[MTK_HDMI_CLK_AUD_BCLK] = "bclk",
-	[MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
-};
-
-static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
-				struct device_node *np)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
-		hdmi->clk[i] = of_clk_get_by_name(np,
-						  mtk_hdmi_clk_names[i]);
-		if (IS_ERR(hdmi->clk[i]))
-			return PTR_ERR(hdmi->clk[i]);
-	}
-	return 0;
-}
-
 static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
 {
 	int ret;
@@ -1125,13 +869,12 @@ static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
 		return ret;
 
 	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
-	if (ret)
-		goto err;
+	if (ret) {
+		clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
+		return ret;
+	}
 
 	return 0;
-err:
-	clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
-	return ret;
 }
 
 static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
@@ -1143,10 +886,11 @@ static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
 static enum drm_connector_status
 mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
 {
-	bool connected;
+	bool connected = true;
 
 	mutex_lock(&hdmi->update_plugged_status_lock);
-	connected = mtk_cec_hpd_high(hdmi->cec_dev);
+	if (hdmi->cec_dev)
+		connected = mtk_cec_hpd_high(hdmi->cec_dev);
 	if (hdmi->plugged_cb && hdmi->codec_dev)
 		hdmi->plugged_cb(hdmi->codec_dev, connected);
 	mutex_unlock(&hdmi->update_plugged_status_lock);
@@ -1254,18 +998,12 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
 			return ret;
 	}
 
-	mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
+	if (hdmi->cec_dev)
+		mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
 
 	return 0;
 }
 
-static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
-				       const struct drm_display_mode *mode,
-				       struct drm_display_mode *adjusted_mode)
-{
-	return true;
-}
-
 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
 					   struct drm_bridge_state *old_bridge_state)
 {
@@ -1297,28 +1035,6 @@ static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
 	hdmi->powered = false;
 }
 
-static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
-				const struct drm_display_mode *mode,
-				const struct drm_display_mode *adjusted_mode)
-{
-	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
-
-	dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
-		adjusted_mode->name, adjusted_mode->hdisplay);
-	dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
-		adjusted_mode->hsync_start, adjusted_mode->hsync_end,
-		adjusted_mode->htotal);
-	dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
-		adjusted_mode->hskew, adjusted_mode->vdisplay);
-	dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
-		adjusted_mode->vsync_start, adjusted_mode->vsync_end,
-		adjusted_mode->vtotal);
-	dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
-		adjusted_mode->vscan, adjusted_mode->flags);
-
-	drm_mode_copy(&hdmi->mode, adjusted_mode);
-}
-
 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
 					      struct drm_bridge_state *old_state)
 {
@@ -1330,21 +1046,13 @@ static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
 	hdmi->powered = true;
 }
 
-static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
-				    struct drm_display_mode *mode)
-{
-	mtk_hdmi_setup_audio_infoframe(hdmi);
-	mtk_hdmi_setup_avi_infoframe(hdmi, mode);
-	mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
-	if (mode->flags & DRM_MODE_FLAG_3D_MASK)
-		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
-}
-
 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
 					  struct drm_bridge_state *old_state)
 {
 	struct drm_atomic_state *state = old_state->base.state;
 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+	u8 buffer_spd[HDMI_INFOFRAME_SIZE(SPD)];
+	u8 buffer_avi[HDMI_INFOFRAME_SIZE(AVI)];
 
 	/* Retrieve the connector through the atomic state. */
 	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
@@ -1354,12 +1062,16 @@ static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
 	phy_power_on(hdmi->phy);
-	mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
+	mtk_hdmi_setup_audio_infoframe(hdmi);
+	mtk_hdmi_send_infoframe(hdmi, buffer_spd, sizeof(buffer_spd),
+				buffer_avi, sizeof(buffer_avi), &hdmi->mode);
+	if (hdmi->mode.flags & DRM_MODE_FLAG_3D_MASK)
+		mtk_hdmi_setup_vendor_specific_infoframe(hdmi, &hdmi->mode);
 
 	hdmi->enabled = true;
 }
 
-static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
+const struct drm_bridge_funcs mtk_mt8183_hdmi_bridge_funcs = {
 	.mode_valid = mtk_hdmi_bridge_mode_valid,
 	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
@@ -1375,180 +1087,19 @@ static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
 	.edid_read = mtk_hdmi_bridge_edid_read,
 };
 
-static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
-				   struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-	struct device_node *np = dev->of_node;
-	struct device_node *cec_np, *remote, *i2c_np;
-	struct platform_device *cec_pdev;
-	struct regmap *regmap;
-	int ret;
-
-	ret = mtk_hdmi_get_all_clk(hdmi, np);
-	if (ret) {
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "Failed to get clocks: %d\n", ret);
-
-		return ret;
-	}
-
-	/* The CEC module handles HDMI hotplug detection */
-	cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
-	if (!cec_np) {
-		dev_err(dev, "Failed to find CEC node\n");
-		return -EINVAL;
-	}
-
-	cec_pdev = of_find_device_by_node(cec_np);
-	if (!cec_pdev) {
-		dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
-			cec_np);
-		of_node_put(cec_np);
-		return -EPROBE_DEFER;
-	}
-	of_node_put(cec_np);
-	hdmi->cec_dev = &cec_pdev->dev;
-
-	/*
-	 * The mediatek,syscon-hdmi property contains a phandle link to the
-	 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
-	 * registers it contains.
-	 */
-	regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
-	ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
-					 &hdmi->sys_offset);
-	if (IS_ERR(regmap))
-		ret = PTR_ERR(regmap);
-	if (ret) {
-		dev_err(dev,
-			"Failed to get system configuration registers: %d\n",
-			ret);
-		goto put_device;
-	}
-	hdmi->sys_regmap = regmap;
-
-	hdmi->regs = device_node_to_regmap(dev->of_node);
-	if (IS_ERR(hdmi->regs)) {
-		ret = PTR_ERR(hdmi->regs);
-		goto put_device;
-	}
-
-	remote = of_graph_get_remote_node(np, 1, 0);
-	if (!remote) {
-		ret = -EINVAL;
-		goto put_device;
-	}
-
-	if (!of_device_is_compatible(remote, "hdmi-connector")) {
-		hdmi->next_bridge = of_drm_find_bridge(remote);
-		if (!hdmi->next_bridge) {
-			dev_err(dev, "Waiting for external bridge\n");
-			of_node_put(remote);
-			ret = -EPROBE_DEFER;
-			goto put_device;
-		}
-	}
-
-	i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
-	if (!i2c_np) {
-		dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
-			remote);
-		of_node_put(remote);
-		ret = -EINVAL;
-		goto put_device;
-	}
-	of_node_put(remote);
-
-	hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
-	of_node_put(i2c_np);
-	if (!hdmi->ddc_adpt) {
-		dev_err(dev, "Failed to get ddc i2c adapter by node\n");
-		ret = -EINVAL;
-		goto put_device;
-	}
-
-	return 0;
-put_device:
-	put_device(hdmi->cec_dev);
-	return ret;
-}
-
 /*
  * HDMI audio codec callbacks
  */
-
 static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
 				    struct hdmi_codec_daifmt *daifmt,
 				    struct hdmi_codec_params *params)
 {
 	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-	struct hdmi_audio_param hdmi_params;
-	unsigned int chan = params->cea.channels;
-
-	dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
-		params->sample_rate, params->sample_width, chan);
-
-	if (!hdmi->bridge.encoder)
-		return -ENODEV;
-
-	switch (chan) {
-	case 2:
-		hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
-		break;
-	case 4:
-		hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
-		break;
-	case 6:
-		hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
-		break;
-	case 8:
-		hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
-		break;
-	default:
-		dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
-		return -EINVAL;
-	}
-
-	switch (params->sample_rate) {
-	case 32000:
-	case 44100:
-	case 48000:
-	case 88200:
-	case 96000:
-	case 176400:
-	case 192000:
-		break;
-	default:
-		dev_err(hdmi->dev, "rate[%d] not supported!\n",
-			params->sample_rate);
-		return -EINVAL;
-	}
 
-	switch (daifmt->fmt) {
-	case HDMI_I2S:
-		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-		hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
-		hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
-		hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
-		hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
-		break;
-	case HDMI_SPDIF:
-		hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
-		hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
-		hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
-		break;
-	default:
-		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
-			daifmt->fmt);
-		return -EINVAL;
+	if (hdmi->audio_enable) {
+		mtk_hdmi_audio_params(hdmi, daifmt, params);
+		mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
 	}
-
-	memcpy(&hdmi_params.codec_params, params,
-	       sizeof(hdmi_params.codec_params));
-
-	mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
-
 	return 0;
 }
 
@@ -1582,28 +1133,13 @@ mtk_hdmi_audio_mute(struct device *dev, void *data,
 	return 0;
 }
 
-static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
-{
-	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-
-	if (hdmi->enabled)
-		memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
-	else
-		memset(buf, 0, len);
-	return 0;
-}
-
 static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
 					  hdmi_codec_plugged_cb fn,
 					  struct device *codec_dev)
 {
 	struct mtk_hdmi *hdmi = data;
 
-	mutex_lock(&hdmi->update_plugged_status_lock);
-	hdmi->plugged_cb = fn;
-	hdmi->codec_dev = codec_dev;
-	mutex_unlock(&hdmi->update_plugged_status_lock);
-
+	mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
 	mtk_hdmi_update_plugged_status(hdmi);
 
 	return 0;
@@ -1619,165 +1155,85 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
 	.no_capture_mute = 1,
 };
 
-static int mtk_hdmi_register_audio_driver(struct device *dev)
+static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
 {
 	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-	struct hdmi_codec_pdata codec_data = {
-		.ops = &mtk_hdmi_audio_codec_ops,
-		.max_i2s_channels = 2,
-		.i2s = 1,
-		.data = hdmi,
-	};
-	struct platform_device *pdev;
-
-	pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
-					     PLATFORM_DEVID_AUTO, &codec_data,
-					     sizeof(codec_data));
-	if (IS_ERR(pdev))
-		return PTR_ERR(pdev);
-
-	DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
+
+	mtk_hdmi_clk_disable_audio(hdmi);
+
 	return 0;
 }
 
-static int mtk_hdmi_probe(struct platform_device *pdev)
+static __maybe_unused int mtk_hdmi_resume(struct device *dev)
 {
-	struct mtk_hdmi *hdmi;
-	struct device *dev = &pdev->dev;
-	int ret;
-
-	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
-	if (!hdmi)
-		return -ENOMEM;
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
 
-	hdmi->dev = dev;
-	hdmi->conf = of_device_get_match_data(dev);
+	return mtk_hdmi_clk_enable_audio(hdmi);
+}
 
-	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
-	if (ret)
-		return ret;
+static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
 
-	hdmi->phy = devm_phy_get(dev, "hdmi");
-	if (IS_ERR(hdmi->phy))
-		return dev_err_probe(dev, PTR_ERR(hdmi->phy),
-				     "Failed to get HDMI PHY\n");
+static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf = {
+	.bridge_funcs = &mtk_mt8183_hdmi_bridge_funcs,
+	.codec_ops = &mtk_hdmi_audio_codec_ops,
+	.mtk_hdmi_clock_names = mtk_hdmi_clk_names_v1,
+	.num_clocks = ARRAY_SIZE(mtk_hdmi_clk_names_v1)
+};
 
-	mutex_init(&hdmi->update_plugged_status_lock);
-	platform_set_drvdata(pdev, hdmi);
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
+	.tz_disabled = true,
+	.ver_conf = &mtk_hdmi_v1_ver_conf
+};
 
-	ret = mtk_hdmi_output_init(hdmi);
-	if (ret)
-		return dev_err_probe(dev, ret,
-				     "Failed to initialize hdmi output\n");
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
+	.max_mode_clock = 148500,
+	.cea_modes_only = true,
+	.ver_conf = &mtk_hdmi_v1_ver_conf
+};
 
-	ret = mtk_hdmi_register_audio_driver(dev);
-	if (ret)
-		return dev_err_probe(dev, ret,
-				     "Failed to register audio driver\n");
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = {
+	.ver_conf = &mtk_hdmi_v1_ver_conf
+};
 
-	hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
-	hdmi->bridge.of_node = pdev->dev.of_node;
-	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
-			 | DRM_BRIDGE_OP_HPD;
-	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
-	drm_bridge_add(&hdmi->bridge);
+static int mtk_hdmi_probe(struct platform_device *pdev)
+{
+	struct mtk_hdmi *hdmi;
 
-	ret = mtk_hdmi_clk_enable_audio(hdmi);
-	if (ret) {
-		drm_bridge_remove(&hdmi->bridge);
-		return dev_err_probe(dev, ret,
-				     "Failed to enable audio clocks\n");
-	}
+	hdmi = mtk_hdmi_common_probe(pdev);
+	if (IS_ERR(hdmi))
+		return PTR_ERR(hdmi);
 
-	return 0;
+	return mtk_hdmi_clk_enable_audio(hdmi);
 }
 
 static void mtk_hdmi_remove(struct platform_device *pdev)
 {
 	struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
 
-	drm_bridge_remove(&hdmi->bridge);
-	mtk_hdmi_clk_disable_audio(hdmi);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int mtk_hdmi_suspend(struct device *dev)
-{
-	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-
 	mtk_hdmi_clk_disable_audio(hdmi);
-
-	return 0;
-}
-
-static int mtk_hdmi_resume(struct device *dev)
-{
-	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
-	int ret = 0;
-
-	ret = mtk_hdmi_clk_enable_audio(hdmi);
-	if (ret) {
-		dev_err(dev, "hdmi resume failed!\n");
-		return ret;
-	}
-
-	return 0;
+	i2c_put_adapter(hdmi->ddc_adpt);
 }
-#endif
-static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
-			 mtk_hdmi_suspend, mtk_hdmi_resume);
-
-static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
-	.tz_disabled = true,
-};
-
-static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
-	.max_mode_clock = 148500,
-	.cea_modes_only = true,
-};
 
-static const struct of_device_id mtk_hdmi_of_ids[] = {
-	{ .compatible = "mediatek,mt2701-hdmi",
-	  .data = &mtk_hdmi_conf_mt2701,
-	},
-	{ .compatible = "mediatek,mt8167-hdmi",
-	  .data = &mtk_hdmi_conf_mt8167,
-	},
-	{ .compatible = "mediatek,mt8173-hdmi",
-	},
-	{}
+static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
+	{ .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
+	{ .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
+	{ .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 },
+	{ /* sentinel */ }
 };
-MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
+MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
 
 static struct platform_driver mtk_hdmi_driver = {
 	.probe = mtk_hdmi_probe,
-	.remove_new = mtk_hdmi_remove,
+	.remove = mtk_hdmi_remove,
 	.driver = {
 		.name = "mediatek-drm-hdmi",
-		.of_match_table = mtk_hdmi_of_ids,
+		.of_match_table = mtk_drm_hdmi_of_ids,
 		.pm = &mtk_hdmi_pm_ops,
 	},
 };
-
-static struct platform_driver * const mtk_hdmi_drivers[] = {
-	&mtk_hdmi_driver,
-};
-
-static int __init mtk_hdmitx_init(void)
-{
-	return platform_register_drivers(mtk_hdmi_drivers,
-					 ARRAY_SIZE(mtk_hdmi_drivers));
-}
-
-static void __exit mtk_hdmitx_exit(void)
-{
-	platform_unregister_drivers(mtk_hdmi_drivers,
-				    ARRAY_SIZE(mtk_hdmi_drivers));
-}
-
-module_init(mtk_hdmitx_init);
-module_exit(mtk_hdmitx_exit);
+module_platform_driver(mtk_hdmi_driver);
 
 MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
+MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
 MODULE_DESCRIPTION("MediaTek HDMI Driver");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
new file mode 100644
index 000000000000..1b23ab6969ec
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Copyright (c) 2022 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <drm/drm_modes.h>
+#include <linux/device.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/math.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
+#include <sound/hdmi-codec.h>
+
+#include "mtk_hdmi_common.h"
+
+struct hdmi_acr_n {
+	unsigned int clock;
+	unsigned int n[3];
+};
+
+/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
+static const struct hdmi_acr_n hdmi_rec_n_table[] = {
+	/* Clock, N: 32kHz 44.1kHz 48kHz */
+	{ 25175,  {  4576,  7007,  6864 } },
+	{ 74176,  { 11648, 17836, 11648 } },
+	{ 148352, { 11648,  8918,  5824 } },
+	{ 296703, {  5824,  4459,  5824 } },
+	{ 297000, {  3072,  4704,  5120 } },
+	{ 0,      {  4096,  6272,  6144 } }, /* all other TMDS clocks */
+};
+
+/**
+ * hdmi_recommended_n() - Return N value recommended by HDMI specification
+ * @freq: audio sample rate in Hz
+ * @clock: rounded TMDS clock in kHz
+ */
+static int hdmi_recommended_n(unsigned int freq, unsigned int clock)
+{
+	const struct hdmi_acr_n *recommended;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
+		if (clock == hdmi_rec_n_table[i].clock)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(hdmi_rec_n_table))
+		return -EINVAL;
+
+	recommended = hdmi_rec_n_table + i;
+
+	switch (freq) {
+	case 32000:
+		return recommended->n[0];
+	case 44100:
+		return recommended->n[1];
+	case 48000:
+		return recommended->n[2];
+	case 88200:
+		return recommended->n[1] * 2;
+	case 96000:
+		return recommended->n[2] * 2;
+	case 176400:
+		return recommended->n[1] * 4;
+	case 192000:
+		return recommended->n[2] * 4;
+	default:
+		return (128 * freq) / 1000;
+	}
+}
+
+static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
+{
+	switch (clock) {
+	case 25175:
+		return 25174825; /* 25.2/1.001 MHz */
+	case 74176:
+		return 74175824; /* 74.25/1.001 MHz */
+	case 148352:
+		return 148351648; /* 148.5/1.001 MHz */
+	case 296703:
+		return 296703297; /* 297/1.001 MHz */
+	default:
+		return clock * 1000;
+	}
+}
+
+static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
+				      unsigned int tmds_clock, unsigned int n)
+{
+	return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
+				     128 * audio_sample_rate);
+}
+
+int mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
+		      unsigned int *n, unsigned int *cts)
+{
+	int rec_n = hdmi_recommended_n(sample_rate, clock);
+
+	if (rec_n < 0)
+		return rec_n;
+
+	*cts = hdmi_expected_cts(sample_rate, clock, rec_n);
+	*n = rec_n;
+
+	return 0;
+}
+
+int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
+			  struct hdmi_codec_daifmt *daifmt,
+			  struct hdmi_codec_params *params)
+{
+	struct hdmi_audio_param aud_params = { 0 };
+	unsigned int chan = params->cea.channels;
+
+	dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
+		params->sample_rate, params->sample_width, chan);
+
+	if (!hdmi->bridge.encoder)
+		return -ENODEV;
+
+	switch (chan) {
+	case 2:
+		aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+		break;
+	case 4:
+		aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
+		break;
+	case 6:
+		aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
+		break;
+	case 8:
+		aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
+		break;
+	default:
+		dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
+		return -EINVAL;
+	}
+
+	switch (params->sample_rate) {
+	case 32000:
+	case 44100:
+	case 48000:
+	case 88200:
+	case 96000:
+	case 176400:
+	case 192000:
+		break;
+	default:
+		dev_err(hdmi->dev, "rate[%d] not supported!\n",
+			params->sample_rate);
+		return -EINVAL;
+	}
+
+	switch (daifmt->fmt) {
+	case HDMI_I2S:
+		aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+		aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
+		aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+		aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
+		break;
+	case HDMI_SPDIF:
+		aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+		aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+		aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
+		break;
+	default:
+		dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
+			daifmt->fmt);
+		return -EINVAL;
+	}
+	memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
+	memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
+
+	dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
+		aud_params.aud_codec, aud_params.aud_input_type,
+		aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
+
+	return 0;
+}
+
+int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	if (hdmi->enabled)
+		memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
+	else
+		memset(buf, 0, len);
+
+	return 0;
+}
+
+void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
+				   struct device *codec_dev)
+{
+	mutex_lock(&hdmi->update_plugged_status_lock);
+	hdmi->plugged_cb = fn;
+	hdmi->codec_dev = codec_dev;
+	mutex_unlock(&hdmi->update_plugged_status_lock);
+}
+
+static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
+				const char * const *mtk_hdmi_clk_names, size_t num_clocks)
+{
+	int i;
+
+	for (i = 0; i < num_clocks; i++) {
+		hdmi->clk[i] = of_clk_get_by_name(np, mtk_hdmi_clk_names[i]);
+
+		if (IS_ERR(hdmi->clk[i]))
+			return PTR_ERR(hdmi->clk[i]);
+	}
+
+	return 0;
+}
+
+bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
+				const struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode)
+{
+	return true;
+}
+
+void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
+			      const struct drm_display_mode *mode,
+			      const struct drm_display_mode *adjusted_mode)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	drm_mode_copy(&hdmi->mode, adjusted_mode);
+}
+
+static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
+{
+	struct platform_device *cec_pdev;
+	struct device_node *cec_np;
+	int ret;
+
+	/* The CEC module handles HDMI hotplug detection */
+	cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
+	if (!cec_np)
+		return dev_err_probe(dev, -ENOTSUPP, "Failed to find CEC node\n");
+
+	cec_pdev = of_find_device_by_node(cec_np);
+	if (!cec_pdev) {
+		dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np);
+		of_node_put(cec_np);
+		return -EPROBE_DEFER;
+	}
+	of_node_put(cec_np);
+
+	/*
+	 * The mediatek,syscon-hdmi property contains a phandle link to the
+	 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
+	 * registers it contains.
+	 */
+	hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
+	if (IS_ERR(hdmi->sys_regmap))
+		return PTR_ERR(hdmi->sys_regmap);
+
+	ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
+	if (ret)
+		return dev_err_probe(dev, ret,
+				     "Failed to get system configuration registers\n");
+
+	hdmi->cec_dev = &cec_pdev->dev;
+	return 0;
+}
+
+static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
+				   const char * const *clk_names, size_t num_clocks)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	struct device_node *remote, *i2c_np;
+	int ret;
+
+	ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to get clocks\n");
+
+	hdmi->irq = platform_get_irq(pdev, 0);
+	if (!hdmi->irq)
+		return hdmi->irq;
+
+	hdmi->regs = device_node_to_regmap(dev->of_node);
+	if (IS_ERR(hdmi->regs))
+		return PTR_ERR(hdmi->regs);
+
+	remote = of_graph_get_remote_node(np, 1, 0);
+	if (!remote)
+		return dev_err_probe(dev, -EINVAL, "Cannot find HDMI input port\n");
+
+	if (!of_device_is_compatible(remote, "hdmi-connector")) {
+		hdmi->next_bridge = of_drm_find_bridge(remote);
+		if (!hdmi->next_bridge) {
+			dev_err(dev, "Waiting for external bridge\n");
+			of_node_put(remote);
+			return -EPROBE_DEFER;
+		}
+	}
+
+	i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
+	if (!i2c_np) {
+		of_node_put(pdev->dev.of_node);
+		return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
+	}
+
+	hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
+	of_node_put(i2c_np);
+	if (!hdmi->ddc_adpt) {
+		dev_err(dev, "Failed to get ddc i2c adapter by node");
+		return -EPROBE_DEFER;
+	}
+
+	ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
+	if (ret == -ENOTSUPP)
+		dev_info(dev, "CEC support unavailable: node not found\n");
+	else if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void mtk_hdmi_unregister_audio_driver(void *data)
+{
+	platform_device_unregister(data);
+}
+
+static int mtk_hdmi_register_audio_driver(struct device *dev)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
+	struct hdmi_codec_pdata codec_data = {
+		.i2s = 1,
+		.max_i2s_channels = 2,
+		.data = hdmi,
+		.ops = hdmi->conf->ver_conf->codec_ops
+	};
+	int ret;
+
+	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
+	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
+	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
+	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
+	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
+	aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
+
+	hdmi->audio_pdev = platform_device_register_data(dev,
+							 HDMI_CODEC_DRV_NAME,
+							 PLATFORM_DEVID_AUTO,
+							 &codec_data,
+							 sizeof(codec_data));
+	if (IS_ERR(hdmi->audio_pdev))
+		return PTR_ERR(hdmi->audio_pdev);
+
+	ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
+				       hdmi->audio_pdev);
+	if (ret) {
+		platform_device_unregister(hdmi->audio_pdev);
+		return ret;
+	}
+
+	return 0;
+}
+
+struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
+{
+	const struct mtk_hdmi_ver_conf *ver_conf;
+	struct device *dev = &pdev->dev;
+	struct mtk_hdmi *hdmi;
+	int ret;
+
+	hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+	if (!hdmi)
+		return ERR_PTR(-ENOMEM);
+
+	hdmi->dev = dev;
+	hdmi->conf = of_device_get_match_data(dev);
+	ver_conf = hdmi->conf->ver_conf;
+
+	hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
+	if (!hdmi->clk)
+		return ERR_PTR(-ENOMEM);
+
+	hdmi->phy = devm_phy_get(dev, "hdmi");
+	if (IS_ERR(hdmi->phy))
+		return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
+
+	ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
+				      ver_conf->num_clocks);
+	if (ret)
+		return ERR_PTR(ret);
+
+	platform_set_drvdata(pdev, hdmi);
+
+	ret = mtk_hdmi_register_audio_driver(dev);
+	if (ret)
+		return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");
+
+	hdmi->bridge.funcs = ver_conf->bridge_funcs;
+	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
+	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
+	hdmi->bridge.of_node = pdev->dev.of_node;
+
+	ret = devm_drm_bridge_add(dev, &hdmi->bridge);
+	if (ret)
+		return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
+
+	return hdmi;
+}
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
+MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMI Common Library");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
new file mode 100644
index 000000000000..15121e8548f3
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2022 BayLibre, SAS
+ */
+
+#ifndef _MTK_HDMI_COMMON_H
+#define _MTK_HDMI_COMMON_H
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/hdmi.h>
+#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mutex.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#include <sound/hdmi-codec.h>
+
+enum hdmi_aud_input_type {
+	HDMI_AUD_INPUT_I2S = 0,
+	HDMI_AUD_INPUT_SPDIF,
+};
+
+enum hdmi_aud_i2s_fmt {
+	HDMI_I2S_MODE_RJT_24BIT = 0,
+	HDMI_I2S_MODE_RJT_16BIT,
+	HDMI_I2S_MODE_LJT_24BIT,
+	HDMI_I2S_MODE_LJT_16BIT,
+	HDMI_I2S_MODE_I2S_24BIT,
+	HDMI_I2S_MODE_I2S_16BIT
+};
+
+enum hdmi_aud_mclk {
+	HDMI_AUD_MCLK_128FS,
+	HDMI_AUD_MCLK_192FS,
+	HDMI_AUD_MCLK_256FS,
+	HDMI_AUD_MCLK_384FS,
+	HDMI_AUD_MCLK_512FS,
+	HDMI_AUD_MCLK_768FS,
+	HDMI_AUD_MCLK_1152FS,
+};
+
+enum hdmi_aud_channel_type {
+	HDMI_AUD_CHAN_TYPE_1_0 = 0,
+	HDMI_AUD_CHAN_TYPE_1_1,
+	HDMI_AUD_CHAN_TYPE_2_0,
+	HDMI_AUD_CHAN_TYPE_2_1,
+	HDMI_AUD_CHAN_TYPE_3_0,
+	HDMI_AUD_CHAN_TYPE_3_1,
+	HDMI_AUD_CHAN_TYPE_4_0,
+	HDMI_AUD_CHAN_TYPE_4_1,
+	HDMI_AUD_CHAN_TYPE_5_0,
+	HDMI_AUD_CHAN_TYPE_5_1,
+	HDMI_AUD_CHAN_TYPE_6_0,
+	HDMI_AUD_CHAN_TYPE_6_1,
+	HDMI_AUD_CHAN_TYPE_7_0,
+	HDMI_AUD_CHAN_TYPE_7_1,
+	HDMI_AUD_CHAN_TYPE_3_0_LRS,
+	HDMI_AUD_CHAN_TYPE_3_1_LRS,
+	HDMI_AUD_CHAN_TYPE_4_0_CLRS,
+	HDMI_AUD_CHAN_TYPE_4_1_CLRS,
+	HDMI_AUD_CHAN_TYPE_6_1_CS,
+	HDMI_AUD_CHAN_TYPE_6_1_CH,
+	HDMI_AUD_CHAN_TYPE_6_1_OH,
+	HDMI_AUD_CHAN_TYPE_6_1_CHR,
+	HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
+	HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
+	HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
+	HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
+	HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
+	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
+	HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
+	HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
+	HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
+	HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
+	HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
+	HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
+	HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
+	HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
+	HDMI_AUD_CHAN_TYPE_6_0_CS,
+	HDMI_AUD_CHAN_TYPE_6_0_CH,
+	HDMI_AUD_CHAN_TYPE_6_0_OH,
+	HDMI_AUD_CHAN_TYPE_6_0_CHR,
+	HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
+	HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
+	HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
+	HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
+	HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
+	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
+	HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
+	HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
+	HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
+	HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
+	HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
+	HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
+	HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
+	HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
+	HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
+	HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
+};
+
+enum hdmi_aud_channel_swap_type {
+	HDMI_AUD_SWAP_LR,
+	HDMI_AUD_SWAP_LFE_CC,
+	HDMI_AUD_SWAP_LSRS,
+	HDMI_AUD_SWAP_RLS_RRS,
+	HDMI_AUD_SWAP_LR_STATUS,
+};
+
+enum hdmi_hpd_state {
+	HDMI_PLUG_OUT = 0,
+	HDMI_PLUG_IN_AND_SINK_POWER_ON,
+	HDMI_PLUG_IN_ONLY,
+};
+
+struct hdmi_audio_param {
+	enum hdmi_audio_coding_type aud_codec;
+	enum hdmi_audio_sample_size aud_sample_size;
+	enum hdmi_aud_input_type aud_input_type;
+	enum hdmi_aud_i2s_fmt aud_i2s_fmt;
+	enum hdmi_aud_mclk aud_mclk;
+	enum hdmi_aud_channel_type aud_input_chan_type;
+	struct hdmi_codec_params codec_params;
+};
+
+struct mtk_hdmi {
+	struct drm_bridge bridge;
+	struct device *dev;
+	const struct mtk_hdmi_conf *conf;
+	struct phy *phy;
+	struct i2c_adapter *ddc_adpt;
+	struct clk **clk;
+	struct drm_display_mode mode;
+	bool dvi_mode;
+	struct regmap *sys_regmap;
+	unsigned int sys_offset;
+	struct regmap *regs;
+
+	bool powered;
+	bool enabled;
+	unsigned int irq;
+	enum hdmi_hpd_state hpd;
+
+	/* Audio */
+	struct platform_device *audio_pdev;
+	struct hdmi_audio_param aud_param;
+	bool audio_enable;
+
+	struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
+	struct mutex update_plugged_status_lock;
+	struct device *cec_dev;
+	struct device *codec_dev;
+	hdmi_codec_plugged_cb plugged_cb;
+	struct drm_bridge *next_bridge;
+};
+
+struct mtk_hdmi_ver_conf {
+	const struct drm_bridge_funcs *bridge_funcs;
+	const struct hdmi_codec_ops *codec_ops;
+	const char * const *mtk_hdmi_clock_names;
+	int num_clocks;
+	bool hdr_support;
+};
+
+struct mtk_hdmi_conf {
+	const struct mtk_hdmi_ver_conf *ver_conf;
+	bool tz_disabled;
+	bool cea_modes_only;
+	unsigned long max_mode_clock;
+};
+
+static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
+{
+	return container_of(b, struct mtk_hdmi, bridge);
+}
+
+int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
+void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
+				   struct device *codec_dev);
+int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
+			  struct hdmi_codec_params *params);
+int mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
+		      unsigned int *n, unsigned int *cts);
+bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
+				const struct drm_display_mode *mode,
+				struct drm_display_mode *adjusted_mode);
+void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
+			      const struct drm_display_mode *mode,
+			      const struct drm_display_mode *adjusted_mode);
+struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
+int mtk_drm_hdmi_probe(struct platform_device *pdev);
+int mtk_drm_hdmi_remove(struct platform_device *pdev);
+
+#endif /* _MTK_HDMI_COMMON_H */
-- 
2.47.0

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[Dmitry Baryshkov]

On Thu, Dec 05, 2024 at 12:45:14PM +0100, AngeloGioacchino Del Regno wrote:
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/Kconfig           |  11 +-
>  drivers/gpu/drm/mediatek/Makefile          |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi.c        | 724 +++------------------
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 425 ++++++++++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 203 ++++++
>  5 files changed, 729 insertions(+), 635 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> 
> @@ -1026,19 +812,12 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
>  	return 0;
>  }
>  
> -static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
> +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, u8 *buffer_spd, size_t bufsz_spd,
> +				    u8 *buffer_avi, size_t bufsz_avi,
> +				    struct drm_display_mode *mode)
>  {
> -	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> -
> -	hdmi->csp = HDMI_COLORSPACE_RGB;
> -	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> -	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> -	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> -	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> -	aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> -
> -	return 0;
> +	mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, bufsz_avi, mode);
> +	mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd, "mediatek", "On-chip HDMI");

Please use the HDMI Connector framework instead of handling everything
on your own.

>  }
>  
>  static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)

-- 
With best wishes
Dmitry

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[AngeloGioacchino Del Regno]

Il 05/12/24 13:29, Dmitry Baryshkov ha scritto:
> On Thu, Dec 05, 2024 at 12:45:14PM +0100, AngeloGioacchino Del Regno wrote:
>> In preparation for adding a new driver for the HDMI TX v2 IP,
>> split out the functions that will be common between the already
>> present mtk_hdmi (v1) driver and the new one.
>>
>> Since the probe flow for both drivers is 90% similar, add a common
>> probe function that will be called from each driver's .probe()
>> callback, avoiding lots of code duplication.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/gpu/drm/mediatek/Kconfig           |  11 +-
>>   drivers/gpu/drm/mediatek/Makefile          |   1 +
>>   drivers/gpu/drm/mediatek/mtk_hdmi.c        | 724 +++------------------
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 425 ++++++++++++
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 203 ++++++
>>   5 files changed, 729 insertions(+), 635 deletions(-)
>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
>>
>> @@ -1026,19 +812,12 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
>>   	return 0;
>>   }
>>   
>> -static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
>> +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, u8 *buffer_spd, size_t bufsz_spd,
>> +				    u8 *buffer_avi, size_t bufsz_avi,
>> +				    struct drm_display_mode *mode)
>>   {
>> -	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
>> -
>> -	hdmi->csp = HDMI_COLORSPACE_RGB;
>> -	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
>> -	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
>> -	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
>> -	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
>> -	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
>> -	aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
>> -
>> -	return 0;
>> +	mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, bufsz_avi, mode);
>> +	mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd, "mediatek", "On-chip HDMI");
> 
> Please use the HDMI Connector framework instead of handling everything
> on your own.
> 

Dmitry, my plan is to get the MediaTek HDMIv2 driver upstreamed *with* using
the HDMI helpers - this commit is only splitting the old HDMI v1 driver in
common parts and v1 handling.

This "handling everything on my own" is something that was already present
into the old v1 driver, I am *not adding* this code, but *moving it around*.

I cannot migrate the v1 driver to the HDMI helpers right now because in this
moment I have no way to test that and I don't want to break any functionality.

If you check patch 15, you'll see that I am indeed using all of the helper
goodies - but for now only on the new driver, and not on the old one.

I do plan to migrate the v1 driver to the new helpers as well, but I would
(please) really prefer to do that only after the v2 driver is upstreamed.

Is that okay for you?

Cheers,
Angelo

>>   }
>>   
>>   static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
> 

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[Dmitry Baryshkov]

On Thu, Dec 05, 2024 at 01:36:18PM +0100, AngeloGioacchino Del Regno wrote:
> Il 05/12/24 13:29, Dmitry Baryshkov ha scritto:
> > On Thu, Dec 05, 2024 at 12:45:14PM +0100, AngeloGioacchino Del Regno wrote:
> > > In preparation for adding a new driver for the HDMI TX v2 IP,
> > > split out the functions that will be common between the already
> > > present mtk_hdmi (v1) driver and the new one.
> > > 
> > > Since the probe flow for both drivers is 90% similar, add a common
> > > probe function that will be called from each driver's .probe()
> > > callback, avoiding lots of code duplication.
> > > 
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > ---
> > >   drivers/gpu/drm/mediatek/Kconfig           |  11 +-
> > >   drivers/gpu/drm/mediatek/Makefile          |   1 +
> > >   drivers/gpu/drm/mediatek/mtk_hdmi.c        | 724 +++------------------
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 425 ++++++++++++
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 203 ++++++
> > >   5 files changed, 729 insertions(+), 635 deletions(-)
> > >   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> > >   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> > > 
> > > @@ -1026,19 +812,12 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
> > >   	return 0;
> > >   }
> > > -static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
> > > +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, u8 *buffer_spd, size_t bufsz_spd,
> > > +				    u8 *buffer_avi, size_t bufsz_avi,
> > > +				    struct drm_display_mode *mode)
> > >   {
> > > -	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> > > -
> > > -	hdmi->csp = HDMI_COLORSPACE_RGB;
> > > -	aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> > > -	aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> > > -	aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> > > -	aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> > > -	aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> > > -	aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> > > -
> > > -	return 0;
> > > +	mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, bufsz_avi, mode);
> > > +	mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd, "mediatek", "On-chip HDMI");
> > 
> > Please use the HDMI Connector framework instead of handling everything
> > on your own.
> > 
> 
> Dmitry, my plan is to get the MediaTek HDMIv2 driver upstreamed *with* using
> the HDMI helpers - this commit is only splitting the old HDMI v1 driver in
> common parts and v1 handling.
> 
> This "handling everything on my own" is something that was already present
> into the old v1 driver, I am *not adding* this code, but *moving it around*.
> 
> I cannot migrate the v1 driver to the HDMI helpers right now because in this
> moment I have no way to test that and I don't want to break any functionality.
> 
> If you check patch 15, you'll see that I am indeed using all of the helper
> goodies - but for now only on the new driver, and not on the old one.
> 
> I do plan to migrate the v1 driver to the new helpers as well, but I would
> (please) really prefer to do that only after the v2 driver is upstreamed.
> 
> Is that okay for you?

Yes, I've sent this comment before seeing the last patches.

> 
> Cheers,
> Angelo
> 
> > >   }
> > >   static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
> > 
> 
> 
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +struct mtk_hdmi_ver_conf {
> +       const struct drm_bridge_funcs *bridge_funcs;
> +       const struct hdmi_codec_ops *codec_ops;
> +       const char * const *mtk_hdmi_clock_names;
> +       int num_clocks;
> +       bool hdr_support;
> +};

Because this patch is a little big. So I would like to separate struct mtk_hdmi_ver_conf related part to an independent patch.
The modification is still in mtk_hdmi.c
And the rest part is moving common part to mtk_hdmi_common.c


Regards,
CK

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/Kconfig           |  11 +-
>  drivers/gpu/drm/mediatek/Makefile          |   1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi.c        | 724 +++------------------
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 425 ++++++++++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.h | 203 ++++++
>  5 files changed, 729 insertions(+), 635 deletions(-)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> 
> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> index f496e6cfdfe0..73459f07dae3 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -34,10 +34,19 @@ config DRM_MEDIATEK_DP
>         help
>           DRM/KMS Display Port driver for MediaTek SoCs.
> 
> +config DRM_MEDIATEK_HDMI_COMMON
> +       tristate
> +       depends on DRM_MEDIATEK
> +       select DRM_DISPLAY_HDMI_HELPER
> +       select DRM_DISPLAY_HELPER
> +       select SND_SOC_HDMI_CODEC if SND_SOC
> +       help
> +         MediaTek SoC HDMI common library
> +
>  config DRM_MEDIATEK_HDMI
>         tristate "DRM HDMI Support for Mediatek SoCs"
>         depends on DRM_MEDIATEK
> -       select SND_SOC_HDMI_CODEC if SND_SOC
> +       select DRM_MEDIATEK_HDMI_COMMON
>         select PHY_MTK_HDMI
>         help
>           DRM/KMS HDMI driver for Mediatek SoCs
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 32a2ed6c0cfe..8973d7ba37d3 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -25,6 +25,7 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
>                           mtk_hdmi.o \
>                           mtk_hdmi_ddc.o
> 
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
>  obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> 
>  obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> index 7808141526fa..44b2bc55afa3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
> @@ -31,6 +31,7 @@
>  #include <drm/drm_probe_helper.h>
> 
>  #include "mtk_cec.h"
> +#include "mtk_hdmi_common.h"
>  #include "mtk_hdmi_regs.h"
> 
>  #define NCTS_BYTES     7
> @@ -43,149 +44,13 @@ enum mtk_hdmi_clk_id {
>         MTK_HDMI_CLK_COUNT
>  };
> 
> -enum hdmi_aud_input_type {
> -       HDMI_AUD_INPUT_I2S = 0,
> -       HDMI_AUD_INPUT_SPDIF,
> -};
> -
> -enum hdmi_aud_i2s_fmt {
> -       HDMI_I2S_MODE_RJT_24BIT = 0,
> -       HDMI_I2S_MODE_RJT_16BIT,
> -       HDMI_I2S_MODE_LJT_24BIT,
> -       HDMI_I2S_MODE_LJT_16BIT,
> -       HDMI_I2S_MODE_I2S_24BIT,
> -       HDMI_I2S_MODE_I2S_16BIT
> -};
> -
> -enum hdmi_aud_mclk {
> -       HDMI_AUD_MCLK_128FS,
> -       HDMI_AUD_MCLK_192FS,
> -       HDMI_AUD_MCLK_256FS,
> -       HDMI_AUD_MCLK_384FS,
> -       HDMI_AUD_MCLK_512FS,
> -       HDMI_AUD_MCLK_768FS,
> -       HDMI_AUD_MCLK_1152FS,
> -};
> -
> -enum hdmi_aud_channel_type {
> -       HDMI_AUD_CHAN_TYPE_1_0 = 0,
> -       HDMI_AUD_CHAN_TYPE_1_1,
> -       HDMI_AUD_CHAN_TYPE_2_0,
> -       HDMI_AUD_CHAN_TYPE_2_1,
> -       HDMI_AUD_CHAN_TYPE_3_0,
> -       HDMI_AUD_CHAN_TYPE_3_1,
> -       HDMI_AUD_CHAN_TYPE_4_0,
> -       HDMI_AUD_CHAN_TYPE_4_1,
> -       HDMI_AUD_CHAN_TYPE_5_0,
> -       HDMI_AUD_CHAN_TYPE_5_1,
> -       HDMI_AUD_CHAN_TYPE_6_0,
> -       HDMI_AUD_CHAN_TYPE_6_1,
> -       HDMI_AUD_CHAN_TYPE_7_0,
> -       HDMI_AUD_CHAN_TYPE_7_1,
> -       HDMI_AUD_CHAN_TYPE_3_0_LRS,
> -       HDMI_AUD_CHAN_TYPE_3_1_LRS,
> -       HDMI_AUD_CHAN_TYPE_4_0_CLRS,
> -       HDMI_AUD_CHAN_TYPE_4_1_CLRS,
> -       HDMI_AUD_CHAN_TYPE_6_1_CS,
> -       HDMI_AUD_CHAN_TYPE_6_1_CH,
> -       HDMI_AUD_CHAN_TYPE_6_1_OH,
> -       HDMI_AUD_CHAN_TYPE_6_1_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
> -       HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
> -       HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
> -       HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
> -       HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
> -       HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
> -       HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
> -       HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
> -       HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
> -       HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
> -       HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
> -       HDMI_AUD_CHAN_TYPE_6_0_CS,
> -       HDMI_AUD_CHAN_TYPE_6_0_CH,
> -       HDMI_AUD_CHAN_TYPE_6_0_OH,
> -       HDMI_AUD_CHAN_TYPE_6_0_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
> -       HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
> -       HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
> -       HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
> -       HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
> -       HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
> -       HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
> -       HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
> -       HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
> -       HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
> -       HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
> -       HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
> -       HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
> -       HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
> -};
> -
> -enum hdmi_aud_channel_swap_type {
> -       HDMI_AUD_SWAP_LR,
> -       HDMI_AUD_SWAP_LFE_CC,
> -       HDMI_AUD_SWAP_LSRS,
> -       HDMI_AUD_SWAP_RLS_RRS,
> -       HDMI_AUD_SWAP_LR_STATUS,
> -};
> -
> -struct hdmi_audio_param {
> -       enum hdmi_audio_coding_type aud_codec;
> -       enum hdmi_audio_sample_size aud_sample_size;
> -       enum hdmi_aud_input_type aud_input_type;
> -       enum hdmi_aud_i2s_fmt aud_i2s_fmt;
> -       enum hdmi_aud_mclk aud_mclk;
> -       enum hdmi_aud_channel_type aud_input_chan_type;
> -       struct hdmi_codec_params codec_params;
> -};
> -
> -struct mtk_hdmi_conf {
> -       bool tz_disabled;
> -       bool cea_modes_only;
> -       unsigned long max_mode_clock;
> -};
> -
> -struct mtk_hdmi {
> -       struct drm_bridge bridge;
> -       struct drm_bridge *next_bridge;
> -       struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
> -       struct device *dev;
> -       const struct mtk_hdmi_conf *conf;
> -       struct phy *phy;
> -       struct device *cec_dev;
> -       struct i2c_adapter *ddc_adpt;
> -       struct clk *clk[MTK_HDMI_CLK_COUNT];
> -       struct drm_display_mode mode;
> -       bool dvi_mode;
> -       u32 min_clock;
> -       u32 max_clock;
> -       u32 max_hdisplay;
> -       u32 max_vdisplay;
> -       u32 ibias;
> -       u32 ibias_up;
> -       struct regmap *sys_regmap;
> -       unsigned int sys_offset;
> -       struct regmap *regs;
> -       enum hdmi_colorspace csp;
> -       struct hdmi_audio_param aud_param;
> -       bool audio_enable;
> -       bool powered;
> -       bool enabled;
> -       hdmi_codec_plugged_cb plugged_cb;
> -       struct device *codec_dev;
> -       struct mutex update_plugged_status_lock;
> +const char * const mtk_hdmi_clk_names_v1[MTK_HDMI_CLK_COUNT] = {
> +       [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
> +       [MTK_HDMI_CLK_HDMI_PLL] = "pll",
> +       [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
> +       [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
>  };
> 
> -static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
> -{
> -       return container_of(b, struct mtk_hdmi, bridge);
> -}
> -
>  static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
>  {
>         regmap_update_bits(hdmi->regs, VIDEO_SOURCE_SEL,
> @@ -606,81 +471,6 @@ static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
>         regmap_write(hdmi->regs, GRL_CFG5, val);
>  }
> 
> -struct hdmi_acr_n {
> -       unsigned int clock;
> -       unsigned int n[3];
> -};
> -
> -/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
> -static const struct hdmi_acr_n hdmi_rec_n_table[] = {
> -       /* Clock, N: 32kHz 44.1kHz 48kHz */
> -       {  25175, {  4576,  7007,  6864 } },
> -       {  74176, { 11648, 17836, 11648 } },
> -       { 148352, { 11648,  8918,  5824 } },
> -       { 296703, {  5824,  4459,  5824 } },
> -       { 297000, {  3072,  4704,  5120 } },
> -       {      0, {  4096,  6272,  6144 } }, /* all other TMDS clocks */
> -};
> -
> -/**
> - * hdmi_recommended_n() - Return N value recommended by HDMI specification
> - * @freq: audio sample rate in Hz
> - * @clock: rounded TMDS clock in kHz
> - */
> -static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
> -{
> -       const struct hdmi_acr_n *recommended;
> -       unsigned int i;
> -
> -       for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
> -               if (clock == hdmi_rec_n_table[i].clock)
> -                       break;
> -       }
> -       recommended = hdmi_rec_n_table + i;
> -
> -       switch (freq) {
> -       case 32000:
> -               return recommended->n[0];
> -       case 44100:
> -               return recommended->n[1];
> -       case 48000:
> -               return recommended->n[2];
> -       case 88200:
> -               return recommended->n[1] * 2;
> -       case 96000:
> -               return recommended->n[2] * 2;
> -       case 176400:
> -               return recommended->n[1] * 4;
> -       case 192000:
> -               return recommended->n[2] * 4;
> -       default:
> -               return (128 * freq) / 1000;
> -       }
> -}
> -
> -static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
> -{
> -       switch (clock) {
> -       case 25175:
> -               return 25174825;        /* 25.2/1.001 MHz */
> -       case 74176:
> -               return 74175824;        /* 74.25/1.001 MHz */
> -       case 148352:
> -               return 148351648;       /* 148.5/1.001 MHz */
> -       case 296703:
> -               return 296703297;       /* 297/1.001 MHz */
> -       default:
> -               return clock * 1000;
> -       }
> -}
> -
> -static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
> -                                     unsigned int tmds_clock, unsigned int n)
> -{
> -       return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
> -                                    128 * audio_sample_rate);
> -}
> -
>  static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
>                                     unsigned int cts)
>  {
> @@ -710,9 +500,13 @@ static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
>                                      unsigned int clock)
>  {
>         unsigned int n, cts;
> +       int ret;
> 
> -       n = hdmi_recommended_n(sample_rate, clock);
> -       cts = hdmi_expected_cts(sample_rate, clock, n);
> +       ret = mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
> +       if (ret) {
> +               dev_err(hdmi->dev, "Invalid sample rate: %u\n", sample_rate);
> +               return;
> +       }
> 
>         dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
>                 __func__, sample_rate, clock, n, cts);
> @@ -829,7 +623,6 @@ static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
>         mtk_hdmi_hw_msic_setting(hdmi, mode);
>  }
> 
> -
>  static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
>  {
>         enum hdmi_aud_channel_type chan_type;
> @@ -920,53 +713,46 @@ static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
>         return 0;
>  }
> 
> -static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
> +static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, size_t bufsz,
>                                         struct drm_display_mode *mode)
>  {
>         struct hdmi_avi_infoframe frame;
> -       u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
>         ssize_t err;
> 
> -       err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
> -                                                      hdmi->curr_conn, mode);
> +       err = drm_hdmi_avi_infoframe_from_display_mode(&frame, hdmi->curr_conn, mode);
>         if (err < 0) {
>                 dev_err(hdmi->dev,
>                         "Failed to get AVI infoframe from mode: %zd\n", err);
>                 return err;
>         }
> 
> -       err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
> +       err = hdmi_avi_infoframe_pack(&frame, buffer, bufsz);
>         if (err < 0) {
>                 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
>                 return err;
>         }
> 
> -       mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
>         return 0;
>  }
> 
> -static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
> -                                       const char *vendor,
> -                                       const char *product)
> +static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi, u8 *buffer, size_t bufsz,
> +                                       const char *vendor, const char *product)
>  {
>         struct hdmi_spd_infoframe frame;
> -       u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
>         ssize_t err;
> 
>         err = hdmi_spd_infoframe_init(&frame, vendor, product);
>         if (err < 0) {
> -               dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
> -                       err);
> +               dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n", err);
>                 return err;
>         }
> 
> -       err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
> +       err = hdmi_spd_infoframe_pack(&frame, buffer, bufsz);
>         if (err < 0) {
>                 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
>                 return err;
>         }
> 
> -       mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
>         return 0;
>  }
> 
> @@ -1026,19 +812,12 @@ static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
>         return 0;
>  }
> 
> -static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
> +static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi, u8 *buffer_spd, size_t bufsz_spd,
> +                                   u8 *buffer_avi, size_t bufsz_avi,
> +                                   struct drm_display_mode *mode)
>  {
> -       struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> -
> -       hdmi->csp = HDMI_COLORSPACE_RGB;
> -       aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -       aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> -       aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> -       aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> -       aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> -       aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> -
> -       return 0;
> +       mtk_hdmi_setup_avi_infoframe(hdmi, buffer_avi, bufsz_avi, mode);
> +       mtk_hdmi_setup_spd_infoframe(hdmi, buffer_spd, bufsz_spd, "mediatek", "On-chip HDMI");
>  }
> 
>  static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
> @@ -1053,20 +832,6 @@ static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
>         hdmi->audio_enable = false;
>  }
> 
> -static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
> -                                   struct hdmi_audio_param *param)
> -{
> -       if (!hdmi->audio_enable) {
> -               dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
> -               return -EINVAL;
> -       }
> -       dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
> -               param->aud_codec, param->aud_input_type,
> -               param->aud_input_chan_type, param->codec_params.sample_rate);
> -       memcpy(&hdmi->aud_param, param, sizeof(*param));
> -       return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
> -}
> -
>  static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
>                                             struct drm_display_mode *mode)
>  {
> @@ -1095,27 +860,6 @@ static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
>         return 0;
>  }
> 
> -static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
> -       [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
> -       [MTK_HDMI_CLK_HDMI_PLL] = "pll",
> -       [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
> -       [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
> -};
> -
> -static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
> -                               struct device_node *np)
> -{
> -       int i;
> -
> -       for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
> -               hdmi->clk[i] = of_clk_get_by_name(np,
> -                                                 mtk_hdmi_clk_names[i]);
> -               if (IS_ERR(hdmi->clk[i]))
> -                       return PTR_ERR(hdmi->clk[i]);
> -       }
> -       return 0;
> -}
> -
>  static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
>  {
>         int ret;
> @@ -1125,13 +869,12 @@ static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
>                 return ret;
> 
>         ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
> -       if (ret)
> -               goto err;
> +       if (ret) {
> +               clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
> +               return ret;
> +       }
> 
>         return 0;
> -err:
> -       clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
> -       return ret;
>  }
> 
>  static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
> @@ -1143,10 +886,11 @@ static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
>  static enum drm_connector_status
>  mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
>  {
> -       bool connected;
> +       bool connected = true;
> 
>         mutex_lock(&hdmi->update_plugged_status_lock);
> -       connected = mtk_cec_hpd_high(hdmi->cec_dev);
> +       if (hdmi->cec_dev)
> +               connected = mtk_cec_hpd_high(hdmi->cec_dev);
>         if (hdmi->plugged_cb && hdmi->codec_dev)
>                 hdmi->plugged_cb(hdmi->codec_dev, connected);
>         mutex_unlock(&hdmi->update_plugged_status_lock);
> @@ -1254,18 +998,12 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
>                         return ret;
>         }
> 
> -       mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
> +       if (hdmi->cec_dev)
> +               mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
> 
>         return 0;
>  }
> 
> -static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> -                                      const struct drm_display_mode *mode,
> -                                      struct drm_display_mode *adjusted_mode)
> -{
> -       return true;
> -}
> -
>  static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
>                                            struct drm_bridge_state *old_bridge_state)
>  {
> @@ -1297,28 +1035,6 @@ static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
>         hdmi->powered = false;
>  }
> 
> -static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
> -                               const struct drm_display_mode *mode,
> -                               const struct drm_display_mode *adjusted_mode)
> -{
> -       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> -
> -       dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
> -               adjusted_mode->name, adjusted_mode->hdisplay);
> -       dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
> -               adjusted_mode->hsync_start, adjusted_mode->hsync_end,
> -               adjusted_mode->htotal);
> -       dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
> -               adjusted_mode->hskew, adjusted_mode->vdisplay);
> -       dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
> -               adjusted_mode->vsync_start, adjusted_mode->vsync_end,
> -               adjusted_mode->vtotal);
> -       dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
> -               adjusted_mode->vscan, adjusted_mode->flags);
> -
> -       drm_mode_copy(&hdmi->mode, adjusted_mode);
> -}
> -
>  static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>                                               struct drm_bridge_state *old_state)
>  {
> @@ -1330,21 +1046,13 @@ static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
>         hdmi->powered = true;
>  }
> 
> -static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
> -                                   struct drm_display_mode *mode)
> -{
> -       mtk_hdmi_setup_audio_infoframe(hdmi);
> -       mtk_hdmi_setup_avi_infoframe(hdmi, mode);
> -       mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
> -       if (mode->flags & DRM_MODE_FLAG_3D_MASK)
> -               mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
> -}
> -
>  static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
>                                           struct drm_bridge_state *old_state)
>  {
>         struct drm_atomic_state *state = old_state->base.state;
>         struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +       u8 buffer_spd[HDMI_INFOFRAME_SIZE(SPD)];
> +       u8 buffer_avi[HDMI_INFOFRAME_SIZE(AVI)];
> 
>         /* Retrieve the connector through the atomic state. */
>         hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
> @@ -1354,12 +1062,16 @@ static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
>         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
>         clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
>         phy_power_on(hdmi->phy);
> -       mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
> +       mtk_hdmi_setup_audio_infoframe(hdmi);
> +       mtk_hdmi_send_infoframe(hdmi, buffer_spd, sizeof(buffer_spd),
> +                               buffer_avi, sizeof(buffer_avi), &hdmi->mode);
> +       if (hdmi->mode.flags & DRM_MODE_FLAG_3D_MASK)
> +               mtk_hdmi_setup_vendor_specific_infoframe(hdmi, &hdmi->mode);
> 
>         hdmi->enabled = true;
>  }
> 
> -static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
> +const struct drm_bridge_funcs mtk_mt8183_hdmi_bridge_funcs = {
>         .mode_valid = mtk_hdmi_bridge_mode_valid,
>         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
>         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> @@ -1375,180 +1087,19 @@ static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
>         .edid_read = mtk_hdmi_bridge_edid_read,
>  };
> 
> -static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
> -                                  struct platform_device *pdev)
> -{
> -       struct device *dev = &pdev->dev;
> -       struct device_node *np = dev->of_node;
> -       struct device_node *cec_np, *remote, *i2c_np;
> -       struct platform_device *cec_pdev;
> -       struct regmap *regmap;
> -       int ret;
> -
> -       ret = mtk_hdmi_get_all_clk(hdmi, np);
> -       if (ret) {
> -               if (ret != -EPROBE_DEFER)
> -                       dev_err(dev, "Failed to get clocks: %d\n", ret);
> -
> -               return ret;
> -       }
> -
> -       /* The CEC module handles HDMI hotplug detection */
> -       cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
> -       if (!cec_np) {
> -               dev_err(dev, "Failed to find CEC node\n");
> -               return -EINVAL;
> -       }
> -
> -       cec_pdev = of_find_device_by_node(cec_np);
> -       if (!cec_pdev) {
> -               dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
> -                       cec_np);
> -               of_node_put(cec_np);
> -               return -EPROBE_DEFER;
> -       }
> -       of_node_put(cec_np);
> -       hdmi->cec_dev = &cec_pdev->dev;
> -
> -       /*
> -        * The mediatek,syscon-hdmi property contains a phandle link to the
> -        * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
> -        * registers it contains.
> -        */
> -       regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
> -       ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
> -                                        &hdmi->sys_offset);
> -       if (IS_ERR(regmap))
> -               ret = PTR_ERR(regmap);
> -       if (ret) {
> -               dev_err(dev,
> -                       "Failed to get system configuration registers: %d\n",
> -                       ret);
> -               goto put_device;
> -       }
> -       hdmi->sys_regmap = regmap;
> -
> -       hdmi->regs = device_node_to_regmap(dev->of_node);
> -       if (IS_ERR(hdmi->regs)) {
> -               ret = PTR_ERR(hdmi->regs);
> -               goto put_device;
> -       }
> -
> -       remote = of_graph_get_remote_node(np, 1, 0);
> -       if (!remote) {
> -               ret = -EINVAL;
> -               goto put_device;
> -       }
> -
> -       if (!of_device_is_compatible(remote, "hdmi-connector")) {
> -               hdmi->next_bridge = of_drm_find_bridge(remote);
> -               if (!hdmi->next_bridge) {
> -                       dev_err(dev, "Waiting for external bridge\n");
> -                       of_node_put(remote);
> -                       ret = -EPROBE_DEFER;
> -                       goto put_device;
> -               }
> -       }
> -
> -       i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
> -       if (!i2c_np) {
> -               dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
> -                       remote);
> -               of_node_put(remote);
> -               ret = -EINVAL;
> -               goto put_device;
> -       }
> -       of_node_put(remote);
> -
> -       hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
> -       of_node_put(i2c_np);
> -       if (!hdmi->ddc_adpt) {
> -               dev_err(dev, "Failed to get ddc i2c adapter by node\n");
> -               ret = -EINVAL;
> -               goto put_device;
> -       }
> -
> -       return 0;
> -put_device:
> -       put_device(hdmi->cec_dev);
> -       return ret;
> -}
> -
>  /*
>   * HDMI audio codec callbacks
>   */
> -
>  static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
>                                     struct hdmi_codec_daifmt *daifmt,
>                                     struct hdmi_codec_params *params)
>  {
>         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> -       struct hdmi_audio_param hdmi_params;
> -       unsigned int chan = params->cea.channels;
> -
> -       dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
> -               params->sample_rate, params->sample_width, chan);
> -
> -       if (!hdmi->bridge.encoder)
> -               return -ENODEV;
> -
> -       switch (chan) {
> -       case 2:
> -               hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> -               break;
> -       case 4:
> -               hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
> -               break;
> -       case 6:
> -               hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
> -               break;
> -       case 8:
> -               hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
> -               break;
> -       default:
> -               dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
> -               return -EINVAL;
> -       }
> -
> -       switch (params->sample_rate) {
> -       case 32000:
> -       case 44100:
> -       case 48000:
> -       case 88200:
> -       case 96000:
> -       case 176400:
> -       case 192000:
> -               break;
> -       default:
> -               dev_err(hdmi->dev, "rate[%d] not supported!\n",
> -                       params->sample_rate);
> -               return -EINVAL;
> -       }
> 
> -       switch (daifmt->fmt) {
> -       case HDMI_I2S:
> -               hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -               hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> -               hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
> -               hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> -               hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
> -               break;
> -       case HDMI_SPDIF:
> -               hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> -               hdmi_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> -               hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> -               break;
> -       default:
> -               dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
> -                       daifmt->fmt);
> -               return -EINVAL;
> +       if (hdmi->audio_enable) {
> +               mtk_hdmi_audio_params(hdmi, daifmt, params);
> +               mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
>         }
> -
> -       memcpy(&hdmi_params.codec_params, params,
> -              sizeof(hdmi_params.codec_params));
> -
> -       mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
> -
>         return 0;
>  }
> 
> @@ -1582,28 +1133,13 @@ mtk_hdmi_audio_mute(struct device *dev, void *data,
>         return 0;
>  }
> 
> -static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
> -{
> -       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> -
> -       if (hdmi->enabled)
> -               memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
> -       else
> -               memset(buf, 0, len);
> -       return 0;
> -}
> -
>  static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
>                                           hdmi_codec_plugged_cb fn,
>                                           struct device *codec_dev)
>  {
>         struct mtk_hdmi *hdmi = data;
> 
> -       mutex_lock(&hdmi->update_plugged_status_lock);
> -       hdmi->plugged_cb = fn;
> -       hdmi->codec_dev = codec_dev;
> -       mutex_unlock(&hdmi->update_plugged_status_lock);
> -
> +       mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
>         mtk_hdmi_update_plugged_status(hdmi);
> 
>         return 0;
> @@ -1619,165 +1155,85 @@ static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
>         .no_capture_mute = 1,
>  };
> 
> -static int mtk_hdmi_register_audio_driver(struct device *dev)
> +static __maybe_unused int mtk_hdmi_suspend(struct device *dev)
>  {
>         struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> -       struct hdmi_codec_pdata codec_data = {
> -               .ops = &mtk_hdmi_audio_codec_ops,
> -               .max_i2s_channels = 2,
> -               .i2s = 1,
> -               .data = hdmi,
> -       };
> -       struct platform_device *pdev;
> -
> -       pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
> -                                            PLATFORM_DEVID_AUTO, &codec_data,
> -                                            sizeof(codec_data));
> -       if (IS_ERR(pdev))
> -               return PTR_ERR(pdev);
> -
> -       DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
> +
> +       mtk_hdmi_clk_disable_audio(hdmi);
> +
>         return 0;
>  }
> 
> -static int mtk_hdmi_probe(struct platform_device *pdev)
> +static __maybe_unused int mtk_hdmi_resume(struct device *dev)
>  {
> -       struct mtk_hdmi *hdmi;
> -       struct device *dev = &pdev->dev;
> -       int ret;
> -
> -       hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
> -       if (!hdmi)
> -               return -ENOMEM;
> +       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> 
> -       hdmi->dev = dev;
> -       hdmi->conf = of_device_get_match_data(dev);
> +       return mtk_hdmi_clk_enable_audio(hdmi);
> +}
> 
> -       ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
> -       if (ret)
> -               return ret;
> +static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops, mtk_hdmi_suspend, mtk_hdmi_resume);
> 
> -       hdmi->phy = devm_phy_get(dev, "hdmi");
> -       if (IS_ERR(hdmi->phy))
> -               return dev_err_probe(dev, PTR_ERR(hdmi->phy),
> -                                    "Failed to get HDMI PHY\n");
> +static const struct mtk_hdmi_ver_conf mtk_hdmi_v1_ver_conf = {
> +       .bridge_funcs = &mtk_mt8183_hdmi_bridge_funcs,
> +       .codec_ops = &mtk_hdmi_audio_codec_ops,
> +       .mtk_hdmi_clock_names = mtk_hdmi_clk_names_v1,
> +       .num_clocks = ARRAY_SIZE(mtk_hdmi_clk_names_v1)
> +};
> 
> -       mutex_init(&hdmi->update_plugged_status_lock);
> -       platform_set_drvdata(pdev, hdmi);
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
> +       .tz_disabled = true,
> +       .ver_conf = &mtk_hdmi_v1_ver_conf
> +};
> 
> -       ret = mtk_hdmi_output_init(hdmi);
> -       if (ret)
> -               return dev_err_probe(dev, ret,
> -                                    "Failed to initialize hdmi output\n");
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
> +       .max_mode_clock = 148500,
> +       .cea_modes_only = true,
> +       .ver_conf = &mtk_hdmi_v1_ver_conf
> +};
> 
> -       ret = mtk_hdmi_register_audio_driver(dev);
> -       if (ret)
> -               return dev_err_probe(dev, ret,
> -                                    "Failed to register audio driver\n");
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8173 = {
> +       .ver_conf = &mtk_hdmi_v1_ver_conf
> +};
> 
> -       hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
> -       hdmi->bridge.of_node = pdev->dev.of_node;
> -       hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
> -                        | DRM_BRIDGE_OP_HPD;
> -       hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> -       drm_bridge_add(&hdmi->bridge);
> +static int mtk_hdmi_probe(struct platform_device *pdev)
> +{
> +       struct mtk_hdmi *hdmi;
> 
> -       ret = mtk_hdmi_clk_enable_audio(hdmi);
> -       if (ret) {
> -               drm_bridge_remove(&hdmi->bridge);
> -               return dev_err_probe(dev, ret,
> -                                    "Failed to enable audio clocks\n");
> -       }
> +       hdmi = mtk_hdmi_common_probe(pdev);
> +       if (IS_ERR(hdmi))
> +               return PTR_ERR(hdmi);
> 
> -       return 0;
> +       return mtk_hdmi_clk_enable_audio(hdmi);
>  }
> 
>  static void mtk_hdmi_remove(struct platform_device *pdev)
>  {
>         struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
> 
> -       drm_bridge_remove(&hdmi->bridge);
> -       mtk_hdmi_clk_disable_audio(hdmi);
> -}
> -
> -#ifdef CONFIG_PM_SLEEP
> -static int mtk_hdmi_suspend(struct device *dev)
> -{
> -       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> -
>         mtk_hdmi_clk_disable_audio(hdmi);
> -
> -       return 0;
> -}
> -
> -static int mtk_hdmi_resume(struct device *dev)
> -{
> -       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> -       int ret = 0;
> -
> -       ret = mtk_hdmi_clk_enable_audio(hdmi);
> -       if (ret) {
> -               dev_err(dev, "hdmi resume failed!\n");
> -               return ret;
> -       }
> -
> -       return 0;
> +       i2c_put_adapter(hdmi->ddc_adpt);
>  }
> -#endif
> -static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
> -                        mtk_hdmi_suspend, mtk_hdmi_resume);
> -
> -static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
> -       .tz_disabled = true,
> -};
> -
> -static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
> -       .max_mode_clock = 148500,
> -       .cea_modes_only = true,
> -};
> 
> -static const struct of_device_id mtk_hdmi_of_ids[] = {
> -       { .compatible = "mediatek,mt2701-hdmi",
> -         .data = &mtk_hdmi_conf_mt2701,
> -       },
> -       { .compatible = "mediatek,mt8167-hdmi",
> -         .data = &mtk_hdmi_conf_mt8167,
> -       },
> -       { .compatible = "mediatek,mt8173-hdmi",
> -       },
> -       {}
> +static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
> +       { .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
> +       { .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
> +       { .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 },
> +       { /* sentinel */ }
>  };
> -MODULE_DEVICE_TABLE(of, mtk_hdmi_of_ids);
> +MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
> 
>  static struct platform_driver mtk_hdmi_driver = {
>         .probe = mtk_hdmi_probe,
> -       .remove_new = mtk_hdmi_remove,
> +       .remove = mtk_hdmi_remove,
>         .driver = {
>                 .name = "mediatek-drm-hdmi",
> -               .of_match_table = mtk_hdmi_of_ids,
> +               .of_match_table = mtk_drm_hdmi_of_ids,
>                 .pm = &mtk_hdmi_pm_ops,
>         },
>  };
> -
> -static struct platform_driver * const mtk_hdmi_drivers[] = {
> -       &mtk_hdmi_driver,
> -};
> -
> -static int __init mtk_hdmitx_init(void)
> -{
> -       return platform_register_drivers(mtk_hdmi_drivers,
> -                                        ARRAY_SIZE(mtk_hdmi_drivers));
> -}
> -
> -static void __exit mtk_hdmitx_exit(void)
> -{
> -       platform_unregister_drivers(mtk_hdmi_drivers,
> -                                   ARRAY_SIZE(mtk_hdmi_drivers));
> -}
> -
> -module_init(mtk_hdmitx_init);
> -module_exit(mtk_hdmitx_exit);
> +module_platform_driver(mtk_hdmi_driver);
> 
>  MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
> +MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
>  MODULE_DESCRIPTION("MediaTek HDMI Driver");
>  MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> new file mode 100644
> index 000000000000..1b23ab6969ec
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> @@ -0,0 +1,425 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Copyright (c) 2022 BayLibre, SAS
> + * Copyright (c) 2024 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#include <drm/drm_modes.h>
> +#include <linux/device.h>
> +#include <linux/hdmi.h>
> +#include <linux/i2c.h>
> +#include <linux/math.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/mfd/syscon.h>
> +#include <sound/hdmi-codec.h>
> +
> +#include "mtk_hdmi_common.h"
> +
> +struct hdmi_acr_n {
> +       unsigned int clock;
> +       unsigned int n[3];
> +};
> +
> +/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
> +static const struct hdmi_acr_n hdmi_rec_n_table[] = {
> +       /* Clock, N: 32kHz 44.1kHz 48kHz */
> +       { 25175,  {  4576,  7007,  6864 } },
> +       { 74176,  { 11648, 17836, 11648 } },
> +       { 148352, { 11648,  8918,  5824 } },
> +       { 296703, {  5824,  4459,  5824 } },
> +       { 297000, {  3072,  4704,  5120 } },
> +       { 0,      {  4096,  6272,  6144 } }, /* all other TMDS clocks */
> +};
> +
> +/**
> + * hdmi_recommended_n() - Return N value recommended by HDMI specification
> + * @freq: audio sample rate in Hz
> + * @clock: rounded TMDS clock in kHz
> + */
> +static int hdmi_recommended_n(unsigned int freq, unsigned int clock)
> +{
> +       const struct hdmi_acr_n *recommended;
> +       unsigned int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
> +               if (clock == hdmi_rec_n_table[i].clock)
> +                       break;
> +       }
> +
> +       if (i == ARRAY_SIZE(hdmi_rec_n_table))
> +               return -EINVAL;
> +
> +       recommended = hdmi_rec_n_table + i;
> +
> +       switch (freq) {
> +       case 32000:
> +               return recommended->n[0];
> +       case 44100:
> +               return recommended->n[1];
> +       case 48000:
> +               return recommended->n[2];
> +       case 88200:
> +               return recommended->n[1] * 2;
> +       case 96000:
> +               return recommended->n[2] * 2;
> +       case 176400:
> +               return recommended->n[1] * 4;
> +       case 192000:
> +               return recommended->n[2] * 4;
> +       default:
> +               return (128 * freq) / 1000;
> +       }
> +}
> +
> +static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
> +{
> +       switch (clock) {
> +       case 25175:
> +               return 25174825; /* 25.2/1.001 MHz */
> +       case 74176:
> +               return 74175824; /* 74.25/1.001 MHz */
> +       case 148352:
> +               return 148351648; /* 148.5/1.001 MHz */
> +       case 296703:
> +               return 296703297; /* 297/1.001 MHz */
> +       default:
> +               return clock * 1000;
> +       }
> +}
> +
> +static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
> +                                     unsigned int tmds_clock, unsigned int n)
> +{
> +       return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
> +                                    128 * audio_sample_rate);
> +}
> +
> +int mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
> +                     unsigned int *n, unsigned int *cts)
> +{
> +       int rec_n = hdmi_recommended_n(sample_rate, clock);
> +
> +       if (rec_n < 0)
> +               return rec_n;
> +
> +       *cts = hdmi_expected_cts(sample_rate, clock, rec_n);
> +       *n = rec_n;
> +
> +       return 0;
> +}
> +
> +int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi,
> +                         struct hdmi_codec_daifmt *daifmt,
> +                         struct hdmi_codec_params *params)
> +{
> +       struct hdmi_audio_param aud_params = { 0 };
> +       unsigned int chan = params->cea.channels;
> +
> +       dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
> +               params->sample_rate, params->sample_width, chan);
> +
> +       if (!hdmi->bridge.encoder)
> +               return -ENODEV;
> +
> +       switch (chan) {
> +       case 2:
> +               aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> +               break;
> +       case 4:
> +               aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
> +               break;
> +       case 6:
> +               aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
> +               break;
> +       case 8:
> +               aud_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
> +               break;
> +       default:
> +               dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
> +               return -EINVAL;
> +       }
> +
> +       switch (params->sample_rate) {
> +       case 32000:
> +       case 44100:
> +       case 48000:
> +       case 88200:
> +       case 96000:
> +       case 176400:
> +       case 192000:
> +               break;
> +       default:
> +               dev_err(hdmi->dev, "rate[%d] not supported!\n",
> +                       params->sample_rate);
> +               return -EINVAL;
> +       }
> +
> +       switch (daifmt->fmt) {
> +       case HDMI_I2S:
> +               aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +               aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +               aud_params.aud_input_type = HDMI_AUD_INPUT_I2S;
> +               aud_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> +               aud_params.aud_mclk = HDMI_AUD_MCLK_128FS;
> +               break;
> +       case HDMI_SPDIF:
> +               aud_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +               aud_params.aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +               aud_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
> +               break;
> +       default:
> +               dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
> +                       daifmt->fmt);
> +               return -EINVAL;
> +       }
> +       memcpy(&aud_params.codec_params, params, sizeof(aud_params.codec_params));
> +       memcpy(&hdmi->aud_param, &aud_params, sizeof(aud_params));
> +
> +       dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
> +               aud_params.aud_codec, aud_params.aud_input_type,
> +               aud_params.aud_input_chan_type, aud_params.codec_params.sample_rate);
> +
> +       return 0;
> +}
> +
> +int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
> +{
> +       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +       if (hdmi->enabled)
> +               memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
> +       else
> +               memset(buf, 0, len);
> +
> +       return 0;
> +}
> +
> +void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
> +                                  struct device *codec_dev)
> +{
> +       mutex_lock(&hdmi->update_plugged_status_lock);
> +       hdmi->plugged_cb = fn;
> +       hdmi->codec_dev = codec_dev;
> +       mutex_unlock(&hdmi->update_plugged_status_lock);
> +}
> +
> +static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi, struct device_node *np,
> +                               const char * const *mtk_hdmi_clk_names, size_t num_clocks)
> +{
> +       int i;
> +
> +       for (i = 0; i < num_clocks; i++) {
> +               hdmi->clk[i] = of_clk_get_by_name(np, mtk_hdmi_clk_names[i]);
> +
> +               if (IS_ERR(hdmi->clk[i]))
> +                       return PTR_ERR(hdmi->clk[i]);
> +       }
> +
> +       return 0;
> +}
> +
> +bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> +                               const struct drm_display_mode *mode,
> +                               struct drm_display_mode *adjusted_mode)
> +{
> +       return true;
> +}
> +
> +void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
> +                             const struct drm_display_mode *mode,
> +                             const struct drm_display_mode *adjusted_mode)
> +{
> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +       drm_mode_copy(&hdmi->mode, adjusted_mode);
> +}
> +
> +static int mtk_hdmi_get_cec_dev(struct mtk_hdmi *hdmi, struct device *dev, struct device_node *np)
> +{
> +       struct platform_device *cec_pdev;
> +       struct device_node *cec_np;
> +       int ret;
> +
> +       /* The CEC module handles HDMI hotplug detection */
> +       cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
> +       if (!cec_np)
> +               return dev_err_probe(dev, -ENOTSUPP, "Failed to find CEC node\n");
> +
> +       cec_pdev = of_find_device_by_node(cec_np);
> +       if (!cec_pdev) {
> +               dev_err(hdmi->dev, "Waiting for CEC device %pOF\n", cec_np);
> +               of_node_put(cec_np);
> +               return -EPROBE_DEFER;
> +       }
> +       of_node_put(cec_np);
> +
> +       /*
> +        * The mediatek,syscon-hdmi property contains a phandle link to the
> +        * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
> +        * registers it contains.
> +        */
> +       hdmi->sys_regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
> +       if (IS_ERR(hdmi->sys_regmap))
> +               return PTR_ERR(hdmi->sys_regmap);
> +
> +       ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1, &hdmi->sys_offset);
> +       if (ret)
> +               return dev_err_probe(dev, ret,
> +                                    "Failed to get system configuration registers\n");
> +
> +       hdmi->cec_dev = &cec_pdev->dev;
> +       return 0;
> +}
> +
> +static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device *pdev,
> +                                  const char * const *clk_names, size_t num_clocks)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *np = dev->of_node;
> +       struct device_node *remote, *i2c_np;
> +       int ret;
> +
> +       ret = mtk_hdmi_get_all_clk(hdmi, np, clk_names, num_clocks);
> +       if (ret)
> +               return dev_err_probe(dev, ret, "Failed to get clocks\n");
> +
> +       hdmi->irq = platform_get_irq(pdev, 0);
> +       if (!hdmi->irq)
> +               return hdmi->irq;
> +
> +       hdmi->regs = device_node_to_regmap(dev->of_node);
> +       if (IS_ERR(hdmi->regs))
> +               return PTR_ERR(hdmi->regs);
> +
> +       remote = of_graph_get_remote_node(np, 1, 0);
> +       if (!remote)
> +               return dev_err_probe(dev, -EINVAL, "Cannot find HDMI input port\n");
> +
> +       if (!of_device_is_compatible(remote, "hdmi-connector")) {
> +               hdmi->next_bridge = of_drm_find_bridge(remote);
> +               if (!hdmi->next_bridge) {
> +                       dev_err(dev, "Waiting for external bridge\n");
> +                       of_node_put(remote);
> +                       return -EPROBE_DEFER;
> +               }
> +       }
> +
> +       i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
> +       if (!i2c_np) {
> +               of_node_put(pdev->dev.of_node);
> +               return dev_err_probe(dev, -EINVAL, "No ddc-i2c-bus in connector\n");
> +       }
> +
> +       hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
> +       of_node_put(i2c_np);
> +       if (!hdmi->ddc_adpt) {
> +               dev_err(dev, "Failed to get ddc i2c adapter by node");
> +               return -EPROBE_DEFER;
> +       }
> +
> +       ret = mtk_hdmi_get_cec_dev(hdmi, dev, np);
> +       if (ret == -ENOTSUPP)
> +               dev_info(dev, "CEC support unavailable: node not found\n");
> +       else if (ret)
> +               return ret;
> +
> +       return 0;
> +}
> +
> +static void mtk_hdmi_unregister_audio_driver(void *data)
> +{
> +       platform_device_unregister(data);
> +}
> +
> +static int mtk_hdmi_register_audio_driver(struct device *dev)
> +{
> +       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +       struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> +       struct hdmi_codec_pdata codec_data = {
> +               .i2s = 1,
> +               .max_i2s_channels = 2,
> +               .data = hdmi,
> +               .ops = hdmi->conf->ver_conf->codec_ops
> +       };
> +       int ret;
> +
> +       aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +       aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +       aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> +       aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> +       aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> +       aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
> +
> +       hdmi->audio_pdev = platform_device_register_data(dev,
> +                                                        HDMI_CODEC_DRV_NAME,
> +                                                        PLATFORM_DEVID_AUTO,
> +                                                        &codec_data,
> +                                                        sizeof(codec_data));
> +       if (IS_ERR(hdmi->audio_pdev))
> +               return PTR_ERR(hdmi->audio_pdev);
> +
> +       ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
> +                                      hdmi->audio_pdev);
> +       if (ret) {
> +               platform_device_unregister(hdmi->audio_pdev);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +
> +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
> +{
> +       const struct mtk_hdmi_ver_conf *ver_conf;
> +       struct device *dev = &pdev->dev;
> +       struct mtk_hdmi *hdmi;
> +       int ret;
> +
> +       hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
> +       if (!hdmi)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->dev = dev;
> +       hdmi->conf = of_device_get_match_data(dev);
> +       ver_conf = hdmi->conf->ver_conf;
> +
> +       hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
> +       if (!hdmi->clk)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->phy = devm_phy_get(dev, "hdmi");
> +       if (IS_ERR(hdmi->phy))
> +               return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
> +
> +       ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
> +                                     ver_conf->num_clocks);
> +       if (ret)
> +               return ERR_PTR(ret);
> +
> +       platform_set_drvdata(pdev, hdmi);
> +
> +       ret = mtk_hdmi_register_audio_driver(dev);
> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");

You change the error message here. If this is necessary, separate this to a refinement patch.

Regards,
CK

> +
> +       hdmi->bridge.funcs = ver_conf->bridge_funcs;
> +       hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
> +       hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> +       hdmi->bridge.of_node = pdev->dev.of_node;
> +
> +       ret = devm_drm_bridge_add(dev, &hdmi->bridge);
> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
> +
> +       return hdmi;
> +}
> +
> +MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
> +MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
> +MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
> +MODULE_DESCRIPTION("MediaTek HDMI Common Library");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> new file mode 100644
> index 000000000000..15121e8548f3
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> @@ -0,0 +1,203 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Copyright (c) 2022 BayLibre, SAS
> + */
> +
> +#ifndef _MTK_HDMI_COMMON_H
> +#define _MTK_HDMI_COMMON_H
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_bridge.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_print.h>
> +
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/hdmi.h>
> +#include <linux/i2c.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mutex.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +#include <sound/hdmi-codec.h>
> +
> +enum hdmi_aud_input_type {
> +       HDMI_AUD_INPUT_I2S = 0,
> +       HDMI_AUD_INPUT_SPDIF,
> +};
> +
> +enum hdmi_aud_i2s_fmt {
> +       HDMI_I2S_MODE_RJT_24BIT = 0,
> +       HDMI_I2S_MODE_RJT_16BIT,
> +       HDMI_I2S_MODE_LJT_24BIT,
> +       HDMI_I2S_MODE_LJT_16BIT,
> +       HDMI_I2S_MODE_I2S_24BIT,
> +       HDMI_I2S_MODE_I2S_16BIT
> +};
> +
> +enum hdmi_aud_mclk {
> +       HDMI_AUD_MCLK_128FS,
> +       HDMI_AUD_MCLK_192FS,
> +       HDMI_AUD_MCLK_256FS,
> +       HDMI_AUD_MCLK_384FS,
> +       HDMI_AUD_MCLK_512FS,
> +       HDMI_AUD_MCLK_768FS,
> +       HDMI_AUD_MCLK_1152FS,
> +};
> +
> +enum hdmi_aud_channel_type {
> +       HDMI_AUD_CHAN_TYPE_1_0 = 0,
> +       HDMI_AUD_CHAN_TYPE_1_1,
> +       HDMI_AUD_CHAN_TYPE_2_0,
> +       HDMI_AUD_CHAN_TYPE_2_1,
> +       HDMI_AUD_CHAN_TYPE_3_0,
> +       HDMI_AUD_CHAN_TYPE_3_1,
> +       HDMI_AUD_CHAN_TYPE_4_0,
> +       HDMI_AUD_CHAN_TYPE_4_1,
> +       HDMI_AUD_CHAN_TYPE_5_0,
> +       HDMI_AUD_CHAN_TYPE_5_1,
> +       HDMI_AUD_CHAN_TYPE_6_0,
> +       HDMI_AUD_CHAN_TYPE_6_1,
> +       HDMI_AUD_CHAN_TYPE_7_0,
> +       HDMI_AUD_CHAN_TYPE_7_1,
> +       HDMI_AUD_CHAN_TYPE_3_0_LRS,
> +       HDMI_AUD_CHAN_TYPE_3_1_LRS,
> +       HDMI_AUD_CHAN_TYPE_4_0_CLRS,
> +       HDMI_AUD_CHAN_TYPE_4_1_CLRS,
> +       HDMI_AUD_CHAN_TYPE_6_1_CS,
> +       HDMI_AUD_CHAN_TYPE_6_1_CH,
> +       HDMI_AUD_CHAN_TYPE_6_1_OH,
> +       HDMI_AUD_CHAN_TYPE_6_1_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
> +       HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
> +       HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
> +       HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
> +       HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
> +       HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
> +       HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
> +       HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
> +       HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
> +       HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
> +       HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
> +       HDMI_AUD_CHAN_TYPE_6_0_CS,
> +       HDMI_AUD_CHAN_TYPE_6_0_CH,
> +       HDMI_AUD_CHAN_TYPE_6_0_OH,
> +       HDMI_AUD_CHAN_TYPE_6_0_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
> +       HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
> +       HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
> +       HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
> +       HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
> +       HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
> +       HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
> +       HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
> +       HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
> +       HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
> +       HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
> +       HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
> +       HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
> +       HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
> +};
> +
> +enum hdmi_aud_channel_swap_type {
> +       HDMI_AUD_SWAP_LR,
> +       HDMI_AUD_SWAP_LFE_CC,
> +       HDMI_AUD_SWAP_LSRS,
> +       HDMI_AUD_SWAP_RLS_RRS,
> +       HDMI_AUD_SWAP_LR_STATUS,
> +};
> +
> +enum hdmi_hpd_state {
> +       HDMI_PLUG_OUT = 0,
> +       HDMI_PLUG_IN_AND_SINK_POWER_ON,
> +       HDMI_PLUG_IN_ONLY,
> +};
> +
> +struct hdmi_audio_param {
> +       enum hdmi_audio_coding_type aud_codec;
> +       enum hdmi_audio_sample_size aud_sample_size;
> +       enum hdmi_aud_input_type aud_input_type;
> +       enum hdmi_aud_i2s_fmt aud_i2s_fmt;
> +       enum hdmi_aud_mclk aud_mclk;
> +       enum hdmi_aud_channel_type aud_input_chan_type;
> +       struct hdmi_codec_params codec_params;
> +};
> +
> +struct mtk_hdmi {
> +       struct drm_bridge bridge;
> +       struct device *dev;
> +       const struct mtk_hdmi_conf *conf;
> +       struct phy *phy;
> +       struct i2c_adapter *ddc_adpt;
> +       struct clk **clk;
> +       struct drm_display_mode mode;
> +       bool dvi_mode;
> +       struct regmap *sys_regmap;
> +       unsigned int sys_offset;
> +       struct regmap *regs;
> +
> +       bool powered;
> +       bool enabled;
> +       unsigned int irq;
> +       enum hdmi_hpd_state hpd;
> +
> +       /* Audio */
> +       struct platform_device *audio_pdev;
> +       struct hdmi_audio_param aud_param;
> +       bool audio_enable;
> +
> +       struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
> +       struct mutex update_plugged_status_lock;
> +       struct device *cec_dev;
> +       struct device *codec_dev;
> +       hdmi_codec_plugged_cb plugged_cb;
> +       struct drm_bridge *next_bridge;
> +};
> +
> +struct mtk_hdmi_ver_conf {
> +       const struct drm_bridge_funcs *bridge_funcs;
> +       const struct hdmi_codec_ops *codec_ops;
> +       const char * const *mtk_hdmi_clock_names;
> +       int num_clocks;
> +       bool hdr_support;
> +};
> +
> +struct mtk_hdmi_conf {
> +       const struct mtk_hdmi_ver_conf *ver_conf;
> +       bool tz_disabled;
> +       bool cea_modes_only;
> +       unsigned long max_mode_clock;
> +};
> +
> +static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
> +{
> +       return container_of(b, struct mtk_hdmi, bridge);
> +}
> +
> +int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len);
> +void mtk_hdmi_audio_set_plugged_cb(struct mtk_hdmi *hdmi, hdmi_codec_plugged_cb fn,
> +                                  struct device *codec_dev);
> +int mtk_hdmi_audio_params(struct mtk_hdmi *hdmi, struct hdmi_codec_daifmt *daifmt,
> +                         struct hdmi_codec_params *params);
> +int mtk_hdmi_get_ncts(unsigned int sample_rate, unsigned int clock,
> +                     unsigned int *n, unsigned int *cts);
> +bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> +                               const struct drm_display_mode *mode,
> +                               struct drm_display_mode *adjusted_mode);
> +void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
> +                             const struct drm_display_mode *mode,
> +                             const struct drm_display_mode *adjusted_mode);
> +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev);
> +int mtk_drm_hdmi_probe(struct platform_device *pdev);
> +int mtk_drm_hdmi_remove(struct platform_device *pdev);
> +
> +#endif /* _MTK_HDMI_COMMON_H */
> --
> 2.47.0
> 

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
> +{
> +       const struct mtk_hdmi_ver_conf *ver_conf;
> +       struct device *dev = &pdev->dev;
> +       struct mtk_hdmi *hdmi;
> +       int ret;
> +
> +       hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
> +       if (!hdmi)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->dev = dev;
> +       hdmi->conf = of_device_get_match_data(dev);
> +       ver_conf = hdmi->conf->ver_conf;
> +
> +       hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
> +       if (!hdmi->clk)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->phy = devm_phy_get(dev, "hdmi");
> +       if (IS_ERR(hdmi->phy))
> +               return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
> +
> +       ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
> +                                     ver_conf->num_clocks);
> +       if (ret)
> +               return ERR_PTR(ret);
> +
> +       platform_set_drvdata(pdev, hdmi);
> +
> +       ret = mtk_hdmi_register_audio_driver(dev);
> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");
> +
> +       hdmi->bridge.funcs = ver_conf->bridge_funcs;
> +       hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
> +       hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> +       hdmi->bridge.of_node = pdev->dev.of_node;
> +
> +       ret = devm_drm_bridge_add(dev, &hdmi->bridge);

You change drm_bridge_add() to devm_drm_bridge_add(). If this is necessary, separate this to a refinement patch.

Regards,
CK

> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
> +
> +       return hdmi;
> +}
> +

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +enum hdmi_hpd_state {

This is used only by v2. So move to patch [15/15].

Regards,
CK

> +       HDMI_PLUG_OUT = 0,
> +       HDMI_PLUG_IN_AND_SINK_POWER_ON,
> +       HDMI_PLUG_IN_ONLY,
> +};
> +
> 2.47.0
> 

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static int mtk_hdmi_probe(struct platform_device *pdev)
> +{
> +       struct mtk_hdmi *hdmi;
> 
> -       ret = mtk_hdmi_clk_enable_audio(hdmi);
> -       if (ret) {
> -               drm_bridge_remove(&hdmi->bridge);
> -               return dev_err_probe(dev, ret,
> -                                    "Failed to enable audio clocks\n");
> -       }
> +       hdmi = mtk_hdmi_common_probe(pdev);
> +       if (IS_ERR(hdmi))
> +               return PTR_ERR(hdmi);

In original v1 driver, update_plugged_status_lock is init in probe.
I can not find the init in this patch.
It's better that moving common code seldom change the order in a function,
so you could easily to compare that moving does not change any thing.
In this patch, you not only moving code, but also change the order in a function,
so it's not easy to find something lost.

That's why I like you to separate this patch into two patches. One is adding version config and the other one is moving common code.
When I review the moving common code part, I would like a function before moving is almost same as after moving,
so it's easy to find out something lost.

Regards,
CK

> 
> -       return 0;
> +       return mtk_hdmi_clk_enable_audio(hdmi);
>  }
> 

[snip]

> +struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
> +{
> +       const struct mtk_hdmi_ver_conf *ver_conf;
> +       struct device *dev = &pdev->dev;
> +       struct mtk_hdmi *hdmi;
> +       int ret;
> +
> +       hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
> +       if (!hdmi)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->dev = dev;
> +       hdmi->conf = of_device_get_match_data(dev);
> +       ver_conf = hdmi->conf->ver_conf;
> +
> +       hdmi->clk = devm_kcalloc(dev, ver_conf->num_clocks, sizeof(*hdmi->clk), GFP_KERNEL);
> +       if (!hdmi->clk)
> +               return ERR_PTR(-ENOMEM);
> +
> +       hdmi->phy = devm_phy_get(dev, "hdmi");
> +       if (IS_ERR(hdmi->phy))
> +               return dev_err_cast_probe(dev, hdmi->phy, "Failed to get HDMI PHY\n");
> +
> +       ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev, ver_conf->mtk_hdmi_clock_names,
> +                                     ver_conf->num_clocks);
> +       if (ret)
> +               return ERR_PTR(ret);
> +
> +       platform_set_drvdata(pdev, hdmi);
> +
> +       ret = mtk_hdmi_register_audio_driver(dev);
> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Cannot register HDMI Audio driver\n");
> +
> +       hdmi->bridge.funcs = ver_conf->bridge_funcs;
> +       hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
> +       hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> +       hdmi->bridge.of_node = pdev->dev.of_node;
> +
> +       ret = devm_drm_bridge_add(dev, &hdmi->bridge);
> +       if (ret)
> +               return dev_err_ptr_probe(dev, ret, "Failed to add bridge\n");
> +
> +       return hdmi;
> +}
> +

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static void mtk_hdmi_unregister_audio_driver(void *data)
> +{
> +       platform_device_unregister(data);
> +}
> +
> +static int mtk_hdmi_register_audio_driver(struct device *dev)
> +{
> +       struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +       struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> +       struct hdmi_codec_pdata codec_data = {
> +               .i2s = 1,
> +               .max_i2s_channels = 2,
> +               .data = hdmi,
> +               .ops = hdmi->conf->ver_conf->codec_ops
> +       };
> +       int ret;
> +
> +       aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
> +       aud_param->aud_sample_size = HDMI_AUDIO_SAMPLE_SIZE_16;
> +       aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
> +       aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
> +       aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
> +       aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;

You squash mtk_hdmi_outout_init() into this function.
I'm not sure this is necessary or not.
If it's necessary, I would like this modification to be a separate patch and it's easier to review.
I want this patch is simply moving common code.

And this patch remove hdmi->csp and it is really not necessary.
Let removing hdmi->csp be a clean up patch.

> +
> +       hdmi->audio_pdev = platform_device_register_data(dev,
> +                                                        HDMI_CODEC_DRV_NAME,
> +                                                        PLATFORM_DEVID_AUTO,
> +                                                        &codec_data,
> +                                                        sizeof(codec_data));
> +       if (IS_ERR(hdmi->audio_pdev))
> +               return PTR_ERR(hdmi->audio_pdev);
> +
> +       ret = devm_add_action_or_reset(dev, mtk_hdmi_unregister_audio_driver,
> +                                      hdmi->audio_pdev);

This adding action or reset is other than moving common function.
So separate this to a refinement patch.

Regards,
CK

> +       if (ret) {
> +               platform_device_unregister(hdmi->audio_pdev);
> +               return ret;
> +       }
> +
> +       return 0;
> +}
> +

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> -struct mtk_hdmi {
> -       struct drm_bridge bridge;
> -       struct drm_bridge *next_bridge;
> -       struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
> -       struct device *dev;
> -       const struct mtk_hdmi_conf *conf;
> -       struct phy *phy;
> -       struct device *cec_dev;
> -       struct i2c_adapter *ddc_adpt;
> -       struct clk *clk[MTK_HDMI_CLK_COUNT];
> -       struct drm_display_mode mode;
> -       bool dvi_mode;
> -       u32 min_clock;
> -       u32 max_clock;
> -       u32 max_hdisplay;
> -       u32 max_vdisplay;
> -       u32 ibias;
> -       u32 ibias_up;
> -       struct regmap *sys_regmap;
> -       unsigned int sys_offset;
> -       struct regmap *regs;
> -       enum hdmi_colorspace csp;
> -       struct hdmi_audio_param aud_param;
> -       bool audio_enable;
> -       bool powered;
> -       bool enabled;
> -       hdmi_codec_plugged_cb plugged_cb;
> -       struct device *codec_dev;
> -       struct mutex update_plugged_status_lock;
> };
> 
> +struct mtk_hdmi {
> +       struct drm_bridge bridge;
> +       struct device *dev;
> +       const struct mtk_hdmi_conf *conf;
> +       struct phy *phy;
> +       struct i2c_adapter *ddc_adpt;
> +       struct clk **clk;
> +       struct drm_display_mode mode;
> +       bool dvi_mode;
> +       struct regmap *sys_regmap;
> +       unsigned int sys_offset;
> +       struct regmap *regs;
> +
> +       bool powered;
> +       bool enabled;
> +       unsigned int irq;

You add something which is used in v2 but not in v1.
Move these to the v2 patch, or separate them to a precondition patch of v2.

> +       enum hdmi_hpd_state hpd;
> +
> +       /* Audio */
> +       struct platform_device *audio_pdev;
> +       struct hdmi_audio_param aud_param;
> +       bool audio_enable;
> +
> +       struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
> +       struct mutex update_plugged_status_lock;
> +       struct device *cec_dev;
> +       struct device *codec_dev;
> +       hdmi_codec_plugged_cb plugged_cb;
> +       struct drm_bridge *next_bridge;

I don't know why you reorder these.
If it's necessary, separate these reorder to a refinement patch.

Regards,
CK

> +};
> +

Re: [PATCH v2 12/15] drm/mediatek: mtk_hdmi: Split driver and add common probe function

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding a new driver for the HDMI TX v2 IP,
> split out the functions that will be common between the already
> present mtk_hdmi (v1) driver and the new one.
> 
> Since the probe flow for both drivers is 90% similar, add a common
> probe function that will be called from each driver's .probe()
> callback, avoiding lots of code duplication.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

>  static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
> @@ -1143,10 +886,11 @@ static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
>  static enum drm_connector_status
>  mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
>  {
> -       bool connected;
> +       bool connected = true;
> 
>         mutex_lock(&hdmi->update_plugged_status_lock);
> -       connected = mtk_cec_hpd_high(hdmi->cec_dev);
> +       if (hdmi->cec_dev)

Only v1 would call mtk_hdmi_update_plugged_status() and v1 should has hdmi->cec_dev,
so this checking is redundant.

> +               connected = mtk_cec_hpd_high(hdmi->cec_dev);
>         if (hdmi->plugged_cb && hdmi->codec_dev)
>                 hdmi->plugged_cb(hdmi->codec_dev, connected);
>         mutex_unlock(&hdmi->update_plugged_status_lock);
> @@ -1254,18 +998,12 @@ static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
>                         return ret;
>         }
> 
> -       mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
> +       if (hdmi->cec_dev)

Ditto.

Regards,
CK

> +               mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
> 
>         return 0;
>  }
> 

[PATCH v2 13/15] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge

[AngeloGioacchino Del Regno]

In preparation for adding the new HDMI TX v2 IP driver, assign the
pointer to the DDC adapter to struct drm_bridge during probe.

This commit brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 1b23ab6969ec..4f708b04f5e8 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -410,6 +410,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
 	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
 	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 	hdmi->bridge.of_node = pdev->dev.of_node;
+	hdmi->bridge.ddc = hdmi->ddc_adpt;
 
 	ret = devm_drm_bridge_add(dev, &hdmi->bridge);
 	if (ret)
-- 
2.47.0

Re: [PATCH v2 13/15] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding the new HDMI TX v2 IP driver, assign the
> pointer to the DDC adapter to struct drm_bridge during probe.
> 
> This commit brings no functional changes.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> index 1b23ab6969ec..4f708b04f5e8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> @@ -410,6 +410,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
>         hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         hdmi->bridge.of_node = pdev->dev.of_node;
> +       hdmi->bridge.ddc = hdmi->ddc_adpt;

I don't know why only v2 driver need to assign this?
Could you point out the code where access this value?

Regards,
CK

> 
>         ret = devm_drm_bridge_add(dev, &hdmi->bridge);
>         if (ret)
> --
> 2.47.0
> 

Re: [PATCH v2 13/15] drm/mediatek: mtk_hdmi_common: Assign DDC adapter pointer to bridge

[AngeloGioacchino Del Regno]

Il 09/12/24 09:17, CK Hu (胡俊光) ha scritto:
> Hi, Angelo:
> 
> On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> In preparation for adding the new HDMI TX v2 IP driver, assign the
>> pointer to the DDC adapter to struct drm_bridge during probe.
>>
>> This commit brings no functional changes.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> index 1b23ab6969ec..4f708b04f5e8 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> @@ -410,6 +410,7 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
>>          hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
>>          hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>>          hdmi->bridge.of_node = pdev->dev.of_node;
>> +       hdmi->bridge.ddc = hdmi->ddc_adpt;
> 
> I don't know why only v2 driver need to assign this?
> Could you point out the code where access this value?
> 

v2 uses hdmi helpers, which make use of bridge->ddc.
mtk_hdmi_v2_bridge_edid_read() calls drm_edid_read().

drm_edid.c -> drm_edid_read()
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/drivers/gpu/drm/drm_edid.c?h=next-20241209#n2704

...while v1 feeds the (internal) ddc pointer to drm_edid_read_ddc() instead.

Cheers,
Angelo

> Regards,
> CK
> 
>>
>>          ret = devm_drm_bridge_add(dev, &hdmi->bridge);
>>          if (ret)
>> --
>> 2.47.0
>>
> 

[PATCH v2 14/15] drm/mediatek: mtk_hdmi_common: Add OP_HDMI, vendor and product strings

[AngeloGioacchino Del Regno]

In preparation for adding the HDMI TX v2 driver, and to allow
a future modernization of the HDMI v1 one, perform changes
that enable the usage of the HDMI Helpers provided by DRM.

Check if the HDMI driver provides the function pointers to
hdmi_{clear,write}_infoframe used by the HDMI Helper API and,
if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops,
enabling the drm API to register the bridge as HDMI and to use
the HDMI Helper functions.

Moreover, as part of data exclusively used (in the context of
HDMI bridges) by the helpers, assign the vendor "MediaTek" and
product "On-Chip HDMI" strings to the drm_bridge struct.

If the hdmi_{write,clear}_infoframe pointers are not assigned,
vendor and product strings and HDMI helpers will not be used,
hence this commit brings no functional changes to drivers that
have not been refactored to use the new helpers.

This also means that, in the current state, there is effectively
no functional change to mtk_hdmi and its other components.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 4f708b04f5e8..0f60842462b0 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -408,9 +408,16 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
 
 	hdmi->bridge.funcs = ver_conf->bridge_funcs;
 	hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
+
+	if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
+	    ver_conf->bridge_funcs->hdmi_clear_infoframe)
+		hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
+
 	hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
 	hdmi->bridge.of_node = pdev->dev.of_node;
 	hdmi->bridge.ddc = hdmi->ddc_adpt;
+	hdmi->bridge.vendor = "MediaTek";
+	hdmi->bridge.product = "On-Chip HDMI";
 
 	ret = devm_drm_bridge_add(dev, &hdmi->bridge);
 	if (ret)
-- 
2.47.0

Re: [PATCH v2 14/15] drm/mediatek: mtk_hdmi_common: Add OP_HDMI, vendor and product strings

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> In preparation for adding the HDMI TX v2 driver, and to allow
> a future modernization of the HDMI v1 one, perform changes
> that enable the usage of the HDMI Helpers provided by DRM.
> 
> Check if the HDMI driver provides the function pointers to
> hdmi_{clear,write}_infoframe used by the HDMI Helper API and,
> if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops,
> enabling the drm API to register the bridge as HDMI and to use
> the HDMI Helper functions.
> 
> Moreover, as part of data exclusively used (in the context of
> HDMI bridges) by the helpers, assign the vendor "MediaTek" and
> product "On-Chip HDMI" strings to the drm_bridge struct.
> 
> If the hdmi_{write,clear}_infoframe pointers are not assigned,
> vendor and product strings and HDMI helpers will not be used,
> hence this commit brings no functional changes to drivers that
> have not been refactored to use the new helpers.
> 
> This also means that, in the current state, there is effectively
> no functional change to mtk_hdmi and its other components.

OP_HDMI is for v2.
vendor and product strings is for both v1 and v2.
So separate this patch to two patches.

Regards,
CK

> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> index 4f708b04f5e8..0f60842462b0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> @@ -408,9 +408,16 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
> 
>         hdmi->bridge.funcs = ver_conf->bridge_funcs;
>         hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
> +
> +       if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
> +           ver_conf->bridge_funcs->hdmi_clear_infoframe)
> +               hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
> +
>         hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>         hdmi->bridge.of_node = pdev->dev.of_node;
>         hdmi->bridge.ddc = hdmi->ddc_adpt;
> +       hdmi->bridge.vendor = "MediaTek";
> +       hdmi->bridge.product = "On-Chip HDMI";
> 
>         ret = devm_drm_bridge_add(dev, &hdmi->bridge);
>         if (ret)
> --
> 2.47.0
> 

Re: [PATCH v2 14/15] drm/mediatek: mtk_hdmi_common: Add OP_HDMI, vendor and product strings

[AngeloGioacchino Del Regno]

Il 09/12/24 10:09, CK Hu (胡俊光) ha scritto:
> Hi, Angelo:
> 
> On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> In preparation for adding the HDMI TX v2 driver, and to allow
>> a future modernization of the HDMI v1 one, perform changes
>> that enable the usage of the HDMI Helpers provided by DRM.
>>
>> Check if the HDMI driver provides the function pointers to
>> hdmi_{clear,write}_infoframe used by the HDMI Helper API and,
>> if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops,
>> enabling the drm API to register the bridge as HDMI and to use
>> the HDMI Helper functions.
>>
>> Moreover, as part of data exclusively used (in the context of
>> HDMI bridges) by the helpers, assign the vendor "MediaTek" and
>> product "On-Chip HDMI" strings to the drm_bridge struct.
>>
>> If the hdmi_{write,clear}_infoframe pointers are not assigned,
>> vendor and product strings and HDMI helpers will not be used,
>> hence this commit brings no functional changes to drivers that
>> have not been refactored to use the new helpers.
>>
>> This also means that, in the current state, there is effectively
>> no functional change to mtk_hdmi and its other components.
> 
> OP_HDMI is for v2.
> vendor and product strings is for both v1 and v2.
> So separate this patch to two patches.
> 

They're both for v2, because only v2 uses the HDMI helpers, while v1 does not.

Cheers,
Angelo

> Regards,
> CK
> 
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> index 4f708b04f5e8..0f60842462b0 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
>> @@ -408,9 +408,16 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
>>
>>          hdmi->bridge.funcs = ver_conf->bridge_funcs;
>>          hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
>> +
>> +       if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
>> +           ver_conf->bridge_funcs->hdmi_clear_infoframe)
>> +               hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
>> +
>>          hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
>>          hdmi->bridge.of_node = pdev->dev.of_node;
>>          hdmi->bridge.ddc = hdmi->ddc_adpt;
>> +       hdmi->bridge.vendor = "MediaTek";
>> +       hdmi->bridge.product = "On-Chip HDMI";
>>
>>          ret = devm_drm_bridge_add(dev, &hdmi->bridge);
>>          if (ret)
>> --
>> 2.47.0
>>
> 

Re: [PATCH v2 14/15] drm/mediatek: mtk_hdmi_common: Add OP_HDMI, vendor and product strings

[CK Hu (胡俊光)]

On Mon, 2024-12-09 at 10:56 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Il 09/12/24 10:09, CK Hu (胡俊光) ha scritto:
> > Hi, Angelo:
> > 
> > On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> > > External email : Please do not click links or open attachments until you have verified the sender or the content.
> > > 
> > > 
> > > In preparation for adding the HDMI TX v2 driver, and to allow
> > > a future modernization of the HDMI v1 one, perform changes
> > > that enable the usage of the HDMI Helpers provided by DRM.
> > > 
> > > Check if the HDMI driver provides the function pointers to
> > > hdmi_{clear,write}_infoframe used by the HDMI Helper API and,
> > > if present, add DRM_BRIDGE_OP_HDMI to the drm_bridge ops,
> > > enabling the drm API to register the bridge as HDMI and to use
> > > the HDMI Helper functions.
> > > 
> > > Moreover, as part of data exclusively used (in the context of
> > > HDMI bridges) by the helpers, assign the vendor "MediaTek" and
> > > product "On-Chip HDMI" strings to the drm_bridge struct.
> > > 
> > > If the hdmi_{write,clear}_infoframe pointers are not assigned,
> > > vendor and product strings and HDMI helpers will not be used,
> > > hence this commit brings no functional changes to drivers that
> > > have not been refactored to use the new helpers.
> > > 
> > > This also means that, in the current state, there is effectively
> > > no functional change to mtk_hdmi and its other components.
> > 
> > OP_HDMI is for v2.
> > vendor and product strings is for both v1 and v2.
> > So separate this patch to two patches.
> > 
> 
> They're both for v2, because only v2 uses the HDMI helpers, while v1 does not.

Sorry, these two is required by DRM_BRIDGE_OP_HDMI.

  /**
         * @vendor: Vendor of the product to be used for the SPD InfoFrame
         * generation. This is required if @DRM_BRIDGE_OP_HDMI is set.
         */
        const char *vendor;
 
        /**
         * @product: Name of the product to be used for the SPD InfoFrame
         * generation. This is required if @DRM_BRIDGE_OP_HDMI is set.
         */
        const char *product;

So,

Reviewed-by: CK Hu <ck.hu@mediatek.com>

> 
> Cheers,
> Angelo
> 
> > Regards,
> > CK
> > 
> > > 
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > ---
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_common.c | 7 +++++++
> > >   1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> > > index 4f708b04f5e8..0f60842462b0 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> > > @@ -408,9 +408,16 @@ struct mtk_hdmi *mtk_hdmi_common_probe(struct platform_device *pdev)
> > > 
> > >          hdmi->bridge.funcs = ver_conf->bridge_funcs;
> > >          hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
> > > +
> > > +       if (ver_conf->bridge_funcs->hdmi_write_infoframe &&
> > > +           ver_conf->bridge_funcs->hdmi_clear_infoframe)
> > > +               hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI;
> > > +
> > >          hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
> > >          hdmi->bridge.of_node = pdev->dev.of_node;
> > >          hdmi->bridge.ddc = hdmi->ddc_adpt;
> > > +       hdmi->bridge.vendor = "MediaTek";
> > > +       hdmi->bridge.product = "On-Chip HDMI";
> > > 
> > >          ret = devm_drm_bridge_add(dev, &hdmi->bridge);
> > >          if (ret)
> > > --
> > > 2.47.0
> > > 
> > 
> 
> 

[PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
found in MediaTek's MT8195, MT8188 SoC and their variants, and
including support for display modes up to 4k60 and for HDMI
Audio, as per the HDMI 2.0 spec.

HDCP and CEC functionalities are also supported by this hardware,
but are not included in this commit and that also poses a slight
difference between the V2 and V1 controllers in how they handle
Hotplug Detection (HPD).

While the v1 controller was using the CEC controller to check
HDMI cable connection and disconnection, in this driver the v2
one does not.

This is due to the fact that on parts with v2 designs, like the
MT8195 SoC, there is one CEC controller shared between the HDMI
Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
adding support to use the CEC HW to wake up the HDMI controllers
it is necessary to have support for one TX, one RX *and* for both
at the same time.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/Kconfig            |    8 +
 drivers/gpu/drm/mediatek/Makefile           |    4 +
 drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
 drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
 7 files changed, 2172 insertions(+)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
 create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c

diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index 73459f07dae3..8127576be1eb 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -50,3 +50,11 @@ config DRM_MEDIATEK_HDMI
 	select PHY_MTK_HDMI
 	help
 	  DRM/KMS HDMI driver for Mediatek SoCs
+
+config DRM_MEDIATEK_HDMI_V2
+	tristate "DRM HDMI v2 IP support for MediaTek SoCs"
+	depends on DRM_MEDIATEK
+	select DRM_MEDIATEK_HDMI_COMMON
+	select PHY_MTK_HDMI
+	help
+	  DRM/KMS HDMI driver for MediaTek SoCs with HDMIv2 IP
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 8973d7ba37d3..928a850f707f 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -25,7 +25,11 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
 			  mtk_hdmi.o \
 			  mtk_hdmi_ddc.o
 
+mediatek-drm-hdmi-v2-objs := mtk_hdmi_ddc_v2.o \
+			     mtk_hdmi_v2.o
+
 obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
 obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
+obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mediatek-drm-hdmi-v2.o
 
 obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
index 0f60842462b0..90f603f34cde 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
@@ -295,6 +295,11 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device
 	if (IS_ERR(hdmi->regs))
 		return PTR_ERR(hdmi->regs);
 
+	/* Populate HDMI sub-devices if present */
+	ret = devm_of_platform_populate(&pdev->dev);
+	if (ret)
+		return ret;
+
 	remote = of_graph_get_remote_node(np, 1, 0);
 	if (!remote)
 		return dev_err_probe(dev, -EINVAL, "Cannot find HDMI input port\n");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
index 15121e8548f3..8cfff39b0d90 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
@@ -176,6 +176,7 @@ struct mtk_hdmi_conf {
 	bool tz_disabled;
 	bool cea_modes_only;
 	unsigned long max_mode_clock;
+	u32 reg_hdmi_tx_cfg;
 };
 
 static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
new file mode 100644
index 000000000000..297b8b6f668c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek HDMI v2 Display Data Channel Driver
+ *
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/semaphore.h>
+#include <linux/slab.h>
+#include <linux/time.h>
+#include <linux/types.h>
+
+#include <drm/drm_edid.h>
+
+#include "mtk_hdmi_common.h"
+#include "mtk_hdmi_regs_v2.h"
+
+#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
+#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
+#define SI2C_ADDR_READ 0xf4
+#define SCDC_I2C_SLAVE_ADDRESS 0x54
+
+struct mtk_hdmi_ddc {
+	struct device *dev;
+	void __iomem *regs;
+	struct clk *clk;
+	struct i2c_adapter adap;
+	/* Serialize read/write operations */
+	struct mutex mtx;
+};
+
+static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
+{
+	u32 val;
+
+	regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
+	if (val & DDC_I2C_BUS_LOW) {
+		regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
+				   FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
+		usleep_range(250, 300);
+	}
+
+	if (val & DDC_I2C_NO_ACK) {
+		u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
+
+		regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
+		regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
+		regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
+	}
+
+	if (val & DDC_I2C_NO_ACK)
+		return -EIO;
+
+	return 0;
+}
+
+static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
+			  u16 offset_id, u8 wr_data)
+{
+	u32 val;
+	int ret;
+
+	/* If down, rise bus for write operation */
+	mtk_ddc_check_and_rise_low_bus(ddc);
+
+	regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
+			   FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
+
+	regmap_write(ddc->regs, SI2C_CTRL,
+		     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+		     FIELD_PREP(SI2C_WDATA, wr_data) |
+		     SI2C_WR);
+
+	regmap_write(ddc->regs, DDC_CTRL,
+		     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
+		     FIELD_PREP(DDC_CTRL_DIN_CNT, 1) |
+		     FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
+		     FIELD_PREP(DDC_CTRL_ADDR, addr_id));
+	usleep_range(1000, 1250);
+
+	ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
+				       !(val & DDC_I2C_IN_PROG), 500, 1000);
+	if (ret) {
+		dev_err(ddc->dev, "DDC I2C write timeout\n");
+		return ret;
+	}
+
+	/* The I2C bus might be down after WR operation: rise it again */
+	ret = mtk_ddc_check_and_rise_low_bus(ddc);
+	if (ret) {
+		dev_err(ddc->dev, "Error during write operation: No ACK\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 dly_cnt, u16 uc_dev,
+			      u8 addr, u8 *puc_value, u16 data_cnt)
+{
+	u16 i, loop_counter, temp_length, uc_idx;
+	u32 rem, uc_read_count, val;
+	int ret;
+
+	if (!puc_value || !data_cnt || !dly_cnt) {
+		dev_err(ddc->dev, "Bad DDCM read request\n");
+		return 0;
+	}
+
+	mtk_ddc_check_and_rise_low_bus(ddc);
+
+	regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
+			   FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
+
+	if (data_cnt >= 16) {
+		temp_length = 16;
+		loop_counter = data_cnt;
+
+		rem = do_div(loop_counter, temp_length);
+		if (rem)
+			loop_counter++;
+	} else {
+		temp_length = data_cnt;
+		loop_counter = 1;
+	}
+
+	if (uc_dev >= DDC_ADDR && dly_cnt < DDC2_DLY_CNT_EDID)
+		dly_cnt = DDC2_DLY_CNT_EDID;
+
+	regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
+			   FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
+
+	for (i = 0; i < loop_counter; i++) {
+		rem = data_cnt % 16;
+
+		if (i > 0 && i == (loop_counter - 1) && rem)
+			temp_length = rem;
+
+		/* 0x51 - 0x53: Flow control */
+		if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
+			regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
+					   FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
+
+			regmap_write(ddc->regs, DDC_CTRL,
+				     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
+				     FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
+				     FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
+				     FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
+		} else {
+			u16 offset;
+
+			if (addr != 0x43)
+				offset = i * 16;
+			else
+				offset = 0;
+
+			regmap_write(ddc->regs, DDC_CTRL,
+				     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
+				     FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
+				     FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
+				     FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
+		}
+		usleep_range(5000, 5500);
+
+		ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
+					       !(val & DDC_I2C_IN_PROG), 1000,
+					       500 * (temp_length + 5));
+		if (ret) {
+			dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
+			return ret;
+		}
+
+		ret = mtk_ddc_check_and_rise_low_bus(ddc);
+		if (ret) {
+			dev_err(ddc->dev, "Error during read operation: No ACK\n");
+			return ret;
+		}
+
+		for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
+			unsigned int read_idx = i * 16 + uc_idx;
+
+			regmap_write(ddc->regs, SI2C_CTRL,
+				     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+				     SI2C_RD);
+
+			regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
+			puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
+
+			regmap_write(ddc->regs, SI2C_CTRL,
+				     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
+				     SI2C_CONFIRM_READ);
+
+			/*
+			 * If HDMI IP gets reset during EDID read, DDC read
+			 * operation will fail and its delay counter will be
+			 * reset to 400.
+			 */
+			regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
+			if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
+				return 0;
+
+			uc_read_count = read_idx + 1;
+		}
+	}
+	if (uc_read_count > U8_MAX)
+		dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
+
+	return uc_read_count;
+}
+
+static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
+				     u8 data_addr, u16 data_cnt, u8 *pr_data)
+{
+	int read_data_cnt;
+	u16 req_data_cnt;
+
+	if (!pr_data || !data_cnt)
+		return -EINVAL;
+
+	req_data_cnt = U8_MAX - data_addr + 1;
+	if (req_data_cnt > data_cnt)
+		req_data_cnt = data_cnt;
+
+	mutex_lock(&ddc->mtx);
+
+	regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
+
+	read_data_cnt = mtk_ddcm_read_hdmi(ddc, DDC2_DLY_CNT, b_dev, data_addr,
+					   pr_data, req_data_cnt);
+
+	mutex_unlock(&ddc->mtx);
+
+	if (read_data_cnt < 0)
+		return read_data_cnt;
+	else if (read_data_cnt != req_data_cnt)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
+				      u8 data_addr, u16 data_cnt, u8 *pr_data)
+{
+	int i = 0, ret;
+
+	mutex_lock(&ddc->mtx);
+
+	regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
+	do {
+		ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data[i]);
+		if (ret)
+			break;
+	} while (++i < data_cnt);
+
+	mutex_unlock(&ddc->mtx);
+
+	return ret;
+}
+
+static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
+{
+	struct mtk_hdmi_ddc *ddc;
+	u8 offset = 0;
+	int i, ret;
+
+	if (!adapter || !adapter->algo_data || !msgs)
+		return -EINVAL;
+
+	ddc = adapter->algo_data;
+
+	for (i = 0; i < num; i++) {
+		struct i2c_msg *msg = &msgs[i];
+
+		if (!msg->buf) {
+			pr_err("XFER: No message buffer\n");
+			return -EINVAL;
+		}
+
+		if (msg->flags & I2C_M_RD) {
+			/*
+			 * The underlying DDC hardware always issues a write request
+			 * that assigns the read offset as part of the read operation,
+			 * therefore, use the `offset` value assigned in the previous
+			 * write request from drm_edid
+			 */
+			ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
+							msg->len, &msg->buf[0]);
+			if (ret)
+				return ret;
+		} else {
+			ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
+							 msg->len - 1, &msg->buf[1]);
+			if (ret)
+				return ret;
+
+			/*
+			 * Store the offset value requested by drm_edid or by
+			 * scdc to use in subsequent read requests.
+			 */
+			if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
+			    msg->len == 1) {
+				offset = msg->buf[0];
+			}
+		}
+	}
+
+	return i;
+}
+
+static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
+	.master_xfer = mtk_hdmi_ddc_v2_xfer,
+	.functionality = mtk_hdmi_ddc_v2_func,
+};
+
+static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct mtk_hdmi_ddc *ddc;
+	int ret;
+
+	ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
+	if (!ddc)
+		return -ENOMEM;
+
+	ddc->dev = dev;
+	ddc->regs = device_node_to_regmap(dev->parent->of_node);
+	if (IS_ERR_OR_NULL(ddc->regs))
+		return dev_err_probe(dev,
+				     IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
+				     "Cannot get regmap\n");
+
+	ddc->clk = devm_clk_get_enabled(dev, NULL);
+	if (IS_ERR(ddc->clk))
+		return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
+
+	mutex_init(&ddc->mtx);
+
+	strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
+	ddc->adap.owner = THIS_MODULE;
+	ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
+	ddc->adap.retries = 3;
+	ddc->adap.dev.of_node = dev->of_node;
+	ddc->adap.algo_data = ddc;
+	ddc->adap.dev.parent = &pdev->dev;
+
+	ret = devm_pm_runtime_enable(&pdev->dev);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
+
+	pm_runtime_get_sync(dev);
+
+	ret = devm_i2c_add_adapter(dev, &ddc->adap);
+	if (ret < 0)
+		return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
+
+	platform_set_drvdata(pdev, ddc);
+	return 0;
+}
+
+static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
+	{ .compatible = "mediatek,mt8195-hdmi-ddc" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match)
+
+struct platform_driver mtk_hdmi_ddc_v2_driver = {
+	.probe = mtk_hdmi_ddc_v2_probe,
+	.driver = {
+		.name = "mediatek-hdmi-ddc-v2",
+		.of_match_table = mtk_hdmi_ddc_v2_match,
+	},
+};
+module_platform_driver(mtk_hdmi_ddc_v2_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
+MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
new file mode 100644
index 000000000000..521b35c7e14d
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2021 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef _MTK_HDMI_REGS_H
+#define _MTK_HDMI_REGS_H
+
+/* HDMI_TOP Config */
+#define TOP_CFG00			0x000
+#define  HDMI2_ON			BIT(2)
+#define  HDMI_MODE_HDMI			BIT(3)
+#define  SCR_ON				BIT(4)
+#define  TMDS_PACK_MODE			GENMASK(9, 8)
+#define   TMDS_PACK_MODE_8BPP		0
+#define   TMDS_PACK_MODE_10BPP		1
+#define   TMDS_PACK_MODE_12BPP		2
+#define   TMDS_PACK_MODE_16BPP		3
+#define  DEEPCOLOR_PKT_EN		BIT(12)
+#define  HDMI_ABIST_VIDEO_FORMAT	GENMASK(21, 16)
+#define  HDMI_ABIST_ENABLE		BIT(31)
+#define TOP_CFG01 0x004
+#define  CP_SET_MUTE_EN			BIT(0)
+#define  CP_CLR_MUTE_EN			BIT(1)
+#define  NULL_PKT_EN			BIT(2)
+#define  NULL_PKT_VSYNC_HIGH_EN		BIT(3)
+
+/* HDMI_TOP Audio: Channel Mapping */
+#define TOP_AUD_MAP			0x00c
+#define  SD0_MAP			GENMASK(2, 0)
+#define  SD1_MAP			GENMASK(6, 4)
+#define  SD2_MAP			GENMASK(10, 8)
+#define  SD3_MAP			GENMASK(14, 12)
+#define  SD4_MAP			GENMASK(18, 16)
+#define  SD5_MAP			GENMASK(22, 20)
+#define  SD6_MAP			GENMASK(26, 24)
+#define  SD7_MAP			GENMASK(30, 28)
+
+/* Auxiliary Video Information (AVI) Infoframe */
+#define TOP_AVI_HEADER			0x024
+#define TOP_AVI_PKT00			0x028
+#define TOP_AVI_PKT01			0x02C
+#define TOP_AVI_PKT02			0x030
+#define TOP_AVI_PKT03			0x034
+#define TOP_AVI_PKT04			0x038
+#define TOP_AVI_PKT05			0x03C
+
+/* Audio Interface Infoframe */
+#define TOP_AIF_HEADER			0x040
+#define TOP_AIF_PKT00			0x044
+#define TOP_AIF_PKT01			0x048
+#define TOP_AIF_PKT02			0x04c
+#define TOP_AIF_PKT03			0x050
+
+/* Audio SPDIF Infoframe */
+#define TOP_SPDIF_HEADER		0x054
+#define TOP_SPDIF_PKT00			0x058
+#define TOP_SPDIF_PKT01			0x05c
+#define TOP_SPDIF_PKT02			0x060
+#define TOP_SPDIF_PKT03			0x064
+#define TOP_SPDIF_PKT04			0x068
+#define TOP_SPDIF_PKT05			0x06c
+#define TOP_SPDIF_PKT06			0x070
+#define TOP_SPDIF_PKT07			0x074
+
+/* Infoframes Configuration */
+#define TOP_INFO_EN			0x01c
+#define  AVI_EN				BIT(0)
+#define  SPD_EN				BIT(1)
+#define  AUD_EN				BIT(2)
+#define  CP_EN				BIT(5)
+#define  VSIF_EN			BIT(11)
+#define  AVI_EN_WR			BIT(16)
+#define  SPD_EN_WR			BIT(17)
+#define  AUD_EN_WR			BIT(18)
+#define  CP_EN_WR			BIT(21)
+#define  VSIF_EN_WR			BIT(27)
+#define TOP_INFO_RPT			0x020
+#define  AVI_RPT_EN			BIT(0)
+#define  SPD_RPT_EN			BIT(1)
+#define  AUD_RPT_EN			BIT(2)
+#define  CP_RPT_EN			BIT(5)
+#define  VSIF_RPT_EN			BIT(11)
+
+/* Vendor Specific Infoframe */
+#define TOP_VSIF_HEADER			0x174
+#define TOP_VSIF_PKT00			0x178
+#define TOP_VSIF_PKT01			0x17c
+#define TOP_VSIF_PKT02			0x180
+#define TOP_VSIF_PKT03			0x184
+#define TOP_VSIF_PKT04			0x188
+#define TOP_VSIF_PKT05			0x18c
+#define TOP_VSIF_PKT06			0x190
+#define TOP_VSIF_PKT07			0x194
+
+/* HDMI_TOP Misc */
+#define TOP_MISC_CTLR			0x1a4
+#define  DEEP_COLOR_ADD			BIT(4)
+
+/* Hardware interrupts */
+#define TOP_INT_STA00			0x1a8
+#define TOP_INT_ENABLE00		0x1b0
+#define  HTPLG_R_INT			BIT(0)
+#define  HTPLG_F_INT			BIT(1)
+#define  PORD_R_INT			BIT(2)
+#define  PORD_F_INT			BIT(3)
+#define  HDMI_VSYNC_INT			BIT(4)
+#define  HDMI_AUDIO_INT			BIT(5)
+#define  HDCP2X_RX_REAUTH_REQ_DDCM_INT	BIT(25)
+#define TOP_INT_ENABLE01		0x1b4
+#define TOP_INT_CLR00			0x1b8
+#define TOP_INT_CLR01			0x1bc
+
+
+/* Video Mute */
+#define TOP_VMUTE_CFG1			0x1c8
+#define  REG_VMUTE_EN			BIT(16)
+
+/* HDMI Audio IP */
+#define AIP_CTRL			0x400
+#define  CTS_SW_SEL			BIT(0)
+#define  CTS_REQ_EN			BIT(1)
+#define  MCLK_EN			BIT(2)
+#define  NO_MCLK_CTSGEN_SEL		BIT(3)
+#define  AUD_IN_EN			BIT(8)
+#define  AUD_SEL_OWRT			BIT(9)
+#define  SPDIF_EN			BIT(13)
+#define  HBRA_ON			BIT(14)
+#define  DSD_EN				BIT(15)
+#define  I2S_EN				GENMASK(19, 16)
+#define  HBR_FROM_SPDIF			BIT(20)
+#define  CTS_CAL_N4			BIT(23)
+#define  SPDIF_INTERNAL_MODULE		BIT(24)
+#define AIP_N_VAL			0x404
+#define AIP_CTS_SVAL			0x408
+#define AIP_SPDIF_CTRL			0x40c
+#define  WR_1UI_LOCK			BIT(0)
+#define  FS_OVERRIDE_WRITE		BIT(1)
+#define  WR_2UI_LOCK			BIT(2)
+#define  MAX_1UI_WRITE			GENMASK(15, 8)
+#define  MAX_2UI_SPDIF_WRITE		GENMASK(23, 16)
+#define  MAX_2UI_I2S_HI_WRITE		GENMASK(23, 20)
+#define   MAX_2UI_I2S_LFE_CC_SWAP	BIT(1)
+#define  MAX_2UI_I2S_LO_WRITE		GENMASK(19, 16)
+#define  AUD_ERR_THRESH			GENMASK(29, 24)
+#define  I2S2DSD_EN			BIT(30)
+#define AIP_I2S_CTRL			0x410
+#define  FIFO0_MAP			GENMASK(1, 0)
+#define  FIFO1_MAP			GENMASK(3, 2)
+#define  FIFO2_MAP			GENMASK(5, 4)
+#define  FIFO3_MAP			GENMASK(7, 6)
+#define  I2S_1ST_BIT_NOSHIFT		BIT(8)
+#define  I2S_DATA_DIR_LSB		BIT(9)
+#define  JUSTIFY_RIGHT			BIT(10)
+#define  WS_HIGH			BIT(11)
+#define  VBIT_COMPRESSED		BIT(12)
+#define  CBIT_ORDER_SAME		BIT(13)
+#define  SCK_EDGE_RISE			BIT(14)
+#define AIP_I2S_CHST0			0x414
+#define AIP_I2S_CHST1			0x418
+#define AIP_TXCTRL			0x424
+#define  RST4AUDIO			BIT(0)
+#define  RST4AUDIO_FIFO			BIT(1)
+#define  RST4AUDIO_ACR			BIT(2)
+#define  AUD_LAYOUT_1			BIT(4)
+#define  AUD_MUTE_FIFO_EN		BIT(5)
+#define  AUD_PACKET_DROP		BIT(6)
+#define  DSD_MUTE_EN			BIT(7)
+#define AIP_TPI_CTRL			0x428
+#define  TPI_AUDIO_LOOKUP_EN		BIT(2)
+
+/* Video downsampling configuration */
+#define VID_DOWNSAMPLE_CONFIG		0x8d0
+#define  C444_C422_CONFIG_ENABLE	BIT(0)
+#define  C422_C420_CONFIG_ENABLE	BIT(4)
+#define  C422_C420_CONFIG_BYPASS	BIT(5)
+#define  C422_C420_CONFIG_OUT_CB_OR_CR	BIT(6)
+#define VID_OUT_FORMAT			0x8fc
+#define  OUTPUT_FORMAT_DEMUX_420_ENABLE	BIT(10)
+
+/* HDCP registers */
+#define HDCP_TOP_CTRL			0xc00
+#define HDCP2X_CTRL_0			0xc20
+#define  HDCP2X_EN			BIT(0)
+#define  HDCP2X_ENCRYPT_EN		BIT(7)
+#define  HDCP2X_HPD_OVR			BIT(10)
+#define  HDCP2X_HPD_SW			BIT(11)
+#define HDCP2X_POL_CTRL			0xc54
+#define  HDCP2X_DIS_POLL_EN		BIT(16)
+#define HDCP1X_CTRL			0xcd0
+#define  HDCP1X_ENC_EN			BIT(6)
+
+/* HDMI DDC registers */
+#define HPD_DDC_CTRL			0xc08
+#define  HPD_DDC_DELAY_CNT		GENMASK(31, 16)
+#define  HPD_DDC_HPD_DBNC_EN		BIT(2)
+#define  HPD_DDC_PORD_DBNC_EN		BIT(3)
+#define DDC_CTRL			0xc10
+#define  DDC_CTRL_ADDR			GENMASK(7, 1)
+#define  DDC_CTRL_OFFSET		GENMASK(15, 8)
+#define  DDC_CTRL_DIN_CNT		GENMASK(25, 16)
+#define  DDC_CTRL_CMD			GENMASK(31, 28)
+#define SCDC_CTRL			0xc18
+#define  SCDC_DDC_SEGMENT		GENMASK(15, 8)
+#define HPD_DDC_STATUS			0xc60
+#define  HPD_STATE			GENMASK(1, 0)
+#define   HPD_STATE_CONNECTED		2
+#define  HPD_PIN_STA			BIT(4)
+#define  PORD_PIN_STA			BIT(5)
+#define  DDC_I2C_IN_PROG		BIT(13)
+#define  DDC_DATA_OUT			GENMASK(23, 16)
+#define SI2C_CTRL			0xcac
+#define  SI2C_WR			BIT(0)
+#define  SI2C_RD			BIT(1)
+#define  SI2C_CONFIRM_READ		BIT(2)
+#define  SI2C_WDATA			GENMASK(15, 8)
+#define  SI2C_ADDR			GENMASK(23, 16)
+
+/* HDCP DDC registers */
+#define HDCP2X_DDCM_STATUS		0xc68
+#define  DDC_I2C_NO_ACK			BIT(10)
+#define  DDC_I2C_BUS_LOW		BIT(11)
+
+/* HDMI TX registers */
+#define HDMITX_CONFIG_MT8188		0xea0
+#define HDMITX_CONFIG_MT8195		0x900
+#define  HDMI_YUV420_MODE		BIT(10)
+#define  HDMITX_SW_HPD			BIT(29)
+#define  HDMITX_SW_RSTB			BIT(31)
+
+/**
+ * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
+ * @DDC_CMD_READ_NOACK:      Current address read with no ACK on last byte
+ * @DDC_CMD_READ:            Current address read with ACK on last byte
+ * @DDC_CMD_SEQ_READ_NOACK:  Sequential read with no ACK on last byte
+ * @DDC_CMD_SEQ_READ:        Sequential read with ACK on last byte
+ * @DDC_CMD_ENH_READ_NOACK:  Enhanced read with no ACK on last byte
+ * @DDC_CMD_ENH_READ:        Enhanced read with ACK on last byte
+ * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
+ * @DDC_CMD_SEQ_WRITE:       Sequential write requiring ACK on last byte
+ * @DDC_CMD_RSVD:            Reserved for future use
+ * @DDC_CMD_CLEAR_FIFO:      Clear DDC I2C FIFO
+ * @DDC_CMD_CLOCK_SCL:       Start clocking DDC I2C SCL
+ * @DDC_CMD_ABORT_XFER:      Abort DDC I2C transaction
+ */
+enum mtk_hdmi_ddc_v2_cmds {
+	DDC_CMD_READ_NOACK = 0x0,
+	DDC_CMD_READ,
+	DDC_CMD_SEQ_READ_NOACK,
+	DDC_CMD_SEQ_READ,
+	DDC_CMD_ENH_READ_NOACK,
+	DDC_CMD_ENH_READ,
+	DDC_CMD_SEQ_WRITE_NOACK,
+	DDC_CMD_SEQ_WRITE = 0x07,
+	DDC_CMD_CLEAR_FIFO = 0x09,
+	DDC_CMD_CLOCK_SCL = 0x0a,
+	DDC_CMD_ABORT_XFER = 0x0f
+};
+
+#endif /* _MTK_HDMI_REGS_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
new file mode 100644
index 000000000000..05cbfc45be54
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
@@ -0,0 +1,1488 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek HDMI v2 IP driver
+ *
+ * Copyright (c) 2022 MediaTek Inc.
+ * Copyright (c) 2022 BayLibre, SAS
+ * Copyright (c) 2024 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/of_graph.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pm_runtime.h>
+#include <linux/suspend.h>
+#include <linux/timer.h>
+#include <linux/units.h>
+
+#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_hdmi_state_helper.h>
+#include <drm/display/drm_scdc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+
+#include "mtk_hdmi_common.h"
+#include "mtk_hdmi_regs_v2.h"
+
+#define MTK_HDMI_V2_CLOCK_MIN	27000
+#define MTK_HDMI_V2_CLOCK_MAX	594000
+
+#define HPD_PORD_HWIRQS		(HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)
+
+enum mtk_hdmi_v2_clk_id {
+	MTK_HDMI_V2_CLK_HDCP_SEL,
+	MTK_HDMI_V2_CLK_HDCP_24M_SEL,
+	MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI,
+	MTK_HDMI_V2_CLK_HDMI_APB_SEL,
+	MTK_HDMI_V2_CLK_COUNT,
+};
+
+const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] = {
+	[MTK_HDMI_V2_CLK_HDMI_APB_SEL] = "bus",
+	[MTK_HDMI_V2_CLK_HDCP_SEL] = "hdcp",
+	[MTK_HDMI_V2_CLK_HDCP_24M_SEL] = "hdcp24m",
+	[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
+};
+
+static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi)
+{
+	regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0);
+	regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0);
+}
+
+static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable)
+{
+	if (enable)
+		regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
+	else
+		regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
+}
+
+static inline void mtk_hdmi_v2_clear_hpd_pord_irq(struct mtk_hdmi *hdmi)
+{
+	regmap_set_bits(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS);
+	regmap_clear_bits(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS);
+}
+
+static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable)
+{
+	if (enable) {
+		regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
+		regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+		regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+	} else {
+		regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+		regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+		regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
+	}
+}
+
+static void mtk_hdmi_v2_disable_hdcp_encrypt(struct mtk_hdmi *hdmi)
+{
+	regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_ENCRYPT_EN);
+	regmap_clear_bits(hdmi->regs, HDCP1X_CTRL, HDCP1X_ENC_EN);
+}
+
+static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable)
+{
+	struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc;
+
+	if (enable)
+		regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
+	else
+		regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
+
+	if (scdc->supported) {
+		if (scdc->scrambling.supported)
+			drm_scdc_set_scrambling(hdmi->curr_conn, enable);
+		drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable);
+	}
+}
+
+static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable)
+{
+	/* If enabled, sends a black image */
+	if (enable)
+		regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
+	else
+		regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
+}
+
+static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable)
+{
+	u32 aip, val;
+
+	if (!enable) {
+		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN);
+		return;
+	}
+
+	regmap_read(hdmi->regs, AIP_CTRL, &aip);
+
+	val = AUD_MUTE_FIFO_EN;
+	if (aip & DSD_EN)
+		val |= DSD_MUTE_EN;
+
+	regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val);
+}
+
+static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi)
+{
+	regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
+	udelay(5);
+	regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
+}
+
+static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len)
+{
+	unsigned short i;
+	u32 val = 0;
+
+	for (i = 0; i < len; i++)
+		val |= buffer[i] << (i * 8);
+
+	return val;
+}
+
+static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+
+	regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+	regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3));
+	regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
+	regmap_write(hdmi->regs, TOP_AIF_PKT02, 0);
+	regmap_write(hdmi->regs, TOP_AIF_PKT03, 0);
+
+	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+	regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
+}
+
+static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+
+	regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+	regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+	regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
+	regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
+	regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
+	regmap_write(hdmi->regs, TOP_AVI_PKT04, 0);
+	regmap_write(hdmi->regs, TOP_AVI_PKT05, 0);
+
+	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+	regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+}
+
+static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+
+	regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4));
+	regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]);
+
+	regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+}
+
+static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
+{
+	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+
+	regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
+	regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
+	regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
+	regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0);
+	regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0);
+	regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0);
+	regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0);
+	regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0);
+	regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0);
+
+	regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+}
+
+static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable)
+{
+	u32 val;
+
+	regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val);
+
+	if (enable) {
+		regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg,
+				HDMI_YUV420_MODE | HDMITX_SW_HPD);
+
+		val |= C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE;
+		val |= C422_C420_CONFIG_OUT_CB_OR_CR;
+		val &= ~C422_C420_CONFIG_BYPASS;
+		regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
+
+		regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
+	} else {
+		regmap_update_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg,
+				   HDMI_YUV420_MODE | HDMITX_SW_HPD, HDMITX_SW_HPD);
+
+		val &= ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE);
+		val &= ~C422_C420_CONFIG_OUT_CB_OR_CR;
+		val |= C422_C420_CONFIG_BYPASS;
+		regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
+
+		regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
+	}
+}
+
+static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
+{
+	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
+	struct hdmi_audio_infoframe frame;
+	u8 buffer[14];
+	ssize_t ret;
+
+	memcpy(&frame, &params->cea, sizeof(frame));
+
+	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
+	if (ret < 0)
+		return ret;
+
+	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
+
+	return 0;
+}
+
+static inline void mtk_hdmi_v2_hw_reset_av_mute_regs(struct mtk_hdmi *hdmi)
+{
+	/* GCP packet */
+	regmap_clear_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN | CP_SET_MUTE_EN);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
+	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
+}
+
+static inline void mtk_hdmi_v2_hw_av_mute(struct mtk_hdmi *hdmi, bool mute)
+{
+	mtk_hdmi_v2_hw_reset_av_mute_regs(hdmi);
+
+	if (mute)
+		regmap_set_bits(hdmi->regs, TOP_CFG01, CP_SET_MUTE_EN);
+	else
+		regmap_set_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN);
+
+	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
+	regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
+}
+
+static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable)
+{
+	if (enable)
+		regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
+	else
+		regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
+}
+
+static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, u8 *ch_status)
+{
+	/* Only the first 5 to 7 bytes of Channel Status contain useful information */
+	regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4));
+	regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3));
+}
+
+static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
+				     unsigned int sample_rate,
+				     unsigned int clock)
+{
+	unsigned int n, cts;
+	int ret;
+
+	ret = mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
+	if (ret) {
+		dev_err(hdmi->dev, "Invalid sample rate: %u\n", sample_rate);
+		return;
+	}
+
+	regmap_write(hdmi->regs, AIP_N_VAL, n);
+	regmap_write(hdmi->regs, AIP_CTS_SVAL, cts);
+}
+
+static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable)
+{
+	if (enable)
+		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
+	else
+		regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
+}
+
+static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 sd3,
+					   u8 sd4, u8 sd5, u8 sd6, u8 sd7)
+{
+	u32 val;
+
+	/*
+	 * Each of the Output Channels (0-7) can be mapped to get their input
+	 * from any of the available Input Channels (0-7): this function
+	 * takes input channel numbers and formats a value that must then
+	 * be written to the TOP_AUD_MAP hardware register by the caller.
+	 */
+	val = FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1);
+	val |= FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3);
+	val |= FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5);
+	val |= FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7);
+
+	return val;
+}
+
+static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi,
+				      unsigned char chnum, bool dsd_bypass)
+{
+	u32 channel_map;
+
+	regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN);
+	regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN);
+
+	if (dsd_bypass)
+		channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 2, 4, 6, 1, 3, 5, 7);
+	else
+		channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 5, 1, 0, 3, 2, 4, 0);
+
+	regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map);
+	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping)
+{
+	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL,
+			   FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, fifo_mapping);
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum)
+{
+	regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum));
+}
+
+static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping)
+{
+	u32 fifo_map;
+	u8 bdata;
+
+	switch (chnum) {
+	default:
+	case 2:
+		bdata = 0x1;
+		break;
+	case 3:
+		bdata = 0x3;
+		break;
+	case 6:
+		if (mapping == 0x0e) {
+			bdata = 0xf;
+			break;
+		}
+		fallthrough;
+	case 5:
+		bdata = 0x7;
+		break;
+	case 7:
+	case 8:
+		bdata = 0xf;
+		break;
+	}
+
+	/* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */
+	fifo_map = FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1);
+	fifo_map |= FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3);
+	mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map);
+	mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata);
+
+	/*
+	 * Set HDMI Audio packet layout indicator:
+	 * Layout 0 is for two channels
+	 * Layout 1 is for up to eight channels
+	 */
+	if (chnum == 2)
+		regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
+	else
+		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
+}
+
+static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt)
+{
+	u32 val;
+
+	regmap_read(hdmi->regs, AIP_I2S_CTRL, &val);
+	val &= ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
+
+	switch (fmt) {
+	case HDMI_I2S_MODE_RJT_24BIT:
+	case HDMI_I2S_MODE_RJT_16BIT:
+		val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
+		break;
+	case HDMI_I2S_MODE_LJT_24BIT:
+	case HDMI_I2S_MODE_LJT_16BIT:
+		val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT);
+		break;
+	case HDMI_I2S_MODE_I2S_24BIT:
+	case HDMI_I2S_MODE_I2S_16BIT:
+	default:
+		break;
+	}
+
+	regmap_write(hdmi->regs, AIP_I2S_CTRL, val);
+}
+
+static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise)
+{
+	if (rise)
+		regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
+	else
+		regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
+}
+
+static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit)
+{
+	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit);
+}
+
+static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit)
+{
+	/* V bit: 0 for PCM, 1 for Compressed data */
+	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit);
+}
+
+static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb)
+{
+	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb);
+}
+
+static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s)
+{
+	regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s));
+}
+
+static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type)
+{
+	switch (channel_type) {
+	case HDMI_AUD_CHAN_TYPE_1_1:
+	case HDMI_AUD_CHAN_TYPE_2_1:
+		return 0x01;
+	case HDMI_AUD_CHAN_TYPE_3_0:
+		return 0x02;
+	case HDMI_AUD_CHAN_TYPE_3_1:
+		return 0x03;
+	case HDMI_AUD_CHAN_TYPE_3_0_LRS:
+	case HDMI_AUD_CHAN_TYPE_4_0:
+		return 0x08;
+	case HDMI_AUD_CHAN_TYPE_5_1:
+		return 0x0b;
+	case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
+	case HDMI_AUD_CHAN_TYPE_6_0:
+	case HDMI_AUD_CHAN_TYPE_6_0_CS:
+	case HDMI_AUD_CHAN_TYPE_6_0_CH:
+	case HDMI_AUD_CHAN_TYPE_6_0_OH:
+	case HDMI_AUD_CHAN_TYPE_6_0_CHR:
+		return 0x0e;
+	case HDMI_AUD_CHAN_TYPE_1_0:
+	case HDMI_AUD_CHAN_TYPE_2_0:
+	case HDMI_AUD_CHAN_TYPE_3_1_LRS:
+	case HDMI_AUD_CHAN_TYPE_4_1:
+	case HDMI_AUD_CHAN_TYPE_5_0:
+	case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
+	case HDMI_AUD_CHAN_TYPE_6_1:
+	case HDMI_AUD_CHAN_TYPE_6_1_CS:
+	case HDMI_AUD_CHAN_TYPE_6_1_CH:
+	case HDMI_AUD_CHAN_TYPE_6_1_OH:
+	case HDMI_AUD_CHAN_TYPE_6_1_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_0:
+	case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
+	case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
+	case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
+	case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
+	case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
+	case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
+	case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
+	case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
+	case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
+	case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
+	case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
+	case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
+	case HDMI_AUD_CHAN_TYPE_7_1:
+	case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
+	case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
+	case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
+	case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
+	case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
+	case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
+	case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
+	case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
+	case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
+	case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
+	case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
+	case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi, unsigned char swapbit)
+{
+	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE,
+			   FIELD_PREP(MAX_2UI_I2S_HI_WRITE, swapbit));
+}
+
+static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass)
+{
+	const u32 hbr_mask = SPDIF_EN | DSD_EN | HBRA_ON;
+
+	if (dsd_bypass) {
+		regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON);
+		regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN);
+	} else {
+		regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN);
+		regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE);
+		regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF);
+		regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4);
+	}
+}
+
+static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi)
+{
+	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK);
+	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE);
+	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK);
+
+	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE,
+			   FIELD_PREP(MAX_1UI_WRITE, 4));
+	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE,
+			   FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9));
+	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH,
+			   FIELD_PREP(AUD_ERR_THRESH, 4));
+
+	regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
+}
+
+static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi)
+{
+	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
+	u8 i2s_ch_map;
+	u32 out_ch_map;
+
+	/* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1, etc */
+	out_ch_map = mtk_hdmi_v2_aud_output_channel_map(0, 1, 2, 3, 4, 5, 6, 7);
+	regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map);
+
+	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0);
+	regmap_clear_bits(hdmi->regs, AIP_CTRL,
+			  SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 |
+			  HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE);
+	regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1);
+
+	if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) {
+		switch (aud_param->aud_codec) {
+		case HDMI_AUDIO_CODING_TYPE_DTS_HD:
+		case HDMI_AUDIO_CODING_TYPE_MLP:
+			mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
+			mtk_hdmi_hbr_config(hdmi, true);
+			break;
+		case HDMI_AUDIO_CODING_TYPE_DSD:
+			mtk_hdmi_audio_dsd_config(hdmi, aud_param->codec_params.channels, 0);
+			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, aud_param->codec_params.channels, 1);
+			break;
+		default:
+			mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
+			mtk_hdmi_i2s_sck_edge_rise(hdmi, true);
+			mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME);
+			mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */
+			mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */
+			mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S);
+			i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi,
+						aud_param->aud_input_chan_type);
+			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi,
+						aud_param->codec_params.channels, i2s_ch_map);
+			mtk_hdmi_v2_hw_i2s_ch_swap(hdmi, MAX_2UI_I2S_LFE_CC_SWAP);
+		}
+	} else {
+		if (aud_param->codec_params.sample_rate == 768000 &&
+		    (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD ||
+		     aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) {
+			mtk_hdmi_hbr_config(hdmi, false);
+		} else {
+			mtk_hdmi_v2_hw_spdif_config(hdmi);
+			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0);
+		}
+	}
+}
+
+static void mtk_hdmi_v2_aud_set_sw_ncts(struct mtk_hdmi *hdmi,
+				     struct drm_display_mode *display_mode)
+{
+	mtk_hdmi_v2_hw_ncts_enable(hdmi, false);
+	mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate,
+				 display_mode->clock);
+}
+
+static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi,
+						  unsigned int enable)
+{
+	if (enable)
+		regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
+	else
+		regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
+}
+
+static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi)
+{
+	regmap_set_bits(hdmi->regs, AIP_CTRL,
+			AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN);
+	regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN);
+}
+
+static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset)
+{
+	const u32 arst_bits = RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR;
+
+	if (reset)
+		regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
+	else
+		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
+}
+
+static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi,
+				       struct drm_display_mode *display_mode)
+{
+	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+	mtk_hdmi_v2_hw_aud_enable(hdmi, false);
+	mtk_hdmi_v2_audio_reset(hdmi, true);
+	mtk_hdmi_v2_aip_ctrl_init(hdmi);
+	mtk_hdmi_v2_aud_set_input(hdmi);
+	mtk_hdmi_v2_hw_aud_set_channel_status(hdmi, hdmi->aud_param.codec_params.iec.status);
+	mtk_hdmi_v2_setup_audio_infoframe(hdmi);
+	mtk_hdmi_v2_hw_audio_input_enable(hdmi, true);
+	mtk_hdmi_v2_audio_reset(hdmi, false);
+	mtk_hdmi_v2_aud_set_sw_ncts(hdmi, display_mode);
+
+	/* Wait for the HW to apply settings */
+	usleep_range(25, 50);
+
+	mtk_hdmi_v2_hw_ncts_enable(hdmi, true);
+	mtk_hdmi_v2_hw_aud_enable(hdmi, true);
+	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
+}
+
+static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi)
+{
+	mtk_hdmi_v2_hw_reset(hdmi);
+	mtk_hdmi_v2_set_sw_hpd(hdmi, true);
+	udelay(2);
+
+	regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0);
+
+	/* Enable HDCP reauthentication interrupt */
+	regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);
+
+	/* Enable hotplug and pord interrupts */
+	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+
+	/* Force enabling HDCP HPD */
+	regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
+	regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
+
+	/* Set 8 bits per pixel */
+	regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE,
+			   FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP));
+	/* Disable generating deepcolor packets */
+	regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN);
+	/* Disable adding deepcolor information to the general packet */
+	regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD);
+
+	if (hdmi->dvi_mode)
+		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
+	else
+		regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
+
+	udelay(5);
+	mtk_hdmi_v2_hw_vid_mute(hdmi, true);
+	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+	mtk_hdmi_v2_hw_av_mute(hdmi, false);
+
+	regmap_update_bits(hdmi->regs, TOP_CFG01,
+			   NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN);
+	usleep_range(100, 150);
+
+	/* Enable scrambling if tmds clock is 340MHz or more */
+	mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO);
+
+	/* Disable YUV420 downsampling */
+	mtk_hdmi_yuv420_downsampling(hdmi, false);
+}
+
+static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi,
+						struct drm_display_mode *mode)
+{
+	union phy_configure_opts opts = {
+		.dp = { .link_rate = hdmi->mode.clock * KILO }
+	};
+	int ret;
+
+	ret = phy_configure(hdmi->phy, &opts);
+	if (ret)
+		dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret);
+
+	mtk_hdmi_v2_change_video_resolution(hdmi);
+	mtk_hdmi_v2_aud_output_config(hdmi, mode);
+}
+
+static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi)
+{
+	int ret;
+
+	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+	if (ret)
+		return ret;
+
+	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+	if (ret)
+		goto disable_hdcp_clk;
+
+	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+	if (ret)
+		goto disable_hdcp_24m_clk;
+
+	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
+	if (ret)
+		goto disable_bus_clk;
+
+	return 0;
+
+disable_bus_clk:
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+disable_hdcp_24m_clk:
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+disable_hdcp_clk:
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+
+	return ret;
+}
+
+static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi)
+{
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
+	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
+}
+
+static void mtk_hdmi_hpd_event(enum hdmi_hpd_state hpd, struct device *dev)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
+		drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
+}
+
+static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi)
+{
+	u8 hpd_pin_sta, pord_pin_sta;
+	u32 hpd_status;
+
+	regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status);
+	hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status);
+	pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status);
+
+	if (hpd_pin_sta && pord_pin_sta)
+		return HDMI_PLUG_IN_AND_SINK_POWER_ON;
+	else if (hpd_pin_sta)
+		return HDMI_PLUG_IN_ONLY;
+	else
+		return HDMI_PLUG_OUT;
+}
+
+static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg)
+{
+	struct mtk_hdmi *hdmi = arg;
+	unsigned int irq_sta;
+	int ret = IRQ_HANDLED;
+
+	regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta);
+
+	/* Handle Hotplug Detection interrupt */
+	if (irq_sta & (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)) {
+		mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false);
+		ret = IRQ_WAKE_THREAD;
+	}
+
+	/*
+	 * Clear all 32 + 19 interrupts in CLR00 and CLR01: this is important
+	 * to avoid unwanted retriggering of any interrupts
+	 */
+	regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));
+	regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));
+
+	/* Restore interrupt clearing registers to zero */
+	regmap_write(hdmi->regs, TOP_INT_CLR00, 0);
+	regmap_write(hdmi->regs, TOP_INT_CLR01, 0);
+
+	return ret;
+}
+
+static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi)
+{
+	enum hdmi_hpd_state hpd;
+
+	hpd = mtk_hdmi_v2_hpd_pord_status(hdmi);
+	if (hpd != hdmi->hpd) {
+		hdmi->hpd = hpd;
+		mtk_hdmi_hpd_event(hpd, hdmi->dev);
+	}
+
+	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg)
+{
+	struct mtk_hdmi *hdmi = arg;
+
+	/*
+	 * Debounce HDMI monitor HPD status.
+	 * Empirical testing shows that 30ms is enough wait
+	 */
+	msleep(30);
+
+	return __mtk_hdmi_v2_isr_thread(hdmi);
+}
+
+static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi)
+{
+	int ret;
+
+	ret = pm_runtime_resume_and_get(hdmi->dev);
+	if (ret) {
+		dev_err(hdmi->dev, "Cannot resume HDMI\n");
+		return ret;
+	}
+
+	mtk_hdmi_v2_clk_enable(hdmi);
+	mtk_hdmi_v2_hw_reset(hdmi);
+	mtk_hdmi_v2_set_sw_hpd(hdmi, true);
+
+	return 0;
+}
+
+/*
+ * Bridge callbacks
+ */
+
+static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge,
+				     enum drm_bridge_attach_flags flags)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+	int ret;
+
+	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+		DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n");
+		return -EINVAL;
+	}
+	if (hdmi->next_bridge) {
+		ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
+		if (ret)
+			return ret;
+	}
+
+	/* Enable the controller at attach time for HPD/Pord feedback */
+	ret = mtk_hdmi_v2_enable(hdmi);
+	if (ret)
+		return ret;
+
+	/* Enable Hotplug and Pord pins internal debouncing */
+	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
+			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
+
+	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
+	enable_irq(hdmi->irq);
+
+	/*
+	 * Check if any HDMI monitor was connected before probing this driver
+	 * and/or attaching the bridge, without debouncing: if so, we want to
+	 * notify the DRM so that we start outputting an image ASAP.
+	 * Note that calling the ISR thread function will also perform a HW
+	 * registers write that enables both the HPD and Pord interrupts.
+	 */
+	__mtk_hdmi_v2_isr_thread(hdmi);
+
+	return 0;
+}
+
+static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	/* Disable interrupts */
+	mtk_hdmi_v2_hwirq_disable(hdmi);
+	disable_irq(hdmi->irq);
+	pm_runtime_put_sync(hdmi->dev);
+}
+
+static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged)
+{
+	mutex_lock(&hdmi->update_plugged_status_lock);
+	if (hdmi->plugged_cb && hdmi->codec_dev)
+		hdmi->plugged_cb(hdmi->codec_dev, plugged);
+	mutex_unlock(&hdmi->update_plugged_status_lock);
+}
+
+static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
+					  struct drm_bridge_state *old_state)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+	struct drm_atomic_state *state = old_state->base.state;
+	struct drm_connector_state *conn_state;
+	union phy_configure_opts opts = {
+		.dp = { .link_rate = hdmi->mode.clock * KILO }
+	};
+
+	/* Retrieve the connector through the atomic state */
+	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
+
+	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
+	if (WARN_ON(!conn_state))
+		return;
+
+	/*
+	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
+	 * stage to make sure that this IP is ready and clocked before the
+	 * mtk_dpi gets powered on and before it enables the output.
+	 */
+	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
+	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
+
+	/* Reconfigure phy clock link with appropriate rate */
+	phy_configure(hdmi->phy, &opts);
+
+	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
+	phy_power_on(hdmi->phy);
+
+	hdmi->powered = true;
+}
+
+static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
+				      struct drm_bridge_state *old_state)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+	struct drm_atomic_state *state = old_state->base.state;
+	int ret;
+
+	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
+	if (ret)
+		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
+
+	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
+	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
+
+	/* signal the connect event to audio codec */
+	mtk_hdmi_v2_handle_plugged_change(hdmi, true);
+
+	hdmi->enabled = true;
+}
+
+static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge,
+				       struct drm_bridge_state *old_bridge_state)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	if (!hdmi->enabled)
+		return;
+
+	mtk_hdmi_v2_hw_av_mute(hdmi, true);
+	msleep(50);
+	mtk_hdmi_v2_hw_vid_mute(hdmi, true);
+	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
+	mtk_hdmi_v2_disable_hdcp_encrypt(hdmi);
+	msleep(50);
+
+	hdmi->enabled = false;
+}
+
+static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge,
+					    struct drm_bridge_state *old_state)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	if (!hdmi->powered)
+		return;
+
+	/* Disable VSync interrupt */
+	regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HDMI_VSYNC_INT);
+
+	phy_power_off(hdmi->phy);
+	hdmi->powered = false;
+
+	/* signal the disconnect event to audio codec */
+	mtk_hdmi_v2_handle_plugged_change(hdmi, false);
+}
+
+static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	return hdmi->hpd != HDMI_PLUG_OUT ?
+	       connector_status_connected : connector_status_disconnected;
+}
+
+static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge,
+							   struct drm_connector *connector)
+{
+	return drm_edid_read(connector);
+}
+
+static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
+						 const struct drm_display_mode *mode,
+						 unsigned long long tmds_rate)
+{
+	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
+		return MODE_CLOCK_LOW;
+	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
+		return MODE_CLOCK_HIGH;
+	else
+		return MODE_OK;
+}
+
+static enum drm_mode_status
+mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
+			      const struct drm_display_info *info,
+			      const struct drm_display_mode *mode)
+{
+	unsigned long long rate;
+
+	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
+	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
+}
+
+static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
+					    enum hdmi_infoframe_type type)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+	u32 reg_start, reg_end;
+
+	switch (type) {
+	case HDMI_INFOFRAME_TYPE_AUDIO:
+		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
+		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
+		reg_start = TOP_AIF_HEADER;
+		reg_end = TOP_AIF_PKT03;
+		break;
+	case HDMI_INFOFRAME_TYPE_AVI:
+		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
+		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
+		reg_start = TOP_AVI_HEADER;
+		reg_end = TOP_AVI_PKT05;
+		break;
+	case HDMI_INFOFRAME_TYPE_SPD:
+		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
+		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
+		reg_start = TOP_SPDIF_HEADER;
+		reg_end = TOP_SPDIF_PKT07;
+		break;
+	case HDMI_INFOFRAME_TYPE_VENDOR:
+		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
+		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
+		reg_start = TOP_VSIF_HEADER;
+		reg_end = TOP_VSIF_PKT07;
+		break;
+	case HDMI_INFOFRAME_TYPE_DRM:
+	default:
+		return 0;
+	};
+
+	for (; reg_start <= reg_end; reg_start += 4)
+		regmap_write(hdmi->regs, reg_start, 0);
+
+	return 0;
+}
+
+static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
+					    enum hdmi_infoframe_type type,
+					    const u8 *buffer, size_t len)
+{
+	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
+
+	switch (type) {
+	case HDMI_INFOFRAME_TYPE_AUDIO:
+		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
+		break;
+	case HDMI_INFOFRAME_TYPE_AVI:
+		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
+		break;
+	case HDMI_INFOFRAME_TYPE_SPD:
+		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
+		break;
+	case HDMI_INFOFRAME_TYPE_VENDOR:
+		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
+		break;
+	case HDMI_INFOFRAME_TYPE_DRM:
+	default:
+		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
+		break;
+	};
+
+	return 0;
+}
+
+static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
+					   struct drm_bridge_state *bridge_state,
+					   struct drm_crtc_state *crtc_state,
+					   struct drm_connector_state *conn_state)
+{
+	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
+						      conn_state->state);
+}
+
+static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
+{
+	struct drm_display_mode *mode = &hdmi->mode;
+	int abist_format = -EINVAL;
+	bool interlaced;
+
+	if (!enable) {
+		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
+		return 0;
+	}
+
+	if (!mode->hdisplay || !mode->vdisplay)
+		return -EINVAL;
+
+	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+
+	switch (mode->hdisplay) {
+	case 720:
+		if (mode->vdisplay == 480)
+			abist_format = 2;
+		else if (mode->vdisplay == 576)
+			abist_format = 11;
+		break;
+	case 1280:
+		if (mode->vdisplay == 720)
+			abist_format = 3;
+		break;
+	case 1440:
+		if (mode->vdisplay == 480)
+			abist_format = interlaced ? 5 : 9;
+		else if (mode->vdisplay == 576)
+			abist_format = interlaced ? 14 : 18;
+		break;
+	case 1920:
+		if (mode->vdisplay == 1080)
+			abist_format = interlaced ? 4 : 10;
+		break;
+	case 3840:
+		if (mode->vdisplay == 2160)
+			abist_format = 25;
+		break;
+	case 4096:
+		if (mode->vdisplay == 2160)
+			abist_format = 26;
+		break;
+	default:
+		break;
+	}
+	if (!abist_format)
+		return -EINVAL;
+
+	regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT,
+			   FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format));
+	regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
+	return 0;
+}
+
+static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg)
+{
+	struct mtk_hdmi *hdmi = m->private;
+	bool en;
+	u32 val;
+	int ret;
+
+	if (!hdmi)
+		return -EINVAL;
+
+	ret = regmap_read(hdmi->regs, TOP_CFG00, &val);
+	if (ret)
+		return ret;
+
+	en = FIELD_GET(HDMI_ABIST_ENABLE, val);
+
+	seq_printf(m, "HDMI Automated Built-In Self Test: %s\n",
+		   en ? "Enabled" : "Disabled");
+
+	return 0;
+}
+
+static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file,
+					     const char __user *ubuf,
+					     size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	int ret;
+	u32 en;
+
+	if (!m || !m->private || *offp)
+		return -EINVAL;
+
+	ret = kstrtouint_from_user(ubuf, len, 0, &en);
+	if (ret)
+		return ret;
+
+	if (en < 0 || en > 1)
+		return -EINVAL;
+
+	mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en);
+	return len;
+}
+
+static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private);
+}
+
+static const struct file_operations mtk_hdmi_debug_abist_fops = {
+	.owner = THIS_MODULE,
+	.open = mtk_hdmi_v2_debug_abist_open,
+	.read = seq_read,
+	.write = mtk_hdmi_v2_debug_abist_write,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
+{
+	struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(bridge);
+
+	debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_fops);
+}
+
+static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
+	.attach = mtk_hdmi_v2_bridge_attach,
+	.detach = mtk_hdmi_v2_bridge_detach,
+	.mode_fixup = mtk_hdmi_bridge_mode_fixup,
+	.mode_set = mtk_hdmi_bridge_mode_set,
+	.mode_valid = mtk_hdmi_v2_bridge_mode_valid,
+	.atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable,
+	.atomic_enable = mtk_hdmi_v2_bridge_enable,
+	.atomic_disable = mtk_hdmi_v2_bridge_disable,
+	.atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+	.atomic_check = mtk_hdmi_v2_bridge_atomic_check,
+	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.detect = mtk_hdmi_v2_bridge_detect,
+	.edid_read = mtk_hdmi_v2_bridge_edid_read,
+	.hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
+	.hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
+	.hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
+	.debugfs_init = mtk_hdmi_v2_debugfs_init,
+};
+
+/*
+ * HDMI audio codec callbacks
+ */
+static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *data,
+					     hdmi_codec_plugged_cb fn,
+					     struct device *codec_dev)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+	bool plugged;
+
+	if (!hdmi)
+		return -ENODEV;
+
+	mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
+	plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON);
+	mtk_hdmi_v2_handle_plugged_change(hdmi, plugged);
+
+	return 0;
+}
+
+static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data,
+				       struct hdmi_codec_daifmt *daifmt,
+				       struct hdmi_codec_params *params)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	if (hdmi->audio_enable) {
+		mtk_hdmi_audio_params(hdmi, daifmt, params);
+		mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode);
+	}
+	return 0;
+}
+
+static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	mtk_hdmi_v2_hw_aud_enable(hdmi, true);
+	hdmi->audio_enable = true;
+
+	return 0;
+}
+
+static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	hdmi->audio_enable = false;
+	mtk_hdmi_v2_hw_aud_enable(hdmi, false);
+}
+
+static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool enable, int dir)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	mtk_hdmi_v2_hw_aud_mute(hdmi, enable);
+
+	return 0;
+}
+
+static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = {
+	.hw_params = mtk_hdmi_v2_audio_hw_params,
+	.audio_startup = mtk_hdmi_v2_audio_startup,
+	.audio_shutdown = mtk_hdmi_v2_audio_shutdown,
+	.mute_stream = mtk_hdmi_v2_audio_mute,
+	.get_eld = mtk_hdmi_audio_get_eld,
+	.hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb,
+};
+
+static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+
+	mtk_hdmi_v2_hwirq_disable(hdmi);
+	mtk_hdmi_v2_clk_disable(hdmi);
+	pm_runtime_put_sync(dev);
+
+	return 0;
+}
+
+static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev)
+{
+	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
+	int ret;
+
+	pm_runtime_get_sync(dev);
+
+	ret = mtk_hdmi_v2_clk_enable(hdmi);
+	if (ret)
+		return ret;
+
+	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
+
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi_v2_resume);
+
+static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 = {
+	.bridge_funcs = &mtk_v2_hdmi_bridge_funcs,
+	.codec_ops = &mtk_hdmi_v2_audio_codec_ops,
+	.mtk_hdmi_clock_names = mtk_hdmi_v2_clk_names,
+	.num_clocks = MTK_HDMI_V2_CLK_COUNT
+};
+
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 = {
+	.ver_conf = &mtk_hdmi_conf_v2,
+	.reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8188
+};
+
+static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = {
+	.ver_conf = &mtk_hdmi_conf_v2,
+	.reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8195,
+};
+
+static int mtk_hdmi_v2_probe(struct platform_device *pdev)
+{
+	struct mtk_hdmi *hdmi;
+	int ret;
+
+	hdmi = mtk_hdmi_common_probe(pdev);
+	if (IS_ERR(hdmi))
+		return PTR_ERR(hdmi);
+
+	hdmi->hpd = HDMI_PLUG_OUT;
+
+	/*
+	 * Disable all HW interrupts at probe stage and install the ISR
+	 * but keep it disabled, as the rest of the interrupts setup is
+	 * done in the .bridge_attach() callback, which will enable both
+	 * the right HW IRQs and the ISR.
+	 */
+	mtk_hdmi_v2_hwirq_disable(hdmi);
+	irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN);
+	ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr,
+					mtk_hdmi_v2_isr_thread,
+					IRQ_TYPE_LEVEL_HIGH,
+					dev_name(&pdev->dev), hdmi);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n");
+
+	ret = devm_pm_runtime_enable(&pdev->dev);
+	if (ret)
+		return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
+
+	return 0;
+}
+
+static void mtk_hdmi_v2_remove(struct platform_device *pdev)
+{
+	struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
+
+	pm_runtime_disable(&pdev->dev);
+	i2c_put_adapter(hdmi->ddc_adpt);
+}
+
+static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] = {
+	{ .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
+	{ .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids);
+
+static struct platform_driver mtk_hdmi_v2_driver = {
+	.probe = mtk_hdmi_v2_probe,
+	.remove = mtk_hdmi_v2_remove,
+	.driver = {
+		.name = "mediatek-drm-hdmi-v2",
+		.of_match_table = mtk_drm_hdmi_v2_of_ids,
+		.pm = &mtk_hdmi_v2_pm_ops,
+	},
+};
+module_platform_driver(mtk_hdmi_v2_driver);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>>");
+MODULE_AUTHOR("Guillaume Ranquet <granquet@baylibre.com>");
+MODULE_DESCRIPTION("MediaTek HDMIv2 Driver");
+MODULE_LICENSE("GPL");
-- 
2.47.0

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[Dmitry Baryshkov]

On Thu, Dec 05, 2024 at 12:45:17PM +0100, AngeloGioacchino Del Regno wrote:
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
>  drivers/gpu/drm/mediatek/Kconfig            |    8 +
>  drivers/gpu/drm/mediatek/Makefile           |    4 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
>  drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
>  drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
>  7 files changed, 2172 insertions(+)
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
>  create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> 
> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> index 73459f07dae3..8127576be1eb 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -50,3 +50,11 @@ config DRM_MEDIATEK_HDMI
>  	select PHY_MTK_HDMI
>  	help
>  	  DRM/KMS HDMI driver for Mediatek SoCs
> +
> +config DRM_MEDIATEK_HDMI_V2
> +	tristate "DRM HDMI v2 IP support for MediaTek SoCs"
> +	depends on DRM_MEDIATEK
> +	select DRM_MEDIATEK_HDMI_COMMON
> +	select PHY_MTK_HDMI
> +	help
> +	  DRM/KMS HDMI driver for MediaTek SoCs with HDMIv2 IP
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 8973d7ba37d3..928a850f707f 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -25,7 +25,11 @@ mediatek-drm-hdmi-objs := mtk_cec.o \
>  			  mtk_hdmi.o \
>  			  mtk_hdmi_ddc.o
>  
> +mediatek-drm-hdmi-v2-objs := mtk_hdmi_ddc_v2.o \
> +			     mtk_hdmi_v2.o
> +
>  obj-$(CONFIG_DRM_MEDIATEK_HDMI_COMMON) += mtk_hdmi_common.o
>  obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
> +obj-$(CONFIG_DRM_MEDIATEK_HDMI_V2) += mediatek-drm-hdmi-v2.o
>  
>  obj-$(CONFIG_DRM_MEDIATEK_DP) += mtk_dp.o
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> index 0f60842462b0..90f603f34cde 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.c
> @@ -295,6 +295,11 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi, struct platform_device
>  	if (IS_ERR(hdmi->regs))
>  		return PTR_ERR(hdmi->regs);
>  
> +	/* Populate HDMI sub-devices if present */
> +	ret = devm_of_platform_populate(&pdev->dev);
> +	if (ret)
> +		return ret;
> +
>  	remote = of_graph_get_remote_node(np, 1, 0);
>  	if (!remote)
>  		return dev_err_probe(dev, -EINVAL, "Cannot find HDMI input port\n");
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> index 15121e8548f3..8cfff39b0d90 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_common.h
> @@ -176,6 +176,7 @@ struct mtk_hdmi_conf {
>  	bool tz_disabled;
>  	bool cea_modes_only;
>  	unsigned long max_mode_clock;
> +	u32 reg_hdmi_tx_cfg;
>  };
>  
>  static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
> new file mode 100644
> index 000000000000..297b8b6f668c
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
> @@ -0,0 +1,403 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek HDMI v2 Display Data Channel Driver
> + *
> + * Copyright (c) 2021 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre, SAS
> + * Copyright (c) 2024 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/errno.h>
> +#include <linux/i2c.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +#include <linux/semaphore.h>
> +#include <linux/slab.h>
> +#include <linux/time.h>
> +#include <linux/types.h>
> +
> +#include <drm/drm_edid.h>
> +
> +#include "mtk_hdmi_common.h"
> +#include "mtk_hdmi_regs_v2.h"
> +
> +#define DDC2_DLY_CNT 572 /* BIM=208M/(v*4) = 90Khz */
> +#define DDC2_DLY_CNT_EDID 832 /* BIM=208M/(v*4) = 62.5Khz */
> +#define SI2C_ADDR_READ 0xf4
> +#define SCDC_I2C_SLAVE_ADDRESS 0x54
> +
> +struct mtk_hdmi_ddc {
> +	struct device *dev;
> +	void __iomem *regs;
> +	struct clk *clk;
> +	struct i2c_adapter adap;
> +	/* Serialize read/write operations */
> +	struct mutex mtx;
> +};
> +
> +static int mtk_ddc_check_and_rise_low_bus(struct mtk_hdmi_ddc *ddc)
> +{
> +	u32 val;
> +
> +	regmap_read(ddc->regs, HDCP2X_DDCM_STATUS, &val);
> +	if (val & DDC_I2C_BUS_LOW) {
> +		regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
> +				   FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLOCK_SCL));
> +		usleep_range(250, 300);
> +	}
> +
> +	if (val & DDC_I2C_NO_ACK) {
> +		u32 ddc_ctrl, hpd_ddc_ctrl, hpd_ddc_status;
> +
> +		regmap_read(ddc->regs, DDC_CTRL, &ddc_ctrl);
> +		regmap_read(ddc->regs, HPD_DDC_CTRL, &hpd_ddc_ctrl);
> +		regmap_read(ddc->regs, HPD_DDC_STATUS, &hpd_ddc_status);
> +	}
> +
> +	if (val & DDC_I2C_NO_ACK)
> +		return -EIO;
> +
> +	return 0;
> +}
> +
> +static int mtk_ddc_wr_one(struct mtk_hdmi_ddc *ddc, u16 addr_id,
> +			  u16 offset_id, u8 wr_data)
> +{
> +	u32 val;
> +	int ret;
> +
> +	/* If down, rise bus for write operation */
> +	mtk_ddc_check_and_rise_low_bus(ddc);
> +
> +	regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
> +			   FIELD_PREP(HPD_DDC_DELAY_CNT, DDC2_DLY_CNT));
> +
> +	regmap_write(ddc->regs, SI2C_CTRL,
> +		     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
> +		     FIELD_PREP(SI2C_WDATA, wr_data) |
> +		     SI2C_WR);
> +
> +	regmap_write(ddc->regs, DDC_CTRL,
> +		     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_WRITE) |
> +		     FIELD_PREP(DDC_CTRL_DIN_CNT, 1) |
> +		     FIELD_PREP(DDC_CTRL_OFFSET, offset_id) |
> +		     FIELD_PREP(DDC_CTRL_ADDR, addr_id));
> +	usleep_range(1000, 1250);
> +
> +	ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
> +				       !(val & DDC_I2C_IN_PROG), 500, 1000);
> +	if (ret) {
> +		dev_err(ddc->dev, "DDC I2C write timeout\n");
> +		return ret;
> +	}
> +
> +	/* The I2C bus might be down after WR operation: rise it again */
> +	ret = mtk_ddc_check_and_rise_low_bus(ddc);
> +	if (ret) {
> +		dev_err(ddc->dev, "Error during write operation: No ACK\n");
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int mtk_ddcm_read_hdmi(struct mtk_hdmi_ddc *ddc, u16 dly_cnt, u16 uc_dev,
> +			      u8 addr, u8 *puc_value, u16 data_cnt)
> +{
> +	u16 i, loop_counter, temp_length, uc_idx;
> +	u32 rem, uc_read_count, val;
> +	int ret;
> +
> +	if (!puc_value || !data_cnt || !dly_cnt) {
> +		dev_err(ddc->dev, "Bad DDCM read request\n");
> +		return 0;
> +	}
> +
> +	mtk_ddc_check_and_rise_low_bus(ddc);
> +
> +	regmap_update_bits(ddc->regs, DDC_CTRL, DDC_CTRL_CMD,
> +			   FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_CLEAR_FIFO));
> +
> +	if (data_cnt >= 16) {
> +		temp_length = 16;
> +		loop_counter = data_cnt;
> +
> +		rem = do_div(loop_counter, temp_length);
> +		if (rem)
> +			loop_counter++;
> +	} else {
> +		temp_length = data_cnt;
> +		loop_counter = 1;
> +	}
> +
> +	if (uc_dev >= DDC_ADDR && dly_cnt < DDC2_DLY_CNT_EDID)
> +		dly_cnt = DDC2_DLY_CNT_EDID;
> +
> +	regmap_update_bits(ddc->regs, HPD_DDC_CTRL, HPD_DDC_DELAY_CNT,
> +			   FIELD_PREP(HPD_DDC_DELAY_CNT, dly_cnt));
> +
> +	for (i = 0; i < loop_counter; i++) {
> +		rem = data_cnt % 16;
> +
> +		if (i > 0 && i == (loop_counter - 1) && rem)
> +			temp_length = rem;
> +
> +		/* 0x51 - 0x53: Flow control */
> +		if (uc_dev > DDC_ADDR && uc_dev <= 0x53) {
> +			regmap_update_bits(ddc->regs, SCDC_CTRL, SCDC_DDC_SEGMENT,
> +					   FIELD_PREP(SCDC_DDC_SEGMENT, uc_dev - DDC_ADDR));
> +
> +			regmap_write(ddc->regs, DDC_CTRL,
> +				     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_ENH_READ_NOACK) |
> +				     FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
> +				     FIELD_PREP(DDC_CTRL_OFFSET, addr + i * temp_length) |
> +				     FIELD_PREP(DDC_CTRL_ADDR, DDC_ADDR));
> +		} else {
> +			u16 offset;
> +
> +			if (addr != 0x43)
> +				offset = i * 16;
> +			else
> +				offset = 0;
> +
> +			regmap_write(ddc->regs, DDC_CTRL,
> +				     FIELD_PREP(DDC_CTRL_CMD, DDC_CMD_SEQ_READ_NOACK) |
> +				     FIELD_PREP(DDC_CTRL_DIN_CNT, temp_length) |
> +				     FIELD_PREP(DDC_CTRL_OFFSET, addr + offset) |
> +				     FIELD_PREP(DDC_CTRL_ADDR, uc_dev));
> +		}
> +		usleep_range(5000, 5500);
> +
> +		ret = regmap_read_poll_timeout(ddc->regs, HPD_DDC_STATUS, val,
> +					       !(val & DDC_I2C_IN_PROG), 1000,
> +					       500 * (temp_length + 5));
> +		if (ret) {
> +			dev_err(ddc->dev, "Timeout waiting for DDC I2C\n");
> +			return ret;
> +		}
> +
> +		ret = mtk_ddc_check_and_rise_low_bus(ddc);
> +		if (ret) {
> +			dev_err(ddc->dev, "Error during read operation: No ACK\n");
> +			return ret;
> +		}
> +
> +		for (uc_idx = 0; uc_idx < temp_length; uc_idx++) {
> +			unsigned int read_idx = i * 16 + uc_idx;
> +
> +			regmap_write(ddc->regs, SI2C_CTRL,
> +				     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
> +				     SI2C_RD);
> +
> +			regmap_read(ddc->regs, HPD_DDC_STATUS, &val);
> +			puc_value[read_idx] = FIELD_GET(DDC_DATA_OUT, val);
> +
> +			regmap_write(ddc->regs, SI2C_CTRL,
> +				     FIELD_PREP(SI2C_ADDR, SI2C_ADDR_READ) |
> +				     SI2C_CONFIRM_READ);
> +
> +			/*
> +			 * If HDMI IP gets reset during EDID read, DDC read
> +			 * operation will fail and its delay counter will be
> +			 * reset to 400.
> +			 */
> +			regmap_read(ddc->regs, HPD_DDC_CTRL, &val);
> +			if (FIELD_GET(HPD_DDC_DELAY_CNT, val) < DDC2_DLY_CNT)
> +				return 0;
> +
> +			uc_read_count = read_idx + 1;
> +		}
> +	}
> +	if (uc_read_count > U8_MAX)
> +		dev_warn(ddc->dev, "Invalid read data count %u\n", uc_read_count);
> +
> +	return uc_read_count;
> +}
> +
> +static int mtk_hdmi_fg_ddc_data_read(struct mtk_hdmi_ddc *ddc, u16 b_dev,
> +				     u8 data_addr, u16 data_cnt, u8 *pr_data)
> +{
> +	int read_data_cnt;
> +	u16 req_data_cnt;
> +
> +	if (!pr_data || !data_cnt)
> +		return -EINVAL;
> +
> +	req_data_cnt = U8_MAX - data_addr + 1;
> +	if (req_data_cnt > data_cnt)
> +		req_data_cnt = data_cnt;
> +
> +	mutex_lock(&ddc->mtx);
> +
> +	regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
> +
> +	read_data_cnt = mtk_ddcm_read_hdmi(ddc, DDC2_DLY_CNT, b_dev, data_addr,
> +					   pr_data, req_data_cnt);
> +
> +	mutex_unlock(&ddc->mtx);
> +
> +	if (read_data_cnt < 0)
> +		return read_data_cnt;
> +	else if (read_data_cnt != req_data_cnt)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_ddc_fg_data_write(struct mtk_hdmi_ddc *ddc, u16 b_dev,
> +				      u8 data_addr, u16 data_cnt, u8 *pr_data)
> +{
> +	int i = 0, ret;
> +
> +	mutex_lock(&ddc->mtx);
> +
> +	regmap_set_bits(ddc->regs, HDCP2X_POL_CTRL, HDCP2X_DIS_POLL_EN);
> +	do {
> +		ret = mtk_ddc_wr_one(ddc, b_dev, data_addr + i, pr_data[i]);
> +		if (ret)
> +			break;
> +	} while (++i < data_cnt);
> +
> +	mutex_unlock(&ddc->mtx);
> +
> +	return ret;
> +}
> +
> +static int mtk_hdmi_ddc_v2_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
> +{
> +	struct mtk_hdmi_ddc *ddc;
> +	u8 offset = 0;
> +	int i, ret;
> +
> +	if (!adapter || !adapter->algo_data || !msgs)
> +		return -EINVAL;
> +
> +	ddc = adapter->algo_data;
> +
> +	for (i = 0; i < num; i++) {
> +		struct i2c_msg *msg = &msgs[i];
> +
> +		if (!msg->buf) {
> +			pr_err("XFER: No message buffer\n");
> +			return -EINVAL;
> +		}
> +
> +		if (msg->flags & I2C_M_RD) {
> +			/*
> +			 * The underlying DDC hardware always issues a write request
> +			 * that assigns the read offset as part of the read operation,
> +			 * therefore, use the `offset` value assigned in the previous
> +			 * write request from drm_edid
> +			 */
> +			ret = mtk_hdmi_fg_ddc_data_read(ddc, msg->addr, offset,
> +							msg->len, &msg->buf[0]);
> +			if (ret)
> +				return ret;
> +		} else {
> +			ret = mtk_hdmi_ddc_fg_data_write(ddc, msg->addr, msg->buf[0],
> +							 msg->len - 1, &msg->buf[1]);
> +			if (ret)
> +				return ret;
> +
> +			/*
> +			 * Store the offset value requested by drm_edid or by
> +			 * scdc to use in subsequent read requests.
> +			 */
> +			if ((msg->addr == DDC_ADDR || msg->addr == SCDC_I2C_SLAVE_ADDRESS) &&
> +			    msg->len == 1) {
> +				offset = msg->buf[0];
> +			}
> +		}
> +	}
> +
> +	return i;
> +}
> +
> +static u32 mtk_hdmi_ddc_v2_func(struct i2c_adapter *adapter)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
> +}
> +
> +static const struct i2c_algorithm mtk_hdmi_ddc_v2_algorithm = {
> +	.master_xfer = mtk_hdmi_ddc_v2_xfer,
> +	.functionality = mtk_hdmi_ddc_v2_func,
> +};
> +
> +static int mtk_hdmi_ddc_v2_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct mtk_hdmi_ddc *ddc;
> +	int ret;
> +
> +	ddc = devm_kzalloc(dev, sizeof(*ddc), GFP_KERNEL);
> +	if (!ddc)
> +		return -ENOMEM;
> +
> +	ddc->dev = dev;
> +	ddc->regs = device_node_to_regmap(dev->parent->of_node);
> +	if (IS_ERR_OR_NULL(ddc->regs))
> +		return dev_err_probe(dev,
> +				     IS_ERR(ddc->regs) ? PTR_ERR(ddc->regs) : -EINVAL,
> +				     "Cannot get regmap\n");
> +
> +	ddc->clk = devm_clk_get_enabled(dev, NULL);
> +	if (IS_ERR(ddc->clk))
> +		return dev_err_probe(dev, PTR_ERR(ddc->clk), "Cannot get DDC clock\n");
> +
> +	mutex_init(&ddc->mtx);
> +
> +	strscpy(ddc->adap.name, "mediatek-hdmi-ddc-v2", sizeof(ddc->adap.name));
> +	ddc->adap.owner = THIS_MODULE;
> +	ddc->adap.algo = &mtk_hdmi_ddc_v2_algorithm;
> +	ddc->adap.retries = 3;
> +	ddc->adap.dev.of_node = dev->of_node;
> +	ddc->adap.algo_data = ddc;
> +	ddc->adap.dev.parent = &pdev->dev;
> +
> +	ret = devm_pm_runtime_enable(&pdev->dev);
> +	if (ret)
> +		return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
> +
> +	pm_runtime_get_sync(dev);
> +
> +	ret = devm_i2c_add_adapter(dev, &ddc->adap);
> +	if (ret < 0)
> +		return dev_err_probe(dev, ret, "Cannot add DDC I2C adapter\n");
> +
> +	platform_set_drvdata(pdev, ddc);
> +	return 0;
> +}
> +
> +static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
> +	{ .compatible = "mediatek,mt8195-hdmi-ddc" },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match)
> +
> +struct platform_driver mtk_hdmi_ddc_v2_driver = {
> +	.probe = mtk_hdmi_ddc_v2_probe,
> +	.driver = {
> +		.name = "mediatek-hdmi-ddc-v2",
> +		.of_match_table = mtk_hdmi_ddc_v2_match,
> +	},
> +};
> +module_platform_driver(mtk_hdmi_ddc_v2_driver);
> +
> +MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
> +MODULE_AUTHOR("Can Zeng <can.zeng@mediatek.com>");
> +MODULE_DESCRIPTION("MediaTek HDMIv2 DDC Driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
> new file mode 100644
> index 000000000000..521b35c7e14d
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
> @@ -0,0 +1,263 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Copyright (c) 2021 BayLibre, SAS
> + * Copyright (c) 2024 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#ifndef _MTK_HDMI_REGS_H
> +#define _MTK_HDMI_REGS_H
> +
> +/* HDMI_TOP Config */
> +#define TOP_CFG00			0x000
> +#define  HDMI2_ON			BIT(2)
> +#define  HDMI_MODE_HDMI			BIT(3)
> +#define  SCR_ON				BIT(4)
> +#define  TMDS_PACK_MODE			GENMASK(9, 8)
> +#define   TMDS_PACK_MODE_8BPP		0
> +#define   TMDS_PACK_MODE_10BPP		1
> +#define   TMDS_PACK_MODE_12BPP		2
> +#define   TMDS_PACK_MODE_16BPP		3
> +#define  DEEPCOLOR_PKT_EN		BIT(12)
> +#define  HDMI_ABIST_VIDEO_FORMAT	GENMASK(21, 16)
> +#define  HDMI_ABIST_ENABLE		BIT(31)
> +#define TOP_CFG01 0x004
> +#define  CP_SET_MUTE_EN			BIT(0)
> +#define  CP_CLR_MUTE_EN			BIT(1)
> +#define  NULL_PKT_EN			BIT(2)
> +#define  NULL_PKT_VSYNC_HIGH_EN		BIT(3)
> +
> +/* HDMI_TOP Audio: Channel Mapping */
> +#define TOP_AUD_MAP			0x00c
> +#define  SD0_MAP			GENMASK(2, 0)
> +#define  SD1_MAP			GENMASK(6, 4)
> +#define  SD2_MAP			GENMASK(10, 8)
> +#define  SD3_MAP			GENMASK(14, 12)
> +#define  SD4_MAP			GENMASK(18, 16)
> +#define  SD5_MAP			GENMASK(22, 20)
> +#define  SD6_MAP			GENMASK(26, 24)
> +#define  SD7_MAP			GENMASK(30, 28)
> +
> +/* Auxiliary Video Information (AVI) Infoframe */
> +#define TOP_AVI_HEADER			0x024
> +#define TOP_AVI_PKT00			0x028
> +#define TOP_AVI_PKT01			0x02C
> +#define TOP_AVI_PKT02			0x030
> +#define TOP_AVI_PKT03			0x034
> +#define TOP_AVI_PKT04			0x038
> +#define TOP_AVI_PKT05			0x03C
> +
> +/* Audio Interface Infoframe */
> +#define TOP_AIF_HEADER			0x040
> +#define TOP_AIF_PKT00			0x044
> +#define TOP_AIF_PKT01			0x048
> +#define TOP_AIF_PKT02			0x04c
> +#define TOP_AIF_PKT03			0x050
> +
> +/* Audio SPDIF Infoframe */
> +#define TOP_SPDIF_HEADER		0x054
> +#define TOP_SPDIF_PKT00			0x058
> +#define TOP_SPDIF_PKT01			0x05c
> +#define TOP_SPDIF_PKT02			0x060
> +#define TOP_SPDIF_PKT03			0x064
> +#define TOP_SPDIF_PKT04			0x068
> +#define TOP_SPDIF_PKT05			0x06c
> +#define TOP_SPDIF_PKT06			0x070
> +#define TOP_SPDIF_PKT07			0x074
> +
> +/* Infoframes Configuration */
> +#define TOP_INFO_EN			0x01c
> +#define  AVI_EN				BIT(0)
> +#define  SPD_EN				BIT(1)
> +#define  AUD_EN				BIT(2)
> +#define  CP_EN				BIT(5)
> +#define  VSIF_EN			BIT(11)
> +#define  AVI_EN_WR			BIT(16)
> +#define  SPD_EN_WR			BIT(17)
> +#define  AUD_EN_WR			BIT(18)
> +#define  CP_EN_WR			BIT(21)
> +#define  VSIF_EN_WR			BIT(27)
> +#define TOP_INFO_RPT			0x020
> +#define  AVI_RPT_EN			BIT(0)
> +#define  SPD_RPT_EN			BIT(1)
> +#define  AUD_RPT_EN			BIT(2)
> +#define  CP_RPT_EN			BIT(5)
> +#define  VSIF_RPT_EN			BIT(11)
> +
> +/* Vendor Specific Infoframe */
> +#define TOP_VSIF_HEADER			0x174
> +#define TOP_VSIF_PKT00			0x178
> +#define TOP_VSIF_PKT01			0x17c
> +#define TOP_VSIF_PKT02			0x180
> +#define TOP_VSIF_PKT03			0x184
> +#define TOP_VSIF_PKT04			0x188
> +#define TOP_VSIF_PKT05			0x18c
> +#define TOP_VSIF_PKT06			0x190
> +#define TOP_VSIF_PKT07			0x194
> +
> +/* HDMI_TOP Misc */
> +#define TOP_MISC_CTLR			0x1a4
> +#define  DEEP_COLOR_ADD			BIT(4)
> +
> +/* Hardware interrupts */
> +#define TOP_INT_STA00			0x1a8
> +#define TOP_INT_ENABLE00		0x1b0
> +#define  HTPLG_R_INT			BIT(0)
> +#define  HTPLG_F_INT			BIT(1)
> +#define  PORD_R_INT			BIT(2)
> +#define  PORD_F_INT			BIT(3)
> +#define  HDMI_VSYNC_INT			BIT(4)
> +#define  HDMI_AUDIO_INT			BIT(5)
> +#define  HDCP2X_RX_REAUTH_REQ_DDCM_INT	BIT(25)
> +#define TOP_INT_ENABLE01		0x1b4
> +#define TOP_INT_CLR00			0x1b8
> +#define TOP_INT_CLR01			0x1bc
> +
> +
> +/* Video Mute */
> +#define TOP_VMUTE_CFG1			0x1c8
> +#define  REG_VMUTE_EN			BIT(16)
> +
> +/* HDMI Audio IP */
> +#define AIP_CTRL			0x400
> +#define  CTS_SW_SEL			BIT(0)
> +#define  CTS_REQ_EN			BIT(1)
> +#define  MCLK_EN			BIT(2)
> +#define  NO_MCLK_CTSGEN_SEL		BIT(3)
> +#define  AUD_IN_EN			BIT(8)
> +#define  AUD_SEL_OWRT			BIT(9)
> +#define  SPDIF_EN			BIT(13)
> +#define  HBRA_ON			BIT(14)
> +#define  DSD_EN				BIT(15)
> +#define  I2S_EN				GENMASK(19, 16)
> +#define  HBR_FROM_SPDIF			BIT(20)
> +#define  CTS_CAL_N4			BIT(23)
> +#define  SPDIF_INTERNAL_MODULE		BIT(24)
> +#define AIP_N_VAL			0x404
> +#define AIP_CTS_SVAL			0x408
> +#define AIP_SPDIF_CTRL			0x40c
> +#define  WR_1UI_LOCK			BIT(0)
> +#define  FS_OVERRIDE_WRITE		BIT(1)
> +#define  WR_2UI_LOCK			BIT(2)
> +#define  MAX_1UI_WRITE			GENMASK(15, 8)
> +#define  MAX_2UI_SPDIF_WRITE		GENMASK(23, 16)
> +#define  MAX_2UI_I2S_HI_WRITE		GENMASK(23, 20)
> +#define   MAX_2UI_I2S_LFE_CC_SWAP	BIT(1)
> +#define  MAX_2UI_I2S_LO_WRITE		GENMASK(19, 16)
> +#define  AUD_ERR_THRESH			GENMASK(29, 24)
> +#define  I2S2DSD_EN			BIT(30)
> +#define AIP_I2S_CTRL			0x410
> +#define  FIFO0_MAP			GENMASK(1, 0)
> +#define  FIFO1_MAP			GENMASK(3, 2)
> +#define  FIFO2_MAP			GENMASK(5, 4)
> +#define  FIFO3_MAP			GENMASK(7, 6)
> +#define  I2S_1ST_BIT_NOSHIFT		BIT(8)
> +#define  I2S_DATA_DIR_LSB		BIT(9)
> +#define  JUSTIFY_RIGHT			BIT(10)
> +#define  WS_HIGH			BIT(11)
> +#define  VBIT_COMPRESSED		BIT(12)
> +#define  CBIT_ORDER_SAME		BIT(13)
> +#define  SCK_EDGE_RISE			BIT(14)
> +#define AIP_I2S_CHST0			0x414
> +#define AIP_I2S_CHST1			0x418
> +#define AIP_TXCTRL			0x424
> +#define  RST4AUDIO			BIT(0)
> +#define  RST4AUDIO_FIFO			BIT(1)
> +#define  RST4AUDIO_ACR			BIT(2)
> +#define  AUD_LAYOUT_1			BIT(4)
> +#define  AUD_MUTE_FIFO_EN		BIT(5)
> +#define  AUD_PACKET_DROP		BIT(6)
> +#define  DSD_MUTE_EN			BIT(7)
> +#define AIP_TPI_CTRL			0x428
> +#define  TPI_AUDIO_LOOKUP_EN		BIT(2)
> +
> +/* Video downsampling configuration */
> +#define VID_DOWNSAMPLE_CONFIG		0x8d0
> +#define  C444_C422_CONFIG_ENABLE	BIT(0)
> +#define  C422_C420_CONFIG_ENABLE	BIT(4)
> +#define  C422_C420_CONFIG_BYPASS	BIT(5)
> +#define  C422_C420_CONFIG_OUT_CB_OR_CR	BIT(6)
> +#define VID_OUT_FORMAT			0x8fc
> +#define  OUTPUT_FORMAT_DEMUX_420_ENABLE	BIT(10)
> +
> +/* HDCP registers */
> +#define HDCP_TOP_CTRL			0xc00
> +#define HDCP2X_CTRL_0			0xc20
> +#define  HDCP2X_EN			BIT(0)
> +#define  HDCP2X_ENCRYPT_EN		BIT(7)
> +#define  HDCP2X_HPD_OVR			BIT(10)
> +#define  HDCP2X_HPD_SW			BIT(11)
> +#define HDCP2X_POL_CTRL			0xc54
> +#define  HDCP2X_DIS_POLL_EN		BIT(16)
> +#define HDCP1X_CTRL			0xcd0
> +#define  HDCP1X_ENC_EN			BIT(6)
> +
> +/* HDMI DDC registers */
> +#define HPD_DDC_CTRL			0xc08
> +#define  HPD_DDC_DELAY_CNT		GENMASK(31, 16)
> +#define  HPD_DDC_HPD_DBNC_EN		BIT(2)
> +#define  HPD_DDC_PORD_DBNC_EN		BIT(3)
> +#define DDC_CTRL			0xc10
> +#define  DDC_CTRL_ADDR			GENMASK(7, 1)
> +#define  DDC_CTRL_OFFSET		GENMASK(15, 8)
> +#define  DDC_CTRL_DIN_CNT		GENMASK(25, 16)
> +#define  DDC_CTRL_CMD			GENMASK(31, 28)
> +#define SCDC_CTRL			0xc18
> +#define  SCDC_DDC_SEGMENT		GENMASK(15, 8)
> +#define HPD_DDC_STATUS			0xc60
> +#define  HPD_STATE			GENMASK(1, 0)
> +#define   HPD_STATE_CONNECTED		2
> +#define  HPD_PIN_STA			BIT(4)
> +#define  PORD_PIN_STA			BIT(5)
> +#define  DDC_I2C_IN_PROG		BIT(13)
> +#define  DDC_DATA_OUT			GENMASK(23, 16)
> +#define SI2C_CTRL			0xcac
> +#define  SI2C_WR			BIT(0)
> +#define  SI2C_RD			BIT(1)
> +#define  SI2C_CONFIRM_READ		BIT(2)
> +#define  SI2C_WDATA			GENMASK(15, 8)
> +#define  SI2C_ADDR			GENMASK(23, 16)
> +
> +/* HDCP DDC registers */
> +#define HDCP2X_DDCM_STATUS		0xc68
> +#define  DDC_I2C_NO_ACK			BIT(10)
> +#define  DDC_I2C_BUS_LOW		BIT(11)
> +
> +/* HDMI TX registers */
> +#define HDMITX_CONFIG_MT8188		0xea0
> +#define HDMITX_CONFIG_MT8195		0x900
> +#define  HDMI_YUV420_MODE		BIT(10)
> +#define  HDMITX_SW_HPD			BIT(29)
> +#define  HDMITX_SW_RSTB			BIT(31)
> +
> +/**
> + * enum mtk_hdmi_ddc_v2_cmds - DDC_CMD register commands
> + * @DDC_CMD_READ_NOACK:      Current address read with no ACK on last byte
> + * @DDC_CMD_READ:            Current address read with ACK on last byte
> + * @DDC_CMD_SEQ_READ_NOACK:  Sequential read with no ACK on last byte
> + * @DDC_CMD_SEQ_READ:        Sequential read with ACK on last byte
> + * @DDC_CMD_ENH_READ_NOACK:  Enhanced read with no ACK on last byte
> + * @DDC_CMD_ENH_READ:        Enhanced read with ACK on last byte
> + * @DDC_CMD_SEQ_WRITE_NOACK: Sequential write ignoring ACK on last byte
> + * @DDC_CMD_SEQ_WRITE:       Sequential write requiring ACK on last byte
> + * @DDC_CMD_RSVD:            Reserved for future use
> + * @DDC_CMD_CLEAR_FIFO:      Clear DDC I2C FIFO
> + * @DDC_CMD_CLOCK_SCL:       Start clocking DDC I2C SCL
> + * @DDC_CMD_ABORT_XFER:      Abort DDC I2C transaction
> + */
> +enum mtk_hdmi_ddc_v2_cmds {
> +	DDC_CMD_READ_NOACK = 0x0,
> +	DDC_CMD_READ,
> +	DDC_CMD_SEQ_READ_NOACK,
> +	DDC_CMD_SEQ_READ,
> +	DDC_CMD_ENH_READ_NOACK,
> +	DDC_CMD_ENH_READ,
> +	DDC_CMD_SEQ_WRITE_NOACK,
> +	DDC_CMD_SEQ_WRITE = 0x07,
> +	DDC_CMD_CLEAR_FIFO = 0x09,
> +	DDC_CMD_CLOCK_SCL = 0x0a,
> +	DDC_CMD_ABORT_XFER = 0x0f
> +};
> +
> +#endif /* _MTK_HDMI_REGS_H */
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> new file mode 100644
> index 000000000000..05cbfc45be54
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> @@ -0,0 +1,1488 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek HDMI v2 IP driver
> + *
> + * Copyright (c) 2022 MediaTek Inc.
> + * Copyright (c) 2022 BayLibre, SAS
> + * Copyright (c) 2024 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/clk-provider.h>
> +#include <linux/clk.h>
> +#include <linux/debugfs.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_graph.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/suspend.h>
> +#include <linux/timer.h>
> +#include <linux/units.h>
> +
> +#include <drm/display/drm_hdmi_helper.h>
> +#include <drm/display/drm_hdmi_state_helper.h>
> +#include <drm/display/drm_scdc_helper.h>
> +#include <drm/drm_edid.h>
> +#include <drm/drm_print.h>
> +#include <drm/drm_probe_helper.h>
> +
> +#include "mtk_hdmi_common.h"
> +#include "mtk_hdmi_regs_v2.h"
> +
> +#define MTK_HDMI_V2_CLOCK_MIN	27000
> +#define MTK_HDMI_V2_CLOCK_MAX	594000
> +
> +#define HPD_PORD_HWIRQS		(HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)
> +
> +enum mtk_hdmi_v2_clk_id {
> +	MTK_HDMI_V2_CLK_HDCP_SEL,
> +	MTK_HDMI_V2_CLK_HDCP_24M_SEL,
> +	MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI,
> +	MTK_HDMI_V2_CLK_HDMI_APB_SEL,
> +	MTK_HDMI_V2_CLK_COUNT,
> +};
> +
> +const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] = {
> +	[MTK_HDMI_V2_CLK_HDMI_APB_SEL] = "bus",
> +	[MTK_HDMI_V2_CLK_HDCP_SEL] = "hdcp",
> +	[MTK_HDMI_V2_CLK_HDCP_24M_SEL] = "hdcp24m",
> +	[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
> +};
> +
> +static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi)
> +{
> +	regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0);
> +	regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0);
> +}
> +
> +static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	if (enable)
> +		regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
> +	else
> +		regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
> +}
> +
> +static inline void mtk_hdmi_v2_clear_hpd_pord_irq(struct mtk_hdmi *hdmi)
> +{
> +	regmap_set_bits(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS);
> +	regmap_clear_bits(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS);
> +}
> +
> +static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	if (enable) {
> +		regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
> +		regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
> +		regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
> +	} else {
> +		regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
> +		regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
> +		regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
> +	}
> +}
> +
> +static void mtk_hdmi_v2_disable_hdcp_encrypt(struct mtk_hdmi *hdmi)
> +{
> +	regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_ENCRYPT_EN);
> +	regmap_clear_bits(hdmi->regs, HDCP1X_CTRL, HDCP1X_ENC_EN);
> +}
> +
> +static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc;
> +
> +	if (enable)
> +		regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
> +	else
> +		regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
> +
> +	if (scdc->supported) {
> +		if (scdc->scrambling.supported)
> +			drm_scdc_set_scrambling(hdmi->curr_conn, enable);
> +		drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable);
> +	}
> +}
> +
> +static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	/* If enabled, sends a black image */
> +	if (enable)
> +		regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
> +	else
> +		regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
> +}
> +
> +static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	u32 aip, val;
> +
> +	if (!enable) {
> +		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN);
> +		return;
> +	}
> +
> +	regmap_read(hdmi->regs, AIP_CTRL, &aip);
> +
> +	val = AUD_MUTE_FIFO_EN;
> +	if (aip & DSD_EN)
> +		val |= DSD_MUTE_EN;
> +
> +	regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val);
> +}
> +
> +static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi)
> +{
> +	regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
> +	udelay(5);
> +	regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
> +}
> +
> +static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len)
> +{
> +	unsigned short i;
> +	u32 val = 0;
> +
> +	for (i = 0; i < len; i++)
> +		val |= buffer[i] << (i * 8);
> +
> +	return val;
> +}
> +
> +static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
> +{
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
> +
> +	regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
> +	regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3));
> +	regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
> +	regmap_write(hdmi->regs, TOP_AIF_PKT02, 0);
> +	regmap_write(hdmi->regs, TOP_AIF_PKT03, 0);
> +
> +	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
> +	regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
> +}
> +
> +static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
> +{
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
> +
> +	regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
> +	regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
> +	regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
> +	regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
> +	regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
> +	regmap_write(hdmi->regs, TOP_AVI_PKT04, 0);
> +	regmap_write(hdmi->regs, TOP_AVI_PKT05, 0);
> +
> +	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
> +	regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
> +}
> +
> +static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
> +{
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
> +
> +	regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4));
> +	regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]);
> +
> +	regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
> +	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
> +}
> +
> +static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
> +{
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
> +
> +	regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3));
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4));
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2));
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0);
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0);
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0);
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0);
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0);
> +	regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0);
> +
> +	regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
> +	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
> +}
> +
> +static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	u32 val;
> +
> +	regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val);
> +
> +	if (enable) {
> +		regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg,
> +				HDMI_YUV420_MODE | HDMITX_SW_HPD);
> +
> +		val |= C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE;
> +		val |= C422_C420_CONFIG_OUT_CB_OR_CR;
> +		val &= ~C422_C420_CONFIG_BYPASS;
> +		regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
> +
> +		regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
> +	} else {
> +		regmap_update_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg,
> +				   HDMI_YUV420_MODE | HDMITX_SW_HPD, HDMITX_SW_HPD);
> +
> +		val &= ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE);
> +		val &= ~C422_C420_CONFIG_OUT_CB_OR_CR;
> +		val |= C422_C420_CONFIG_BYPASS;
> +		regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
> +
> +		regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
> +	}
> +}
> +
> +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
> +{
> +	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
> +	struct hdmi_audio_infoframe frame;
> +	u8 buffer[14];
> +	ssize_t ret;
> +
> +	memcpy(&frame, &params->cea, sizeof(frame));
> +
> +	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
> +	if (ret < 0)
> +		return ret;
> +
> +	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);

This should be handled via HDMI Connector framework too. There is
already an interface to set / clear audio infoframes.
als I have been working on an interface to make HDMI codec
implementation more generic, see [1]. Your comments are appreciated.

[1] https://patchwork.freedesktop.org/series/134927/

> +
> +	return 0;
> +}
> +
> +static inline void mtk_hdmi_v2_hw_reset_av_mute_regs(struct mtk_hdmi *hdmi)
> +{
> +	/* GCP packet */
> +	regmap_clear_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN | CP_SET_MUTE_EN);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
> +	regmap_clear_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_av_mute(struct mtk_hdmi *hdmi, bool mute)
> +{
> +	mtk_hdmi_v2_hw_reset_av_mute_regs(hdmi);
> +
> +	if (mute)
> +		regmap_set_bits(hdmi->regs, TOP_CFG01, CP_SET_MUTE_EN);
> +	else
> +		regmap_set_bits(hdmi->regs, TOP_CFG01, CP_CLR_MUTE_EN);
> +
> +	regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
> +	regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
> +}
> +
> +static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	if (enable)
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
> +	else
> +		regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL);
> +}
> +
> +static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi, u8 *ch_status)
> +{
> +	/* Only the first 5 to 7 bytes of Channel Status contain useful information */
> +	regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4));
> +	regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3));
> +}
> +
> +static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
> +				     unsigned int sample_rate,
> +				     unsigned int clock)
> +{
> +	unsigned int n, cts;
> +	int ret;
> +
> +	ret = mtk_hdmi_get_ncts(sample_rate, clock, &n, &cts);
> +	if (ret) {
> +		dev_err(hdmi->dev, "Invalid sample rate: %u\n", sample_rate);
> +		return;
> +	}
> +
> +	regmap_write(hdmi->regs, AIP_N_VAL, n);
> +	regmap_write(hdmi->regs, AIP_CTS_SVAL, cts);
> +}
> +
> +static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	if (enable)
> +		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
> +	else
> +		regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
> +}
> +
> +static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 sd3,
> +					   u8 sd4, u8 sd5, u8 sd6, u8 sd7)
> +{
> +	u32 val;
> +
> +	/*
> +	 * Each of the Output Channels (0-7) can be mapped to get their input
> +	 * from any of the available Input Channels (0-7): this function
> +	 * takes input channel numbers and formats a value that must then
> +	 * be written to the TOP_AUD_MAP hardware register by the caller.
> +	 */
> +	val = FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1);
> +	val |= FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3);
> +	val |= FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5);
> +	val |= FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7);
> +
> +	return val;
> +}
> +
> +static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi,
> +				      unsigned char chnum, bool dsd_bypass)
> +{
> +	u32 channel_map;
> +
> +	regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN);
> +	regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN);
> +
> +	if (dsd_bypass)
> +		channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 2, 4, 6, 1, 3, 5, 7);
> +	else
> +		channel_map = mtk_hdmi_v2_aud_output_channel_map(0, 5, 1, 0, 3, 2, 4, 0);
> +
> +	regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map);
> +	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL,
> +			   FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, fifo_mapping);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum));
> +}
> +
> +static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping)
> +{
> +	u32 fifo_map;
> +	u8 bdata;
> +
> +	switch (chnum) {
> +	default:
> +	case 2:
> +		bdata = 0x1;
> +		break;
> +	case 3:
> +		bdata = 0x3;
> +		break;
> +	case 6:
> +		if (mapping == 0x0e) {
> +			bdata = 0xf;
> +			break;
> +		}
> +		fallthrough;
> +	case 5:
> +		bdata = 0x7;
> +		break;
> +	case 7:
> +	case 8:
> +		bdata = 0xf;
> +		break;
> +	}
> +
> +	/* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */
> +	fifo_map = FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1);
> +	fifo_map |= FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3);
> +	mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map);
> +	mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata);
> +
> +	/*
> +	 * Set HDMI Audio packet layout indicator:
> +	 * Layout 0 is for two channels
> +	 * Layout 1 is for up to eight channels
> +	 */
> +	if (chnum == 2)
> +		regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
> +	else
> +		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
> +}
> +
> +static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt)
> +{
> +	u32 val;
> +
> +	regmap_read(hdmi->regs, AIP_I2S_CTRL, &val);
> +	val &= ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
> +
> +	switch (fmt) {
> +	case HDMI_I2S_MODE_RJT_24BIT:
> +	case HDMI_I2S_MODE_RJT_16BIT:
> +		val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
> +		break;
> +	case HDMI_I2S_MODE_LJT_24BIT:
> +	case HDMI_I2S_MODE_LJT_16BIT:
> +		val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT);
> +		break;
> +	case HDMI_I2S_MODE_I2S_24BIT:
> +	case HDMI_I2S_MODE_I2S_16BIT:
> +	default:
> +		break;
> +	}
> +
> +	regmap_write(hdmi->regs, AIP_I2S_CTRL, val);
> +}
> +
> +static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise)
> +{
> +	if (rise)
> +		regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
> +	else
> +		regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
> +}
> +
> +static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit);
> +}
> +
> +static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit)
> +{
> +	/* V bit: 0 for PCM, 1 for Compressed data */
> +	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit);
> +}
> +
> +static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s));
> +}
> +
> +static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type)
> +{
> +	switch (channel_type) {
> +	case HDMI_AUD_CHAN_TYPE_1_1:
> +	case HDMI_AUD_CHAN_TYPE_2_1:
> +		return 0x01;
> +	case HDMI_AUD_CHAN_TYPE_3_0:
> +		return 0x02;
> +	case HDMI_AUD_CHAN_TYPE_3_1:
> +		return 0x03;
> +	case HDMI_AUD_CHAN_TYPE_3_0_LRS:
> +	case HDMI_AUD_CHAN_TYPE_4_0:
> +		return 0x08;
> +	case HDMI_AUD_CHAN_TYPE_5_1:
> +		return 0x0b;
> +	case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
> +	case HDMI_AUD_CHAN_TYPE_6_0:
> +	case HDMI_AUD_CHAN_TYPE_6_0_CS:
> +	case HDMI_AUD_CHAN_TYPE_6_0_CH:
> +	case HDMI_AUD_CHAN_TYPE_6_0_OH:
> +	case HDMI_AUD_CHAN_TYPE_6_0_CHR:
> +		return 0x0e;
> +	case HDMI_AUD_CHAN_TYPE_1_0:
> +	case HDMI_AUD_CHAN_TYPE_2_0:
> +	case HDMI_AUD_CHAN_TYPE_3_1_LRS:
> +	case HDMI_AUD_CHAN_TYPE_4_1:
> +	case HDMI_AUD_CHAN_TYPE_5_0:
> +	case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
> +	case HDMI_AUD_CHAN_TYPE_6_1:
> +	case HDMI_AUD_CHAN_TYPE_6_1_CS:
> +	case HDMI_AUD_CHAN_TYPE_6_1_CH:
> +	case HDMI_AUD_CHAN_TYPE_6_1_OH:
> +	case HDMI_AUD_CHAN_TYPE_6_1_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_0:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
> +	case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
> +	case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
> +	case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
> +	case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
> +	case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
> +	case HDMI_AUD_CHAN_TYPE_7_1:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
> +	case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
> +	case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
> +	case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
> +	case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
> +	case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
> +	default:
> +		return 0;
> +	}
> +
> +	return 0;
> +}
> +
> +static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi, unsigned char swapbit)
> +{
> +	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE,
> +			   FIELD_PREP(MAX_2UI_I2S_HI_WRITE, swapbit));
> +}
> +
> +static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass)
> +{
> +	const u32 hbr_mask = SPDIF_EN | DSD_EN | HBRA_ON;
> +
> +	if (dsd_bypass) {
> +		regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON);
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN);
> +	} else {
> +		regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN);
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE);
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF);
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4);
> +	}
> +}
> +
> +static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi)
> +{
> +	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK);
> +	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE);
> +	regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK);
> +
> +	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE,
> +			   FIELD_PREP(MAX_1UI_WRITE, 4));
> +	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE,
> +			   FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9));
> +	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH,
> +			   FIELD_PREP(AUD_ERR_THRESH, 4));
> +
> +	regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
> +}
> +
> +static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi)
> +{
> +	struct hdmi_audio_param *aud_param = &hdmi->aud_param;
> +	u8 i2s_ch_map;
> +	u32 out_ch_map;
> +
> +	/* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1, etc */
> +	out_ch_map = mtk_hdmi_v2_aud_output_channel_map(0, 1, 2, 3, 4, 5, 6, 7);
> +	regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map);
> +
> +	regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0);
> +	regmap_clear_bits(hdmi->regs, AIP_CTRL,
> +			  SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 |
> +			  HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE);
> +	regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1);
> +
> +	if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) {
> +		switch (aud_param->aud_codec) {
> +		case HDMI_AUDIO_CODING_TYPE_DTS_HD:
> +		case HDMI_AUDIO_CODING_TYPE_MLP:
> +			mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
> +			mtk_hdmi_hbr_config(hdmi, true);
> +			break;
> +		case HDMI_AUDIO_CODING_TYPE_DSD:
> +			mtk_hdmi_audio_dsd_config(hdmi, aud_param->codec_params.channels, 0);
> +			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, aud_param->codec_params.channels, 1);
> +			break;
> +		default:
> +			mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt);
> +			mtk_hdmi_i2s_sck_edge_rise(hdmi, true);
> +			mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME);
> +			mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */
> +			mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */
> +			mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S);
> +			i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi,
> +						aud_param->aud_input_chan_type);
> +			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi,
> +						aud_param->codec_params.channels, i2s_ch_map);
> +			mtk_hdmi_v2_hw_i2s_ch_swap(hdmi, MAX_2UI_I2S_LFE_CC_SWAP);
> +		}
> +	} else {
> +		if (aud_param->codec_params.sample_rate == 768000 &&
> +		    (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD ||
> +		     aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) {
> +			mtk_hdmi_hbr_config(hdmi, false);
> +		} else {
> +			mtk_hdmi_v2_hw_spdif_config(hdmi);
> +			mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0);
> +		}
> +	}
> +}
> +
> +static void mtk_hdmi_v2_aud_set_sw_ncts(struct mtk_hdmi *hdmi,
> +				     struct drm_display_mode *display_mode)
> +{
> +	mtk_hdmi_v2_hw_ncts_enable(hdmi, false);
> +	mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate,
> +				 display_mode->clock);
> +}
> +
> +static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi,
> +						  unsigned int enable)
> +{
> +	if (enable)
> +		regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
> +	else
> +		regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN);
> +}
> +
> +static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi)
> +{
> +	regmap_set_bits(hdmi->regs, AIP_CTRL,
> +			AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN);
> +	regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN);
> +}
> +
> +static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset)
> +{
> +	const u32 arst_bits = RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR;
> +
> +	if (reset)
> +		regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
> +	else
> +		regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits);
> +}
> +
> +static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi,
> +				       struct drm_display_mode *display_mode)
> +{
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
> +	mtk_hdmi_v2_hw_aud_enable(hdmi, false);
> +	mtk_hdmi_v2_audio_reset(hdmi, true);
> +	mtk_hdmi_v2_aip_ctrl_init(hdmi);
> +	mtk_hdmi_v2_aud_set_input(hdmi);
> +	mtk_hdmi_v2_hw_aud_set_channel_status(hdmi, hdmi->aud_param.codec_params.iec.status);
> +	mtk_hdmi_v2_setup_audio_infoframe(hdmi);
> +	mtk_hdmi_v2_hw_audio_input_enable(hdmi, true);
> +	mtk_hdmi_v2_audio_reset(hdmi, false);
> +	mtk_hdmi_v2_aud_set_sw_ncts(hdmi, display_mode);
> +
> +	/* Wait for the HW to apply settings */
> +	usleep_range(25, 50);
> +
> +	mtk_hdmi_v2_hw_ncts_enable(hdmi, true);
> +	mtk_hdmi_v2_hw_aud_enable(hdmi, true);
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
> +}
> +
> +static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi)
> +{
> +	mtk_hdmi_v2_hw_reset(hdmi);
> +	mtk_hdmi_v2_set_sw_hpd(hdmi, true);
> +	udelay(2);
> +
> +	regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0);
> +
> +	/* Enable HDCP reauthentication interrupt */
> +	regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);
> +
> +	/* Enable hotplug and pord interrupts */
> +	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
> +
> +	/* Force enabling HDCP HPD */
> +	regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
> +	regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
> +
> +	/* Set 8 bits per pixel */
> +	regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE,
> +			   FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP));
> +	/* Disable generating deepcolor packets */
> +	regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN);
> +	/* Disable adding deepcolor information to the general packet */
> +	regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD);
> +
> +	if (hdmi->dvi_mode)
> +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
> +	else
> +		regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
> +
> +	udelay(5);
> +	mtk_hdmi_v2_hw_vid_mute(hdmi, true);
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
> +	mtk_hdmi_v2_hw_av_mute(hdmi, false);
> +
> +	regmap_update_bits(hdmi->regs, TOP_CFG01,
> +			   NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN);
> +	usleep_range(100, 150);
> +
> +	/* Enable scrambling if tmds clock is 340MHz or more */
> +	mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO);
> +
> +	/* Disable YUV420 downsampling */
> +	mtk_hdmi_yuv420_downsampling(hdmi, false);
> +}
> +
> +static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi,
> +						struct drm_display_mode *mode)
> +{
> +	union phy_configure_opts opts = {
> +		.dp = { .link_rate = hdmi->mode.clock * KILO }
> +	};
> +	int ret;
> +
> +	ret = phy_configure(hdmi->phy, &opts);
> +	if (ret)
> +		dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret);
> +
> +	mtk_hdmi_v2_change_video_resolution(hdmi);
> +	mtk_hdmi_v2_aud_output_config(hdmi, mode);
> +}
> +
> +static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi)
> +{
> +	int ret;
> +
> +	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
> +	if (ret)
> +		return ret;
> +
> +	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
> +	if (ret)
> +		goto disable_hdcp_clk;
> +
> +	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
> +	if (ret)
> +		goto disable_hdcp_24m_clk;
> +
> +	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
> +	if (ret)
> +		goto disable_bus_clk;
> +
> +	return 0;
> +
> +disable_bus_clk:
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
> +disable_hdcp_24m_clk:
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
> +disable_hdcp_clk:
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
> +
> +	return ret;
> +}
> +
> +static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi)
> +{
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
> +	clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
> +}
> +
> +static void mtk_hdmi_hpd_event(enum hdmi_hpd_state hpd, struct device *dev)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev)
> +		drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
> +}
> +
> +static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi)
> +{
> +	u8 hpd_pin_sta, pord_pin_sta;
> +	u32 hpd_status;
> +
> +	regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status);
> +	hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status);
> +	pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status);
> +
> +	if (hpd_pin_sta && pord_pin_sta)
> +		return HDMI_PLUG_IN_AND_SINK_POWER_ON;
> +	else if (hpd_pin_sta)
> +		return HDMI_PLUG_IN_ONLY;
> +	else
> +		return HDMI_PLUG_OUT;
> +}
> +
> +static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg)
> +{
> +	struct mtk_hdmi *hdmi = arg;
> +	unsigned int irq_sta;
> +	int ret = IRQ_HANDLED;
> +
> +	regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta);
> +
> +	/* Handle Hotplug Detection interrupt */
> +	if (irq_sta & (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)) {
> +		mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false);
> +		ret = IRQ_WAKE_THREAD;
> +	}
> +
> +	/*
> +	 * Clear all 32 + 19 interrupts in CLR00 and CLR01: this is important
> +	 * to avoid unwanted retriggering of any interrupts
> +	 */
> +	regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));
> +	regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));
> +
> +	/* Restore interrupt clearing registers to zero */
> +	regmap_write(hdmi->regs, TOP_INT_CLR00, 0);
> +	regmap_write(hdmi->regs, TOP_INT_CLR01, 0);
> +
> +	return ret;
> +}
> +
> +static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi)
> +{
> +	enum hdmi_hpd_state hpd;
> +
> +	hpd = mtk_hdmi_v2_hpd_pord_status(hdmi);
> +	if (hpd != hdmi->hpd) {
> +		hdmi->hpd = hpd;
> +		mtk_hdmi_hpd_event(hpd, hdmi->dev);
> +	}
> +
> +	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg)
> +{
> +	struct mtk_hdmi *hdmi = arg;
> +
> +	/*
> +	 * Debounce HDMI monitor HPD status.
> +	 * Empirical testing shows that 30ms is enough wait
> +	 */
> +	msleep(30);
> +
> +	return __mtk_hdmi_v2_isr_thread(hdmi);
> +}
> +
> +static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi)
> +{
> +	int ret;
> +
> +	ret = pm_runtime_resume_and_get(hdmi->dev);
> +	if (ret) {
> +		dev_err(hdmi->dev, "Cannot resume HDMI\n");
> +		return ret;
> +	}
> +
> +	mtk_hdmi_v2_clk_enable(hdmi);
> +	mtk_hdmi_v2_hw_reset(hdmi);
> +	mtk_hdmi_v2_set_sw_hpd(hdmi, true);
> +
> +	return 0;
> +}
> +
> +/*
> + * Bridge callbacks
> + */
> +
> +static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge,
> +				     enum drm_bridge_attach_flags flags)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +	int ret;
> +
> +	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> +		DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n");
> +		return -EINVAL;
> +	}
> +	if (hdmi->next_bridge) {
> +		ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge, bridge, flags);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	/* Enable the controller at attach time for HPD/Pord feedback */
> +	ret = mtk_hdmi_v2_enable(hdmi);
> +	if (ret)
> +		return ret;

This looks like a hack. Please use .hpd_enable() / .hpd_disable()
callbacks.

> +
> +	/* Enable Hotplug and Pord pins internal debouncing */
> +	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
> +			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
> +
> +	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
> +	enable_irq(hdmi->irq);
> +
> +	/*
> +	 * Check if any HDMI monitor was connected before probing this driver
> +	 * and/or attaching the bridge, without debouncing: if so, we want to
> +	 * notify the DRM so that we start outputting an image ASAP.
> +	 * Note that calling the ISR thread function will also perform a HW
> +	 * registers write that enables both the HPD and Pord interrupts.
> +	 */
> +	__mtk_hdmi_v2_isr_thread(hdmi);
> +
> +	return 0;
> +}
> +
> +static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +	/* Disable interrupts */
> +	mtk_hdmi_v2_hwirq_disable(hdmi);
> +	disable_irq(hdmi->irq);
> +	pm_runtime_put_sync(hdmi->dev);
> +}
> +
> +static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged)
> +{
> +	mutex_lock(&hdmi->update_plugged_status_lock);
> +	if (hdmi->plugged_cb && hdmi->codec_dev)
> +		hdmi->plugged_cb(hdmi->codec_dev, plugged);
> +	mutex_unlock(&hdmi->update_plugged_status_lock);
> +}
> +
> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
> +					  struct drm_bridge_state *old_state)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +	struct drm_atomic_state *state = old_state->base.state;
> +	struct drm_connector_state *conn_state;
> +	union phy_configure_opts opts = {
> +		.dp = { .link_rate = hdmi->mode.clock * KILO }
> +	};
> +
> +	/* Retrieve the connector through the atomic state */
> +	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
> +
> +	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
> +	if (WARN_ON(!conn_state))
> +		return;
> +
> +	/*
> +	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
> +	 * stage to make sure that this IP is ready and clocked before the
> +	 * mtk_dpi gets powered on and before it enables the output.
> +	 */
> +	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;

Can you access display_info directly instead?

> +	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
> +
> +	/* Reconfigure phy clock link with appropriate rate */
> +	phy_configure(hdmi->phy, &opts);
> +
> +	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
> +	phy_power_on(hdmi->phy);
> +
> +	hdmi->powered = true;
> +}
> +
> +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
> +				      struct drm_bridge_state *old_state)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +	struct drm_atomic_state *state = old_state->base.state;
> +	int ret;
> +
> +	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
> +	if (ret)
> +		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
> +
> +	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
> +
> +	/* signal the connect event to audio codec */
> +	mtk_hdmi_v2_handle_plugged_change(hdmi, true);

I think it was agreed that this should be called from the hotplug path,
see the (linked) HDMI codec infrastructure patchset and dicussions for
the previous revisions.

> +
> +	hdmi->enabled = true;
> +}
> +
> +static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge,
> +				       struct drm_bridge_state *old_bridge_state)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +	if (!hdmi->enabled)
> +		return;
> +
> +	mtk_hdmi_v2_hw_av_mute(hdmi, true);
> +	msleep(50);
> +	mtk_hdmi_v2_hw_vid_mute(hdmi, true);
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, true);
> +	mtk_hdmi_v2_disable_hdcp_encrypt(hdmi);
> +	msleep(50);
> +
> +	hdmi->enabled = false;
> +}
> +
> +static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge,
> +					    struct drm_bridge_state *old_state)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +	if (!hdmi->powered)
> +		return;
> +
> +	/* Disable VSync interrupt */
> +	regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HDMI_VSYNC_INT);
> +
> +	phy_power_off(hdmi->phy);
> +	hdmi->powered = false;
> +
> +	/* signal the disconnect event to audio codec */
> +	mtk_hdmi_v2_handle_plugged_change(hdmi, false);
> +}
> +
> +static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +	return hdmi->hpd != HDMI_PLUG_OUT ?
> +	       connector_status_connected : connector_status_disconnected;
> +}
> +
> +static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge,
> +							   struct drm_connector *connector)
> +{
> +	return drm_edid_read(connector);
> +}
> +
> +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
> +						 const struct drm_display_mode *mode,
> +						 unsigned long long tmds_rate)
> +{
> +	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
> +		return MODE_CLOCK_LOW;
> +	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
> +		return MODE_CLOCK_HIGH;
> +	else
> +		return MODE_OK;
> +}
> +
> +static enum drm_mode_status
> +mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
> +			      const struct drm_display_info *info,
> +			      const struct drm_display_mode *mode)
> +{
> +	unsigned long long rate;
> +
> +	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> +	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
> +}

Please rebase on top of https://patchwork.freedesktop.org/series/140193/
There should be no need to do this manually.

> +
> +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
> +					    enum hdmi_infoframe_type type)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +	u32 reg_start, reg_end;
> +
> +	switch (type) {
> +	case HDMI_INFOFRAME_TYPE_AUDIO:
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
> +		reg_start = TOP_AIF_HEADER;
> +		reg_end = TOP_AIF_PKT03;
> +		break;
> +	case HDMI_INFOFRAME_TYPE_AVI:
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
> +		reg_start = TOP_AVI_HEADER;
> +		reg_end = TOP_AVI_PKT05;
> +		break;
> +	case HDMI_INFOFRAME_TYPE_SPD:
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
> +		reg_start = TOP_SPDIF_HEADER;
> +		reg_end = TOP_SPDIF_PKT07;
> +		break;
> +	case HDMI_INFOFRAME_TYPE_VENDOR:
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
> +		reg_start = TOP_VSIF_HEADER;
> +		reg_end = TOP_VSIF_PKT07;
> +		break;
> +	case HDMI_INFOFRAME_TYPE_DRM:
> +	default:
> +		return 0;
> +	};
> +
> +	for (; reg_start <= reg_end; reg_start += 4)
> +		regmap_write(hdmi->regs, reg_start, 0);

Interesting. Usually sending of the infoframe is controlled by a
register of a kind.

> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
> +					    enum hdmi_infoframe_type type,
> +					    const u8 *buffer, size_t len)
> +{
> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +
> +	switch (type) {
> +	case HDMI_INFOFRAME_TYPE_AUDIO:
> +		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> +		break;
> +	case HDMI_INFOFRAME_TYPE_AVI:
> +		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
> +		break;
> +	case HDMI_INFOFRAME_TYPE_SPD:
> +		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
> +		break;
> +	case HDMI_INFOFRAME_TYPE_VENDOR:
> +		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
> +		break;
> +	case HDMI_INFOFRAME_TYPE_DRM:
> +	default:
> +		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
> +		break;
> +	};
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> +					   struct drm_bridge_state *bridge_state,
> +					   struct drm_crtc_state *crtc_state,
> +					   struct drm_connector_state *conn_state)
> +{
> +	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> +						      conn_state->state);
> +}

Note to myself, probably we can move this to drm_bridge_connector too.

> +
> +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
> +{
> +	struct drm_display_mode *mode = &hdmi->mode;
> +	int abist_format = -EINVAL;
> +	bool interlaced;
> +
> +	if (!enable) {
> +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
> +		return 0;
> +	}
> +
> +	if (!mode->hdisplay || !mode->vdisplay)
> +		return -EINVAL;
> +
> +	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;

The interlaced modes should be filtered, unless you also set
bridge->interlace_allowed to true.

> +
> +	switch (mode->hdisplay) {
> +	case 720:
> +		if (mode->vdisplay == 480)
> +			abist_format = 2;
> +		else if (mode->vdisplay == 576)
> +			abist_format = 11;
> +		break;
> +	case 1280:
> +		if (mode->vdisplay == 720)
> +			abist_format = 3;
> +		break;
> +	case 1440:
> +		if (mode->vdisplay == 480)
> +			abist_format = interlaced ? 5 : 9;
> +		else if (mode->vdisplay == 576)
> +			abist_format = interlaced ? 14 : 18;
> +		break;
> +	case 1920:
> +		if (mode->vdisplay == 1080)
> +			abist_format = interlaced ? 4 : 10;
> +		break;
> +	case 3840:
> +		if (mode->vdisplay == 2160)
> +			abist_format = 25;
> +		break;
> +	case 4096:
> +		if (mode->vdisplay == 2160)
> +			abist_format = 26;
> +		break;
> +	default:
> +		break;
> +	}
> +	if (!abist_format)
> +		return -EINVAL;
> +
> +	regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT,
> +			   FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format));
> +	regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
> +	return 0;
> +}
> +
> +static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg)
> +{
> +	struct mtk_hdmi *hdmi = m->private;
> +	bool en;
> +	u32 val;
> +	int ret;
> +
> +	if (!hdmi)
> +		return -EINVAL;
> +
> +	ret = regmap_read(hdmi->regs, TOP_CFG00, &val);
> +	if (ret)
> +		return ret;
> +
> +	en = FIELD_GET(HDMI_ABIST_ENABLE, val);
> +
> +	seq_printf(m, "HDMI Automated Built-In Self Test: %s\n",
> +		   en ? "Enabled" : "Disabled");
> +
> +	return 0;
> +}
> +
> +static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file,
> +					     const char __user *ubuf,
> +					     size_t len, loff_t *offp)
> +{
> +	struct seq_file *m = file->private_data;
> +	int ret;
> +	u32 en;
> +
> +	if (!m || !m->private || *offp)
> +		return -EINVAL;
> +
> +	ret = kstrtouint_from_user(ubuf, len, 0, &en);
> +	if (ret)
> +		return ret;
> +
> +	if (en < 0 || en > 1)
> +		return -EINVAL;
> +
> +	mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en);
> +	return len;
> +}
> +
> +static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *file)
> +{
> +	return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private);
> +}
> +
> +static const struct file_operations mtk_hdmi_debug_abist_fops = {
> +	.owner = THIS_MODULE,
> +	.open = mtk_hdmi_v2_debug_abist_open,
> +	.read = seq_read,
> +	.write = mtk_hdmi_v2_debug_abist_write,
> +	.llseek = seq_lseek,
> +	.release = single_release,
> +};
> +
> +static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
> +{
> +	struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(bridge);
> +
> +	debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_fops);
> +}
> +
> +static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
> +	.attach = mtk_hdmi_v2_bridge_attach,
> +	.detach = mtk_hdmi_v2_bridge_detach,
> +	.mode_fixup = mtk_hdmi_bridge_mode_fixup,
> +	.mode_set = mtk_hdmi_bridge_mode_set,
> +	.mode_valid = mtk_hdmi_v2_bridge_mode_valid,
> +	.atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable,
> +	.atomic_enable = mtk_hdmi_v2_bridge_enable,
> +	.atomic_disable = mtk_hdmi_v2_bridge_disable,
> +	.atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
> +	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> +	.atomic_check = mtk_hdmi_v2_bridge_atomic_check,
> +	.atomic_reset = drm_atomic_helper_bridge_reset,
> +	.detect = mtk_hdmi_v2_bridge_detect,
> +	.edid_read = mtk_hdmi_v2_bridge_edid_read,
> +	.hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
> +	.hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
> +	.hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
> +	.debugfs_init = mtk_hdmi_v2_debugfs_init,
> +};
> +
> +/*
> + * HDMI audio codec callbacks
> + */
> +static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *data,
> +					     hdmi_codec_plugged_cb fn,
> +					     struct device *codec_dev)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +	bool plugged;
> +
> +	if (!hdmi)
> +		return -ENODEV;
> +
> +	mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
> +	plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON);
> +	mtk_hdmi_v2_handle_plugged_change(hdmi, plugged);
> +
> +	return 0;
> +}
> +
> +static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data,
> +				       struct hdmi_codec_daifmt *daifmt,
> +				       struct hdmi_codec_params *params)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	if (hdmi->audio_enable) {
> +		mtk_hdmi_audio_params(hdmi, daifmt, params);
> +		mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode);
> +	}
> +	return 0;
> +}
> +
> +static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	mtk_hdmi_v2_hw_aud_enable(hdmi, true);
> +	hdmi->audio_enable = true;
> +
> +	return 0;
> +}
> +
> +static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	hdmi->audio_enable = false;
> +	mtk_hdmi_v2_hw_aud_enable(hdmi, false);
> +}
> +
> +static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool enable, int dir)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	mtk_hdmi_v2_hw_aud_mute(hdmi, enable);
> +
> +	return 0;
> +}
> +
> +static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = {
> +	.hw_params = mtk_hdmi_v2_audio_hw_params,
> +	.audio_startup = mtk_hdmi_v2_audio_startup,
> +	.audio_shutdown = mtk_hdmi_v2_audio_shutdown,
> +	.mute_stream = mtk_hdmi_v2_audio_mute,
> +	.get_eld = mtk_hdmi_audio_get_eld,
> +	.hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb,
> +};
> +
> +static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +
> +	mtk_hdmi_v2_hwirq_disable(hdmi);
> +	mtk_hdmi_v2_clk_disable(hdmi);
> +	pm_runtime_put_sync(dev);
> +
> +	return 0;
> +}
> +
> +static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev)
> +{
> +	struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
> +	int ret;
> +
> +	pm_runtime_get_sync(dev);
> +
> +	ret = mtk_hdmi_v2_clk_enable(hdmi);
> +	if (ret)
> +		return ret;
> +
> +	mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true);
> +
> +	return 0;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi_v2_resume);
> +
> +static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 = {
> +	.bridge_funcs = &mtk_v2_hdmi_bridge_funcs,
> +	.codec_ops = &mtk_hdmi_v2_audio_codec_ops,
> +	.mtk_hdmi_clock_names = mtk_hdmi_v2_clk_names,
> +	.num_clocks = MTK_HDMI_V2_CLK_COUNT
> +};
> +
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 = {
> +	.ver_conf = &mtk_hdmi_conf_v2,
> +	.reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8188
> +};
> +
> +static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = {
> +	.ver_conf = &mtk_hdmi_conf_v2,
> +	.reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8195,
> +};
> +
> +static int mtk_hdmi_v2_probe(struct platform_device *pdev)
> +{
> +	struct mtk_hdmi *hdmi;
> +	int ret;
> +
> +	hdmi = mtk_hdmi_common_probe(pdev);
> +	if (IS_ERR(hdmi))
> +		return PTR_ERR(hdmi);
> +
> +	hdmi->hpd = HDMI_PLUG_OUT;
> +
> +	/*
> +	 * Disable all HW interrupts at probe stage and install the ISR
> +	 * but keep it disabled, as the rest of the interrupts setup is
> +	 * done in the .bridge_attach() callback, which will enable both
> +	 * the right HW IRQs and the ISR.
> +	 */
> +	mtk_hdmi_v2_hwirq_disable(hdmi);
> +	irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN);
> +	ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr,
> +					mtk_hdmi_v2_isr_thread,
> +					IRQ_TYPE_LEVEL_HIGH,
> +					dev_name(&pdev->dev), hdmi);
> +	if (ret)
> +		return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n");
> +
> +	ret = devm_pm_runtime_enable(&pdev->dev);
> +	if (ret)
> +		return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n");
> +
> +	return 0;
> +}
> +
> +static void mtk_hdmi_v2_remove(struct platform_device *pdev)
> +{
> +	struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
> +
> +	pm_runtime_disable(&pdev->dev);
> +	i2c_put_adapter(hdmi->ddc_adpt);
> +}
> +
> +static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] = {
> +	{ .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
> +	{ .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
> +	{ /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids);
> +
> +static struct platform_driver mtk_hdmi_v2_driver = {
> +	.probe = mtk_hdmi_v2_probe,
> +	.remove = mtk_hdmi_v2_remove,
> +	.driver = {
> +		.name = "mediatek-drm-hdmi-v2",
> +		.of_match_table = mtk_drm_hdmi_v2_of_ids,
> +		.pm = &mtk_hdmi_v2_pm_ops,
> +	},
> +};
> +module_platform_driver(mtk_hdmi_v2_driver);
> +
> +MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>>");
> +MODULE_AUTHOR("Guillaume Ranquet <granquet@baylibre.com>");
> +MODULE_DESCRIPTION("MediaTek HDMIv2 Driver");
> +MODULE_LICENSE("GPL");
> -- 
> 2.47.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Il 05/12/24 13:56, Dmitry Baryshkov ha scritto:
> On Thu, Dec 05, 2024 at 12:45:17PM +0100, AngeloGioacchino Del Regno wrote:
>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
>> found in MediaTek's MT8195, MT8188 SoC and their variants, and
>> including support for display modes up to 4k60 and for HDMI
>> Audio, as per the HDMI 2.0 spec.
>>
>> HDCP and CEC functionalities are also supported by this hardware,
>> but are not included in this commit and that also poses a slight
>> difference between the V2 and V1 controllers in how they handle
>> Hotplug Detection (HPD).
>>
>> While the v1 controller was using the CEC controller to check
>> HDMI cable connection and disconnection, in this driver the v2
>> one does not.
>>
>> This is due to the fact that on parts with v2 designs, like the
>> MT8195 SoC, there is one CEC controller shared between the HDMI
>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
>> adding support to use the CEC HW to wake up the HDMI controllers
>> it is necessary to have support for one TX, one RX *and* for both
>> at the same time.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   drivers/gpu/drm/mediatek/Kconfig            |    8 +
>>   drivers/gpu/drm/mediatek/Makefile           |    4 +
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
>>   drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
>>   drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
>>   drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
>>   drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
>>   7 files changed, 2172 insertions(+)
>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
>>   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>>

..snip..

>> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>> new file mode 100644
>> index 000000000000..05cbfc45be54
>> --- /dev/null
>> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>> @@ -0,0 +1,1488 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*

..snip..

>> +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
>> +{
>> +	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
>> +	struct hdmi_audio_infoframe frame;
>> +	u8 buffer[14];
>> +	ssize_t ret;
>> +
>> +	memcpy(&frame, &params->cea, sizeof(frame));
>> +
>> +	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> 
> This should be handled via HDMI Connector framework too. There is
> already an interface to set / clear audio infoframes.
> als I have been working on an interface to make HDMI codec
> implementation more generic, see [1]. Your comments are appreciated.
> 
> [1] https://patchwork.freedesktop.org/series/134927/
> 

I didn't go for that because I was afraid that your series wouldn't actually
land in the same window as this driver.

I am at this point puzzled to whether I should add a commit on top of this
submission that switches this driver to using the generic HDMI Codec infra
(which could also be helpful as guidance to others trying to do the same on
other drivers, I guess), or if I should just rebase on top of that.

I'd rather add a commit on top to mainly avoid risking to delay this driver,
but if you're absolutely certain that you can get your series merged in the
same window as this driver I have *zero* problems in just rebasing on top.

Besides...

I'll find the time to review your series - I'm sad it didn't land earlier as
I would've written a bit less code otherwise :-)

>> +
>> +	return 0;
>> +}
>> +

..snip..

>> +
>> +	/* Enable the controller at attach time for HPD/Pord feedback */
>> +	ret = mtk_hdmi_v2_enable(hdmi);
>> +	if (ret)
>> +		return ret;
> 
> This looks like a hack. Please use .hpd_enable() / .hpd_disable()
> callbacks.
> 

...but there's no way to power on only the HPD - you can either power on
the entire controller, or nothing.

I can't call mtk_hdmi_v2_enable/disable() from the HPD callbacks.

Perhaps the comment should have been

"Enable the controller attach time also allows HPD/Pord feedback"?

>> +
>> +	/* Enable Hotplug and Pord pins internal debouncing */
>> +	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
>> +			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
>> +
>> +	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
>> +	enable_irq(hdmi->irq);
>> +
>> +	/*
>> +	 * Check if any HDMI monitor was connected before probing this driver
>> +	 * and/or attaching the bridge, without debouncing: if so, we want to
>> +	 * notify the DRM so that we start outputting an image ASAP.
>> +	 * Note that calling the ISR thread function will also perform a HW
>> +	 * registers write that enables both the HPD and Pord interrupts.
>> +	 */
>> +	__mtk_hdmi_v2_isr_thread(hdmi);
>> +
>> +	return 0;
>> +}
>> +

..snip..

>> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
>> +					  struct drm_bridge_state *old_state)
>> +{
>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +	struct drm_atomic_state *state = old_state->base.state;
>> +	struct drm_connector_state *conn_state;
>> +	union phy_configure_opts opts = {
>> +		.dp = { .link_rate = hdmi->mode.clock * KILO }
>> +	};
>> +
>> +	/* Retrieve the connector through the atomic state */
>> +	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
>> +
>> +	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
>> +	if (WARN_ON(!conn_state))
>> +		return;
>> +
>> +	/*
>> +	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
>> +	 * stage to make sure that this IP is ready and clocked before the
>> +	 * mtk_dpi gets powered on and before it enables the output.
>> +	 */
>> +	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
> 
> Can you access display_info directly instead?
> 

Nice catch. Yeah, I should've done that from the beginning. Fixed for v3.

>> +	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
>> +
>> +	/* Reconfigure phy clock link with appropriate rate */
>> +	phy_configure(hdmi->phy, &opts);
>> +
>> +	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
>> +	phy_power_on(hdmi->phy);
>> +
>> +	hdmi->powered = true;
>> +}
>> +
>> +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
>> +				      struct drm_bridge_state *old_state)
>> +{
>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +	struct drm_atomic_state *state = old_state->base.state;
>> +	int ret;
>> +
>> +	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
>> +	if (ret)
>> +		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
>> +
>> +	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
>> +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
>> +
>> +	/* signal the connect event to audio codec */
>> +	mtk_hdmi_v2_handle_plugged_change(hdmi, true);
> 
> I think it was agreed that this should be called from the hotplug path,
> see the (linked) HDMI codec infrastructure patchset and dicussions for
> the previous revisions.
> 

Okay, I'll check that out.

>> +
>> +	hdmi->enabled = true;
>> +}
>> +

..snip..

>> +
>> +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
>> +						 const struct drm_display_mode *mode,
>> +						 unsigned long long tmds_rate)
>> +{
>> +	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
>> +		return MODE_CLOCK_LOW;
>> +	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
>> +		return MODE_CLOCK_HIGH;
>> +	else
>> +		return MODE_OK;
>> +}
>> +
>> +static enum drm_mode_status
>> +mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
>> +			      const struct drm_display_info *info,
>> +			      const struct drm_display_mode *mode)
>> +{
>> +	unsigned long long rate;
>> +
>> +	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
>> +	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
>> +}
> 
> Please rebase on top of https://patchwork.freedesktop.org/series/140193/
> There should be no need to do this manually.
> 

Oh finally there's a helper for this. Cool, will rebase! Thanks!

>> +
>> +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
>> +					    enum hdmi_infoframe_type type)
>> +{
>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +	u32 reg_start, reg_end;
>> +
>> +	switch (type) {
>> +	case HDMI_INFOFRAME_TYPE_AUDIO:
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
>> +		reg_start = TOP_AIF_HEADER;
>> +		reg_end = TOP_AIF_PKT03;
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_AVI:
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
>> +		reg_start = TOP_AVI_HEADER;
>> +		reg_end = TOP_AVI_PKT05;
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_SPD:
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
>> +		reg_start = TOP_SPDIF_HEADER;
>> +		reg_end = TOP_SPDIF_PKT07;
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_VENDOR:
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
>> +		reg_start = TOP_VSIF_HEADER;
>> +		reg_end = TOP_VSIF_PKT07;
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_DRM:
>> +	default:
>> +		return 0;
>> +	};
>> +
>> +	for (; reg_start <= reg_end; reg_start += 4)
>> +		regmap_write(hdmi->regs, reg_start, 0);
> 
> Interesting. Usually sending of the infoframe is controlled by a
> register of a kind.
> 

"This callback clears the infoframes in the hardware during commit"

...and that's exactly what this function does: clears the infoframes
in the HW and stops the RPT, making the HW ready for the "next round".

Did I get the documentation wrong?
Should this function *send* an all-zero infoframe to the external display?

>> +
>> +	return 0;
>> +}
>> +
>> +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
>> +					    enum hdmi_infoframe_type type,
>> +					    const u8 *buffer, size_t len)
>> +{
>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +
>> +	switch (type) {
>> +	case HDMI_INFOFRAME_TYPE_AUDIO:
>> +		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_AVI:
>> +		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_SPD:
>> +		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_VENDOR:
>> +		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
>> +		break;
>> +	case HDMI_INFOFRAME_TYPE_DRM:
>> +	default:
>> +		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
>> +		break;
>> +	};
>> +
>> +	return 0;
>> +}
>> +
>> +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
>> +					   struct drm_bridge_state *bridge_state,
>> +					   struct drm_crtc_state *crtc_state,
>> +					   struct drm_connector_state *conn_state)
>> +{
>> +	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
>> +						      conn_state->state);
>> +}
> 
> Note to myself, probably we can move this to drm_bridge_connector too.
> 
>> +
>> +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
>> +{
>> +	struct drm_display_mode *mode = &hdmi->mode;
>> +	int abist_format = -EINVAL;
>> +	bool interlaced;
>> +
>> +	if (!enable) {
>> +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
>> +		return 0;
>> +	}
>> +
>> +	if (!mode->hdisplay || !mode->vdisplay)
>> +		return -EINVAL;
>> +
>> +	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
> 
> The interlaced modes should be filtered, unless you also set
> bridge->interlace_allowed to true.
> 

Noted. Many Thanks for the review!

I'll wait until next week for more feedback before sending a v3.

Cheers,
Angelo

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[Dmitry Baryshkov]

On Thu, Dec 05, 2024 at 02:30:51PM +0100, AngeloGioacchino Del Regno wrote:
> Il 05/12/24 13:56, Dmitry Baryshkov ha scritto:
> > On Thu, Dec 05, 2024 at 12:45:17PM +0100, AngeloGioacchino Del Regno wrote:
> > > Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> > > found in MediaTek's MT8195, MT8188 SoC and their variants, and
> > > including support for display modes up to 4k60 and for HDMI
> > > Audio, as per the HDMI 2.0 spec.
> > > 
> > > HDCP and CEC functionalities are also supported by this hardware,
> > > but are not included in this commit and that also poses a slight
> > > difference between the V2 and V1 controllers in how they handle
> > > Hotplug Detection (HPD).
> > > 
> > > While the v1 controller was using the CEC controller to check
> > > HDMI cable connection and disconnection, in this driver the v2
> > > one does not.
> > > 
> > > This is due to the fact that on parts with v2 designs, like the
> > > MT8195 SoC, there is one CEC controller shared between the HDMI
> > > Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> > > adding support to use the CEC HW to wake up the HDMI controllers
> > > it is necessary to have support for one TX, one RX *and* for both
> > > at the same time.
> > > 
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > ---
> > >   drivers/gpu/drm/mediatek/Kconfig            |    8 +
> > >   drivers/gpu/drm/mediatek/Makefile           |    4 +
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
> > >   drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
> > >   7 files changed, 2172 insertions(+)
> > >   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
> > >   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
> > >   create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > 
> 
> ..snip..
> 
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > new file mode 100644
> > > index 000000000000..05cbfc45be54
> > > --- /dev/null
> > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > @@ -0,0 +1,1488 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> 
> ..snip..
> 
> > > +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
> > > +{
> > > +	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
> > > +	struct hdmi_audio_infoframe frame;
> > > +	u8 buffer[14];
> > > +	ssize_t ret;
> > > +
> > > +	memcpy(&frame, &params->cea, sizeof(frame));
> > > +
> > > +	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
> > > +	if (ret < 0)
> > > +		return ret;
> > > +
> > > +	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> > 
> > This should be handled via HDMI Connector framework too. There is
> > already an interface to set / clear audio infoframes.
> > als I have been working on an interface to make HDMI codec
> > implementation more generic, see [1]. Your comments are appreciated.
> > 
> > [1] https://patchwork.freedesktop.org/series/134927/
> > 
> 
> I didn't go for that because I was afraid that your series wouldn't actually
> land in the same window as this driver.

There were two points in my comment (sorry for being not explicit
enough). One is to point to the HDMI codec infra (and you are right,
it's not yet in the mergeable state). Second one is to use
drm_atomic_helper_connector_hdmi_update_audio_infoframe() and
drm_atomic_helper_connector_hdmi_clear_audio_infoframe() if possible (it
might be hard to do it - in fact it being hard kind of forced me to
work on the HDMI codec infra).

> I am at this point puzzled to whether I should add a commit on top of this
> submission that switches this driver to using the generic HDMI Codec infra
> (which could also be helpful as guidance to others trying to do the same on
> other drivers, I guess), or if I should just rebase on top of that.

I'd say, a completely separate patch might be even better, I can then
integrate it into the HDMI codec patchset, adding a soft dependency on
your series. If for some reason the codec lands earlier than your
patchset, the patch can be dropped and reintegrated into your series. Or
just committed separately.

> I'd rather add a commit on top to mainly avoid risking to delay this driver,
> but if you're absolutely certain that you can get your series merged in the
> same window as this driver I have *zero* problems in just rebasing on top.
> 
> Besides...
> 
> I'll find the time to review your series - I'm sad it didn't land earlier as
> I would've written a bit less code otherwise :-)
> 
> > > +
> > > +	return 0;
> > > +}
> > > +
> 
> ..snip..
> 
> > > +
> > > +	/* Enable the controller at attach time for HPD/Pord feedback */
> > > +	ret = mtk_hdmi_v2_enable(hdmi);
> > > +	if (ret)
> > > +		return ret;
> > 
> > This looks like a hack. Please use .hpd_enable() / .hpd_disable()
> > callbacks.
> > 
> 
> ...but there's no way to power on only the HPD - you can either power on
> the entire controller, or nothing.
> 
> I can't call mtk_hdmi_v2_enable/disable() from the HPD callbacks.

Why? Add a powerup refcount if necessary.

> 
> Perhaps the comment should have been
> 
> "Enable the controller attach time also allows HPD/Pord feedback"?

I think it should still be explicit call from those callbacks. Consider
a platform using external GPIO to implement HPD. Then the HDMI
controller can stay disabled if it is not necessary.

> 
> > > +
> > > +	/* Enable Hotplug and Pord pins internal debouncing */
> > > +	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
> > > +			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
> > > +
> > > +	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
> > > +	enable_irq(hdmi->irq);
> > > +
> > > +	/*
> > > +	 * Check if any HDMI monitor was connected before probing this driver
> > > +	 * and/or attaching the bridge, without debouncing: if so, we want to
> > > +	 * notify the DRM so that we start outputting an image ASAP.
> > > +	 * Note that calling the ISR thread function will also perform a HW
> > > +	 * registers write that enables both the HPD and Pord interrupts.
> > > +	 */
> > > +	__mtk_hdmi_v2_isr_thread(hdmi);
> > > +
> > > +	return 0;
> > > +}
> > > +
> 
> ..snip..
> 
> > > +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
> > > +					  struct drm_bridge_state *old_state)
> > > +{
> > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > +	struct drm_atomic_state *state = old_state->base.state;
> > > +	struct drm_connector_state *conn_state;
> > > +	union phy_configure_opts opts = {
> > > +		.dp = { .link_rate = hdmi->mode.clock * KILO }
> > > +	};
> > > +
> > > +	/* Retrieve the connector through the atomic state */
> > > +	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
> > > +
> > > +	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
> > > +	if (WARN_ON(!conn_state))
> > > +		return;
> > > +
> > > +	/*
> > > +	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
> > > +	 * stage to make sure that this IP is ready and clocked before the
> > > +	 * mtk_dpi gets powered on and before it enables the output.
> > > +	 */
> > > +	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
> > 
> > Can you access display_info directly instead?
> > 
> 
> Nice catch. Yeah, I should've done that from the beginning. Fixed for v3.
> 
> > > +	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
> > > +
> > > +	/* Reconfigure phy clock link with appropriate rate */
> > > +	phy_configure(hdmi->phy, &opts);
> > > +
> > > +	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
> > > +	phy_power_on(hdmi->phy);
> > > +
> > > +	hdmi->powered = true;
> > > +}
> > > +
> > > +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
> > > +				      struct drm_bridge_state *old_state)
> > > +{
> > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > +	struct drm_atomic_state *state = old_state->base.state;
> > > +	int ret;
> > > +
> > > +	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
> > > +	if (ret)
> > > +		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
> > > +
> > > +	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
> > > +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
> > > +
> > > +	/* signal the connect event to audio codec */
> > > +	mtk_hdmi_v2_handle_plugged_change(hdmi, true);
> > 
> > I think it was agreed that this should be called from the hotplug path,
> > see the (linked) HDMI codec infrastructure patchset and dicussions for
> > the previous revisions.
> > 
> 
> Okay, I'll check that out.
> 
> > > +
> > > +	hdmi->enabled = true;
> > > +}
> > > +
> 
> ..snip..
> 
> > > +
> > > +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
> > > +						 const struct drm_display_mode *mode,
> > > +						 unsigned long long tmds_rate)
> > > +{
> > > +	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
> > > +		return MODE_CLOCK_LOW;
> > > +	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
> > > +		return MODE_CLOCK_HIGH;
> > > +	else
> > > +		return MODE_OK;
> > > +}
> > > +
> > > +static enum drm_mode_status
> > > +mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
> > > +			      const struct drm_display_info *info,
> > > +			      const struct drm_display_mode *mode)
> > > +{
> > > +	unsigned long long rate;
> > > +
> > > +	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> > > +	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
> > > +}
> > 
> > Please rebase on top of https://patchwork.freedesktop.org/series/140193/
> > There should be no need to do this manually.
> > 
> 
> Oh finally there's a helper for this. Cool, will rebase! Thanks!

And it doesn't even add an extra dependency for you.

> 
> > > +
> > > +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
> > > +					    enum hdmi_infoframe_type type)
> > > +{
> > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > +	u32 reg_start, reg_end;
> > > +
> > > +	switch (type) {
> > > +	case HDMI_INFOFRAME_TYPE_AUDIO:
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
> > > +		reg_start = TOP_AIF_HEADER;
> > > +		reg_end = TOP_AIF_PKT03;
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_AVI:
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
> > > +		reg_start = TOP_AVI_HEADER;
> > > +		reg_end = TOP_AVI_PKT05;
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_SPD:
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
> > > +		reg_start = TOP_SPDIF_HEADER;
> > > +		reg_end = TOP_SPDIF_PKT07;
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_VENDOR:
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
> > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
> > > +		reg_start = TOP_VSIF_HEADER;
> > > +		reg_end = TOP_VSIF_PKT07;
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_DRM:
> > > +	default:
> > > +		return 0;
> > > +	};
> > > +
> > > +	for (; reg_start <= reg_end; reg_start += 4)
> > > +		regmap_write(hdmi->regs, reg_start, 0);
> > 
> > Interesting. Usually sending of the infoframe is controlled by a
> > register of a kind.
> > 
> 
> "This callback clears the infoframes in the hardware during commit"
> 
> ...and that's exactly what this function does: clears the infoframes
> in the HW and stops the RPT, making the HW ready for the "next round".
> 
> Did I get the documentation wrong?
> Should this function *send* an all-zero infoframe to the external display?

No, it should stop sending the callback. My point was that usually there
is a separate register which controls the infoframes. You code just
clears the header (which probably is handled as disabling in the IP
core).

> 
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
> > > +					    enum hdmi_infoframe_type type,
> > > +					    const u8 *buffer, size_t len)
> > > +{
> > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > +
> > > +	switch (type) {
> > > +	case HDMI_INFOFRAME_TYPE_AUDIO:
> > > +		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_AVI:
> > > +		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_SPD:
> > > +		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_VENDOR:
> > > +		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
> > > +		break;
> > > +	case HDMI_INFOFRAME_TYPE_DRM:
> > > +	default:
> > > +		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
> > > +		break;
> > > +	};
> > > +
> > > +	return 0;
> > > +}
> > > +
> > > +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> > > +					   struct drm_bridge_state *bridge_state,
> > > +					   struct drm_crtc_state *crtc_state,
> > > +					   struct drm_connector_state *conn_state)
> > > +{
> > > +	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> > > +						      conn_state->state);
> > > +}
> > 
> > Note to myself, probably we can move this to drm_bridge_connector too.
> > 
> > > +
> > > +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
> > > +{
> > > +	struct drm_display_mode *mode = &hdmi->mode;
> > > +	int abist_format = -EINVAL;
> > > +	bool interlaced;
> > > +
> > > +	if (!enable) {
> > > +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
> > > +		return 0;
> > > +	}
> > > +
> > > +	if (!mode->hdisplay || !mode->vdisplay)
> > > +		return -EINVAL;
> > > +
> > > +	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
> > 
> > The interlaced modes should be filtered, unless you also set
> > bridge->interlace_allowed to true.
> > 
> 
> Noted. Many Thanks for the review!
> 
> I'll wait until next week for more feedback before sending a v3.

-- 
With best wishes
Dmitry

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Il 05/12/24 20:35, Dmitry Baryshkov ha scritto:
> On Thu, Dec 05, 2024 at 02:30:51PM +0100, AngeloGioacchino Del Regno wrote:
>> Il 05/12/24 13:56, Dmitry Baryshkov ha scritto:
>>> On Thu, Dec 05, 2024 at 12:45:17PM +0100, AngeloGioacchino Del Regno wrote:
>>>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
>>>> found in MediaTek's MT8195, MT8188 SoC and their variants, and
>>>> including support for display modes up to 4k60 and for HDMI
>>>> Audio, as per the HDMI 2.0 spec.
>>>>
>>>> HDCP and CEC functionalities are also supported by this hardware,
>>>> but are not included in this commit and that also poses a slight
>>>> difference between the V2 and V1 controllers in how they handle
>>>> Hotplug Detection (HPD).
>>>>
>>>> While the v1 controller was using the CEC controller to check
>>>> HDMI cable connection and disconnection, in this driver the v2
>>>> one does not.
>>>>
>>>> This is due to the fact that on parts with v2 designs, like the
>>>> MT8195 SoC, there is one CEC controller shared between the HDMI
>>>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
>>>> adding support to use the CEC HW to wake up the HDMI controllers
>>>> it is necessary to have support for one TX, one RX *and* for both
>>>> at the same time.
>>>>
>>>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>>>> ---
>>>>    drivers/gpu/drm/mediatek/Kconfig            |    8 +
>>>>    drivers/gpu/drm/mediatek/Makefile           |    4 +
>>>>    drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
>>>>    drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
>>>>    drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
>>>>    drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
>>>>    drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
>>>>    7 files changed, 2172 insertions(+)
>>>>    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
>>>>    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
>>>>    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>>>>
>>
>> ..snip..
>>
>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>>>> new file mode 100644
>>>> index 000000000000..05cbfc45be54
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
>>>> @@ -0,0 +1,1488 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> +/*
>>
>> ..snip..
>>
>>>> +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
>>>> +{
>>>> +	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
>>>> +	struct hdmi_audio_infoframe frame;
>>>> +	u8 buffer[14];
>>>> +	ssize_t ret;
>>>> +
>>>> +	memcpy(&frame, &params->cea, sizeof(frame));
>>>> +
>>>> +	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
>>>> +	if (ret < 0)
>>>> +		return ret;
>>>> +
>>>> +	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
>>>
>>> This should be handled via HDMI Connector framework too. There is
>>> already an interface to set / clear audio infoframes.
>>> als I have been working on an interface to make HDMI codec
>>> implementation more generic, see [1]. Your comments are appreciated.
>>>
>>> [1] https://patchwork.freedesktop.org/series/134927/
>>>
>>
>> I didn't go for that because I was afraid that your series wouldn't actually
>> land in the same window as this driver.
> 
> There were two points in my comment (sorry for being not explicit
> enough). One is to point to the HDMI codec infra (and you are right,
> it's not yet in the mergeable state). Second one is to use
> drm_atomic_helper_connector_hdmi_update_audio_infoframe() and
> drm_atomic_helper_connector_hdmi_clear_audio_infoframe() if possible (it
> might be hard to do it - in fact it being hard kind of forced me to
> work on the HDMI codec infra).
> 

That *is* indeed hard and adding almost unnecessary complications to my submission.

>> I am at this point puzzled to whether I should add a commit on top of this
>> submission that switches this driver to using the generic HDMI Codec infra
>> (which could also be helpful as guidance to others trying to do the same on
>> other drivers, I guess), or if I should just rebase on top of that.
> 
> I'd say, a completely separate patch might be even better, I can then
> integrate it into the HDMI codec patchset, adding a soft dependency on
> your series. If for some reason the codec lands earlier than your
> patchset, the patch can be dropped and reintegrated into your series. Or
> just committed separately.

I'd rather get the audio part merged as-is with the old handling at this point...

As you can see, once your HDMI Codec infra gets in a mergeable state the cleanup
(or conversion, however you prefer to call it) in this driver will be mostly
trivial.

This means that whenever your series is ready to merge, I'll be able to send a
(single, most probably) commit updating this driver to use the new helpers in a
jiffy (or two).

> 
>> I'd rather add a commit on top to mainly avoid risking to delay this driver,
>> but if you're absolutely certain that you can get your series merged in the
>> same window as this driver I have *zero* problems in just rebasing on top.
>>
>> Besides...
>>
>> I'll find the time to review your series - I'm sad it didn't land earlier as
>> I would've written a bit less code otherwise :-)
>>
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>
>> ..snip..
>>
>>>> +
>>>> +	/* Enable the controller at attach time for HPD/Pord feedback */
>>>> +	ret = mtk_hdmi_v2_enable(hdmi);
>>>> +	if (ret)
>>>> +		return ret;
>>>
>>> This looks like a hack. Please use .hpd_enable() / .hpd_disable()
>>> callbacks.
>>>
>>
>> ...but there's no way to power on only the HPD - you can either power on
>> the entire controller, or nothing.
>>
>> I can't call mtk_hdmi_v2_enable/disable() from the HPD callbacks.
> 
> Why? Add a powerup refcount if necessary.
> 

...but this means that I still have to keep the mtk_hdmi_v2_enable() call
here, but I didn't understand the point of this until you made me think
about...

>>
>> Perhaps the comment should have been
>>
>> "Enable the controller attach time also allows HPD/Pord feedback"?
> 
> I think it should still be explicit call from those callbacks. Consider
> a platform using external GPIO to implement HPD. Then the HDMI
> controller can stay disabled if it is not necessary.

...this case.

I'm still not sure whether I can actually do what you propose because this
IP needs another IP (mtk_dpi) to be in a configured state before this one
gets enabled, or you get a freeze.

I'll check - if that's feasible, I'll add the refcounting and will go for
the hpd_{en,dis}able callbacks.

> 
>>
>>>> +
>>>> +	/* Enable Hotplug and Pord pins internal debouncing */
>>>> +	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
>>>> +			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
>>>> +
>>>> +	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
>>>> +	enable_irq(hdmi->irq);
>>>> +
>>>> +	/*
>>>> +	 * Check if any HDMI monitor was connected before probing this driver
>>>> +	 * and/or attaching the bridge, without debouncing: if so, we want to
>>>> +	 * notify the DRM so that we start outputting an image ASAP.
>>>> +	 * Note that calling the ISR thread function will also perform a HW
>>>> +	 * registers write that enables both the HPD and Pord interrupts.
>>>> +	 */
>>>> +	__mtk_hdmi_v2_isr_thread(hdmi);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>
>> ..snip..
>>
>>>> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
>>>> +					  struct drm_bridge_state *old_state)
>>>> +{
>>>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>>>> +	struct drm_atomic_state *state = old_state->base.state;
>>>> +	struct drm_connector_state *conn_state;
>>>> +	union phy_configure_opts opts = {
>>>> +		.dp = { .link_rate = hdmi->mode.clock * KILO }
>>>> +	};
>>>> +
>>>> +	/* Retrieve the connector through the atomic state */
>>>> +	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
>>>> +
>>>> +	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
>>>> +	if (WARN_ON(!conn_state))
>>>> +		return;
>>>> +
>>>> +	/*
>>>> +	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
>>>> +	 * stage to make sure that this IP is ready and clocked before the
>>>> +	 * mtk_dpi gets powered on and before it enables the output.
>>>> +	 */
>>>> +	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
>>>
>>> Can you access display_info directly instead?
>>>
>>
>> Nice catch. Yeah, I should've done that from the beginning. Fixed for v3.
>>
>>>> +	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
>>>> +
>>>> +	/* Reconfigure phy clock link with appropriate rate */
>>>> +	phy_configure(hdmi->phy, &opts);
>>>> +
>>>> +	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
>>>> +	phy_power_on(hdmi->phy);
>>>> +
>>>> +	hdmi->powered = true;
>>>> +}
>>>> +
>>>> +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
>>>> +				      struct drm_bridge_state *old_state)
>>>> +{
>>>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>>>> +	struct drm_atomic_state *state = old_state->base.state;
>>>> +	int ret;
>>>> +
>>>> +	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
>>>> +	if (ret)
>>>> +		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
>>>> +
>>>> +	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
>>>> +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
>>>> +
>>>> +	/* signal the connect event to audio codec */
>>>> +	mtk_hdmi_v2_handle_plugged_change(hdmi, true);
>>>
>>> I think it was agreed that this should be called from the hotplug path,
>>> see the (linked) HDMI codec infrastructure patchset and dicussions for
>>> the previous revisions.
>>>
>>
>> Okay, I'll check that out.
>>
>>>> +
>>>> +	hdmi->enabled = true;
>>>> +}
>>>> +
>>
>> ..snip..
>>
>>>> +
>>>> +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
>>>> +						 const struct drm_display_mode *mode,
>>>> +						 unsigned long long tmds_rate)
>>>> +{
>>>> +	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
>>>> +		return MODE_CLOCK_LOW;
>>>> +	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
>>>> +		return MODE_CLOCK_HIGH;
>>>> +	else
>>>> +		return MODE_OK;
>>>> +}
>>>> +
>>>> +static enum drm_mode_status
>>>> +mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
>>>> +			      const struct drm_display_info *info,
>>>> +			      const struct drm_display_mode *mode)
>>>> +{
>>>> +	unsigned long long rate;
>>>> +
>>>> +	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
>>>> +	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
>>>> +}
>>>
>>> Please rebase on top of https://patchwork.freedesktop.org/series/140193/
>>> There should be no need to do this manually.
>>>
>>
>> Oh finally there's a helper for this. Cool, will rebase! Thanks!
> 
> And it doesn't even add an extra dependency for you.
> 

... Which is even cool-er, yes :-)

>>
>>>> +
>>>> +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
>>>> +					    enum hdmi_infoframe_type type)
>>>> +{
>>>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>>>> +	u32 reg_start, reg_end;
>>>> +
>>>> +	switch (type) {
>>>> +	case HDMI_INFOFRAME_TYPE_AUDIO:
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
>>>> +		reg_start = TOP_AIF_HEADER;
>>>> +		reg_end = TOP_AIF_PKT03;
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_AVI:
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
>>>> +		reg_start = TOP_AVI_HEADER;
>>>> +		reg_end = TOP_AVI_PKT05;
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_SPD:
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
>>>> +		reg_start = TOP_SPDIF_HEADER;
>>>> +		reg_end = TOP_SPDIF_PKT07;
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_VENDOR:
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
>>>> +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
>>>> +		reg_start = TOP_VSIF_HEADER;
>>>> +		reg_end = TOP_VSIF_PKT07;
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_DRM:
>>>> +	default:
>>>> +		return 0;
>>>> +	};
>>>> +
>>>> +	for (; reg_start <= reg_end; reg_start += 4)
>>>> +		regmap_write(hdmi->regs, reg_start, 0);
>>>
>>> Interesting. Usually sending of the infoframe is controlled by a
>>> register of a kind.
>>>
>>
>> "This callback clears the infoframes in the hardware during commit"
>>
>> ...and that's exactly what this function does: clears the infoframes
>> in the HW and stops the RPT, making the HW ready for the "next round".
>>
>> Did I get the documentation wrong?
>> Should this function *send* an all-zero infoframe to the external display?
> 
> No, it should stop sending the callback. My point was that usually there
> is a separate register which controls the infoframes. You code just
> clears the header (which probably is handled as disabling in the IP
> core).
> 

No, my code is clearing everything, not just the header.

The registers in this IP are sequential, I'm setting the code to start writing
at HEADER, and stop writing at PKTxx, where PKTxx registers contain the infoframe.

In any case, disabling in the IP core is managed by clearing the _EN and _EN_WR
(where WR means "Write", and RPT_EN is "repeat write") bits in the xxx_INFO_EN
register(s), and that's what I'm doing at the beginning, before actually cleaning
the infoframe registers.

Actually, I could've just cleared the EN bits and that would've been enough, but
I wanted to leave the IP in a clean+known state and decided to zero out the entire
infoframe header/data register set.

....but anyway, what you just said before me explaining how this IP works means
that I got it right, and that this function does exactly what it is supposed to do.


Cheers!
Angelo

>>
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
>>>> +					    enum hdmi_infoframe_type type,
>>>> +					    const u8 *buffer, size_t len)
>>>> +{
>>>> +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>>>> +
>>>> +	switch (type) {
>>>> +	case HDMI_INFOFRAME_TYPE_AUDIO:
>>>> +		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_AVI:
>>>> +		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_SPD:
>>>> +		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_VENDOR:
>>>> +		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
>>>> +		break;
>>>> +	case HDMI_INFOFRAME_TYPE_DRM:
>>>> +	default:
>>>> +		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
>>>> +		break;
>>>> +	};
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
>>>> +					   struct drm_bridge_state *bridge_state,
>>>> +					   struct drm_crtc_state *crtc_state,
>>>> +					   struct drm_connector_state *conn_state)
>>>> +{
>>>> +	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
>>>> +						      conn_state->state);
>>>> +}
>>>
>>> Note to myself, probably we can move this to drm_bridge_connector too.
>>>
>>>> +
>>>> +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
>>>> +{
>>>> +	struct drm_display_mode *mode = &hdmi->mode;
>>>> +	int abist_format = -EINVAL;
>>>> +	bool interlaced;
>>>> +
>>>> +	if (!enable) {
>>>> +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
>>>> +		return 0;
>>>> +	}
>>>> +
>>>> +	if (!mode->hdisplay || !mode->vdisplay)
>>>> +		return -EINVAL;
>>>> +
>>>> +	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
>>>
>>> The interlaced modes should be filtered, unless you also set
>>> bridge->interlace_allowed to true.
>>>
>>
>> Noted. Many Thanks for the review!
>>
>> I'll wait until next week for more feedback before sending a v3.
> 


-- 
AngeloGioacchino Del Regno
Senior Software Engineer

Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[Dmitry Baryshkov]

On Mon, Dec 09, 2024 at 12:33:57PM +0100, AngeloGioacchino Del Regno wrote:
> Il 05/12/24 20:35, Dmitry Baryshkov ha scritto:
> > On Thu, Dec 05, 2024 at 02:30:51PM +0100, AngeloGioacchino Del Regno wrote:
> > > Il 05/12/24 13:56, Dmitry Baryshkov ha scritto:
> > > > On Thu, Dec 05, 2024 at 12:45:17PM +0100, AngeloGioacchino Del Regno wrote:
> > > > > Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> > > > > found in MediaTek's MT8195, MT8188 SoC and their variants, and
> > > > > including support for display modes up to 4k60 and for HDMI
> > > > > Audio, as per the HDMI 2.0 spec.
> > > > > 
> > > > > HDCP and CEC functionalities are also supported by this hardware,
> > > > > but are not included in this commit and that also poses a slight
> > > > > difference between the V2 and V1 controllers in how they handle
> > > > > Hotplug Detection (HPD).
> > > > > 
> > > > > While the v1 controller was using the CEC controller to check
> > > > > HDMI cable connection and disconnection, in this driver the v2
> > > > > one does not.
> > > > > 
> > > > > This is due to the fact that on parts with v2 designs, like the
> > > > > MT8195 SoC, there is one CEC controller shared between the HDMI
> > > > > Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> > > > > adding support to use the CEC HW to wake up the HDMI controllers
> > > > > it is necessary to have support for one TX, one RX *and* for both
> > > > > at the same time.
> > > > > 
> > > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > > > ---
> > > > >    drivers/gpu/drm/mediatek/Kconfig            |    8 +
> > > > >    drivers/gpu/drm/mediatek/Makefile           |    4 +
> > > > >    drivers/gpu/drm/mediatek/mtk_hdmi_common.c  |    5 +
> > > > >    drivers/gpu/drm/mediatek/mtk_hdmi_common.h  |    1 +
> > > > >    drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c  |  403 +++++
> > > > >    drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h |  263 ++++
> > > > >    drivers/gpu/drm/mediatek/mtk_hdmi_v2.c      | 1488 +++++++++++++++++++
> > > > >    7 files changed, 2172 insertions(+)
> > > > >    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c
> > > > >    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_regs_v2.h
> > > > >    create mode 100644 drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > > > 
> > > 
> > > ..snip..
> > > 
> > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > > > new file mode 100644
> > > > > index 000000000000..05cbfc45be54
> > > > > --- /dev/null
> > > > > +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c
> > > > > @@ -0,0 +1,1488 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > +/*
> > > 
> > > ..snip..
> > > 
> > > > > +static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
> > > > > +{
> > > > > +	struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
> > > > > +	struct hdmi_audio_infoframe frame;
> > > > > +	u8 buffer[14];
> > > > > +	ssize_t ret;
> > > > > +
> > > > > +	memcpy(&frame, &params->cea, sizeof(frame));
> > > > > +
> > > > > +	ret = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
> > > > > +	if (ret < 0)
> > > > > +		return ret;
> > > > > +
> > > > > +	mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> > > > 
> > > > This should be handled via HDMI Connector framework too. There is
> > > > already an interface to set / clear audio infoframes.
> > > > als I have been working on an interface to make HDMI codec
> > > > implementation more generic, see [1]. Your comments are appreciated.
> > > > 
> > > > [1] https://patchwork.freedesktop.org/series/134927/
> > > > 
> > > 
> > > I didn't go for that because I was afraid that your series wouldn't actually
> > > land in the same window as this driver.
> > 
> > There were two points in my comment (sorry for being not explicit
> > enough). One is to point to the HDMI codec infra (and you are right,
> > it's not yet in the mergeable state). Second one is to use
> > drm_atomic_helper_connector_hdmi_update_audio_infoframe() and
> > drm_atomic_helper_connector_hdmi_clear_audio_infoframe() if possible (it
> > might be hard to do it - in fact it being hard kind of forced me to
> > work on the HDMI codec infra).
> > 
> 
> That *is* indeed hard and adding almost unnecessary complications to my submission.
> 
> > > I am at this point puzzled to whether I should add a commit on top of this
> > > submission that switches this driver to using the generic HDMI Codec infra
> > > (which could also be helpful as guidance to others trying to do the same on
> > > other drivers, I guess), or if I should just rebase on top of that.
> > 
> > I'd say, a completely separate patch might be even better, I can then
> > integrate it into the HDMI codec patchset, adding a soft dependency on
> > your series. If for some reason the codec lands earlier than your
> > patchset, the patch can be dropped and reintegrated into your series. Or
> > just committed separately.
> 
> I'd rather get the audio part merged as-is with the old handling at this point...
> 
> As you can see, once your HDMI Codec infra gets in a mergeable state the cleanup
> (or conversion, however you prefer to call it) in this driver will be mostly
> trivial.
> 
> This means that whenever your series is ready to merge, I'll be able to send a
> (single, most probably) commit updating this driver to use the new helpers in a
> jiffy (or two).

SGTM

> 
> > 
> > > I'd rather add a commit on top to mainly avoid risking to delay this driver,
> > > but if you're absolutely certain that you can get your series merged in the
> > > same window as this driver I have *zero* problems in just rebasing on top.
> > > 
> > > Besides...
> > > 
> > > I'll find the time to review your series - I'm sad it didn't land earlier as
> > > I would've written a bit less code otherwise :-)
> > > 
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +
> > > 
> > > ..snip..
> > > 
> > > > > +
> > > > > +	/* Enable the controller at attach time for HPD/Pord feedback */
> > > > > +	ret = mtk_hdmi_v2_enable(hdmi);
> > > > > +	if (ret)
> > > > > +		return ret;
> > > > 
> > > > This looks like a hack. Please use .hpd_enable() / .hpd_disable()
> > > > callbacks.
> > > > 
> > > 
> > > ...but there's no way to power on only the HPD - you can either power on
> > > the entire controller, or nothing.
> > > 
> > > I can't call mtk_hdmi_v2_enable/disable() from the HPD callbacks.
> > 
> > Why? Add a powerup refcount if necessary.
> > 
> 
> ...but this means that I still have to keep the mtk_hdmi_v2_enable() call
> here, but I didn't understand the point of this until you made me think
> about...
> 
> > > 
> > > Perhaps the comment should have been
> > > 
> > > "Enable the controller attach time also allows HPD/Pord feedback"?
> > 
> > I think it should still be explicit call from those callbacks. Consider
> > a platform using external GPIO to implement HPD. Then the HDMI
> > controller can stay disabled if it is not necessary.
> 
> ...this case.
> 
> I'm still not sure whether I can actually do what you propose because this
> IP needs another IP (mtk_dpi) to be in a configured state before this one
> gets enabled, or you get a freeze.

This sounds like PM runtime and PM devlink from HDMI to DPI, bringing
DPI up when HDMI is PM-runtime-resumed.

> 
> I'll check - if that's feasible, I'll add the refcounting and will go for
> the hpd_{en,dis}able callbacks.
> 
> > 
> > > 
> > > > > +
> > > > > +	/* Enable Hotplug and Pord pins internal debouncing */
> > > > > +	regmap_set_bits(hdmi->regs, HPD_DDC_CTRL,
> > > > > +			HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
> > > > > +
> > > > > +	irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN);
> > > > > +	enable_irq(hdmi->irq);
> > > > > +
> > > > > +	/*
> > > > > +	 * Check if any HDMI monitor was connected before probing this driver
> > > > > +	 * and/or attaching the bridge, without debouncing: if so, we want to
> > > > > +	 * notify the DRM so that we start outputting an image ASAP.
> > > > > +	 * Note that calling the ISR thread function will also perform a HW
> > > > > +	 * registers write that enables both the HPD and Pord interrupts.
> > > > > +	 */
> > > > > +	__mtk_hdmi_v2_isr_thread(hdmi);
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +
> > > 
> > > ..snip..
> > > 
> > > > > +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
> > > > > +					  struct drm_bridge_state *old_state)
> > > > > +{
> > > > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > > > +	struct drm_atomic_state *state = old_state->base.state;
> > > > > +	struct drm_connector_state *conn_state;
> > > > > +	union phy_configure_opts opts = {
> > > > > +		.dp = { .link_rate = hdmi->mode.clock * KILO }
> > > > > +	};
> > > > > +
> > > > > +	/* Retrieve the connector through the atomic state */
> > > > > +	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
> > > > > +
> > > > > +	conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
> > > > > +	if (WARN_ON(!conn_state))
> > > > > +		return;
> > > > > +
> > > > > +	/*
> > > > > +	 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
> > > > > +	 * stage to make sure that this IP is ready and clocked before the
> > > > > +	 * mtk_dpi gets powered on and before it enables the output.
> > > > > +	 */
> > > > > +	hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
> > > > 
> > > > Can you access display_info directly instead?
> > > > 
> > > 
> > > Nice catch. Yeah, I should've done that from the beginning. Fixed for v3.
> > > 
> > > > > +	mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
> > > > > +
> > > > > +	/* Reconfigure phy clock link with appropriate rate */
> > > > > +	phy_configure(hdmi->phy, &opts);
> > > > > +
> > > > > +	/* Power on the PHY here to make sure that DPI_HDMI is clocked */
> > > > > +	phy_power_on(hdmi->phy);
> > > > > +
> > > > > +	hdmi->powered = true;
> > > > > +}
> > > > > +
> > > > > +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
> > > > > +				      struct drm_bridge_state *old_state)
> > > > > +{
> > > > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > > > +	struct drm_atomic_state *state = old_state->base.state;
> > > > > +	int ret;
> > > > > +
> > > > > +	ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
> > > > > +	if (ret)
> > > > > +		dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
> > > > > +
> > > > > +	mtk_hdmi_v2_hw_vid_mute(hdmi, false);
> > > > > +	mtk_hdmi_v2_hw_aud_mute(hdmi, false);
> > > > > +
> > > > > +	/* signal the connect event to audio codec */
> > > > > +	mtk_hdmi_v2_handle_plugged_change(hdmi, true);
> > > > 
> > > > I think it was agreed that this should be called from the hotplug path,
> > > > see the (linked) HDMI codec infrastructure patchset and dicussions for
> > > > the previous revisions.
> > > > 
> > > 
> > > Okay, I'll check that out.
> > > 
> > > > > +
> > > > > +	hdmi->enabled = true;
> > > > > +}
> > > > > +
> > > 
> > > ..snip..
> > > 
> > > > > +
> > > > > +static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
> > > > > +						 const struct drm_display_mode *mode,
> > > > > +						 unsigned long long tmds_rate)
> > > > > +{
> > > > > +	if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
> > > > > +		return MODE_CLOCK_LOW;
> > > > > +	else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
> > > > > +		return MODE_CLOCK_HIGH;
> > > > > +	else
> > > > > +		return MODE_OK;
> > > > > +}
> > > > > +
> > > > > +static enum drm_mode_status
> > > > > +mtk_hdmi_v2_bridge_mode_valid(struct drm_bridge *bridge,
> > > > > +			      const struct drm_display_info *info,
> > > > > +			      const struct drm_display_mode *mode)
> > > > > +{
> > > > > +	unsigned long long rate;
> > > > > +
> > > > > +	rate = drm_hdmi_compute_mode_clock(mode, 8, HDMI_COLORSPACE_RGB);
> > > > > +	return mtk_hdmi_v2_hdmi_tmds_char_rate_valid(bridge, mode, rate);
> > > > > +}
> > > > 
> > > > Please rebase on top of https://patchwork.freedesktop.org/series/140193/
> > > > There should be no need to do this manually.
> > > > 
> > > 
> > > Oh finally there's a helper for this. Cool, will rebase! Thanks!
> > 
> > And it doesn't even add an extra dependency for you.
> > 
> 
> ... Which is even cool-er, yes :-)
> 
> > > 
> > > > > +
> > > > > +static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
> > > > > +					    enum hdmi_infoframe_type type)
> > > > > +{
> > > > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > > > +	u32 reg_start, reg_end;
> > > > > +
> > > > > +	switch (type) {
> > > > > +	case HDMI_INFOFRAME_TYPE_AUDIO:
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
> > > > > +		reg_start = TOP_AIF_HEADER;
> > > > > +		reg_end = TOP_AIF_PKT03;
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_AVI:
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
> > > > > +		reg_start = TOP_AVI_HEADER;
> > > > > +		reg_end = TOP_AVI_PKT05;
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_SPD:
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
> > > > > +		reg_start = TOP_SPDIF_HEADER;
> > > > > +		reg_end = TOP_SPDIF_PKT07;
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_VENDOR:
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
> > > > > +		reg_start = TOP_VSIF_HEADER;
> > > > > +		reg_end = TOP_VSIF_PKT07;
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_DRM:
> > > > > +	default:
> > > > > +		return 0;
> > > > > +	};
> > > > > +
> > > > > +	for (; reg_start <= reg_end; reg_start += 4)
> > > > > +		regmap_write(hdmi->regs, reg_start, 0);
> > > > 
> > > > Interesting. Usually sending of the infoframe is controlled by a
> > > > register of a kind.
> > > > 
> > > 
> > > "This callback clears the infoframes in the hardware during commit"
> > > 
> > > ...and that's exactly what this function does: clears the infoframes
> > > in the HW and stops the RPT, making the HW ready for the "next round".
> > > 
> > > Did I get the documentation wrong?
> > > Should this function *send* an all-zero infoframe to the external display?
> > 
> > No, it should stop sending the callback. My point was that usually there
> > is a separate register which controls the infoframes. You code just
> > clears the header (which probably is handled as disabling in the IP
> > core).
> > 
> 
> No, my code is clearing everything, not just the header.
> 
> The registers in this IP are sequential, I'm setting the code to start writing
> at HEADER, and stop writing at PKTxx, where PKTxx registers contain the infoframe.
> 
> In any case, disabling in the IP core is managed by clearing the _EN and _EN_WR
> (where WR means "Write", and RPT_EN is "repeat write") bits in the xxx_INFO_EN
> register(s), and that's what I'm doing at the beginning, before actually cleaning
> the infoframe registers.
> 
> Actually, I could've just cleared the EN bits and that would've been enough, but
> I wanted to leave the IP in a clean+known state and decided to zero out the entire
> infoframe header/data register set.
> 
> ....but anyway, what you just said before me explaining how this IP works means
> that I got it right, and that this function does exactly what it is supposed to do.

I'd say, clearing just the EN/EN_WR/RPT_EN is enough - this is what
other drivers do.

> 
> 
> Cheers!
> Angelo
> 
> > > 
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +
> > > > > +static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
> > > > > +					    enum hdmi_infoframe_type type,
> > > > > +					    const u8 *buffer, size_t len)
> > > > > +{
> > > > > +	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> > > > > +
> > > > > +	switch (type) {
> > > > > +	case HDMI_INFOFRAME_TYPE_AUDIO:
> > > > > +		mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_AVI:
> > > > > +		mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_SPD:
> > > > > +		mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_VENDOR:
> > > > > +		mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
> > > > > +		break;
> > > > > +	case HDMI_INFOFRAME_TYPE_DRM:
> > > > > +	default:
> > > > > +		dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
> > > > > +		break;
> > > > > +	};
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +
> > > > > +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> > > > > +					   struct drm_bridge_state *bridge_state,
> > > > > +					   struct drm_crtc_state *crtc_state,
> > > > > +					   struct drm_connector_state *conn_state)
> > > > > +{
> > > > > +	return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> > > > > +						      conn_state->state);
> > > > > +}
> > > > 
> > > > Note to myself, probably we can move this to drm_bridge_connector too.
> > > > 
> > > > > +
> > > > > +static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
> > > > > +{
> > > > > +	struct drm_display_mode *mode = &hdmi->mode;
> > > > > +	int abist_format = -EINVAL;
> > > > > +	bool interlaced;
> > > > > +
> > > > > +	if (!enable) {
> > > > > +		regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
> > > > > +		return 0;
> > > > > +	}
> > > > > +
> > > > > +	if (!mode->hdisplay || !mode->vdisplay)
> > > > > +		return -EINVAL;
> > > > > +
> > > > > +	interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
> > > > 
> > > > The interlaced modes should be filtered, unless you also set
> > > > bridge->interlace_allowed to true.
> > > > 
> > > 
> > > Noted. Many Thanks for the review!
> > > 
> > > I'll wait until next week for more feedback before sending a v3.
> > 
> 
> 
> -- 
> AngeloGioacchino Del Regno
> Senior Software Engineer
> 
> Collabora Ltd.
> Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
> Registered in England & Wales, no. 5513718

-- 
With best wishes
Dmitry

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[kernel test robot]

Hi AngeloGioacchino,

kernel test robot noticed the following build errors:

[auto build test ERROR on robh/for-next]
[also build test ERROR on pza/reset/next linus/master drm-misc/drm-misc-next v6.13-rc1 next-20241205]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/dt-bindings-display-mediatek-dpi-Add-MT8195-and-MT8188-compat/20241205-194853
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20241205114518.53527-16-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20241206/202412060636.00bzNpm9-lkp@intel.com/config)
compiler: clang version 20.0.0git (https://github.com/llvm/llvm-project 592c0fe55f6d9a811028b5f3507be91458ab2713)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241206/202412060636.00bzNpm9-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202412060636.00bzNpm9-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c:15:
   In file included from include/linux/i2c.h:13:
   In file included from include/linux/acpi.h:39:
   In file included from include/acpi/acpi_io.h:7:
   In file included from arch/arm64/include/asm/acpi.h:14:
   In file included from include/linux/memblock.h:12:
   In file included from include/linux/mm.h:2223:
   include/linux/vmstat.h:504:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     504 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     505 |                            item];
         |                            ~~~~
   include/linux/vmstat.h:511:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     511 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     512 |                            NR_VM_NUMA_EVENT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~~
   include/linux/vmstat.h:518:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
     518 |         return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
         |                               ~~~~~~~~~~~ ^ ~~~
   include/linux/vmstat.h:524:43: warning: arithmetic between different enumeration types ('enum zone_stat_item' and 'enum numa_stat_item') [-Wenum-enum-conversion]
     524 |         return vmstat_text[NR_VM_ZONE_STAT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~ ^
     525 |                            NR_VM_NUMA_EVENT_ITEMS +
         |                            ~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c:389:47: error: expected ';' after top level declarator
     389 | MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match)
         |                                               ^
         |                                               ;
   4 warnings and 1 error generated.


vim +389 drivers/gpu/drm/mediatek/mtk_hdmi_ddc_v2.c

   384	
   385	static const struct of_device_id mtk_hdmi_ddc_v2_match[] = {
   386		{ .compatible = "mediatek,mt8195-hdmi-ddc" },
   387		{ /* sentinel */ }
   388	};
 > 389	MODULE_DEVICE_TABLE(of, mtk_hdmi_ddc_v2_match)
   390	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
> +                                     struct drm_bridge_state *old_state)
> +{
> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +       struct drm_atomic_state *state = old_state->base.state;
> +       int ret;
> +
> +       ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
> +       if (ret)
> +               dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
> +
> +       mtk_hdmi_v2_hw_vid_mute(hdmi, false);
> +       mtk_hdmi_v2_hw_aud_mute(hdmi, false);

In v1, it does not unmute when bridge enable.
I would like v1 and v2 has the same behavior.
If possible, remove these code.
If remove thee code would result in some problem,
add comment to describe why need these code.

Regards,
CK

> +
> +       /* signal the connect event to audio codec */
> +       mtk_hdmi_v2_handle_plugged_change(hdmi, true);
> +
> +       hdmi->enabled = true;
> +}
> +

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Il 10/12/24 04:28, CK Hu (胡俊光) ha scritto:
> Hi, Angelo:
> 
> On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
>> found in MediaTek's MT8195, MT8188 SoC and their variants, and
>> including support for display modes up to 4k60 and for HDMI
>> Audio, as per the HDMI 2.0 spec.
>>
>> HDCP and CEC functionalities are also supported by this hardware,
>> but are not included in this commit and that also poses a slight
>> difference between the V2 and V1 controllers in how they handle
>> Hotplug Detection (HPD).
>>
>> While the v1 controller was using the CEC controller to check
>> HDMI cable connection and disconnection, in this driver the v2
>> one does not.
>>
>> This is due to the fact that on parts with v2 designs, like the
>> MT8195 SoC, there is one CEC controller shared between the HDMI
>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
>> adding support to use the CEC HW to wake up the HDMI controllers
>> it is necessary to have support for one TX, one RX *and* for both
>> at the same time.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
> 
> [snip]
> 
>> +static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
>> +                                     struct drm_bridge_state *old_state)
>> +{
>> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +       struct drm_atomic_state *state = old_state->base.state;
>> +       int ret;
>> +
>> +       ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state);
>> +       if (ret)
>> +               dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
>> +
>> +       mtk_hdmi_v2_hw_vid_mute(hdmi, false);
>> +       mtk_hdmi_v2_hw_aud_mute(hdmi, false);
> 
> In v1, it does not unmute when bridge enable.
> I would like v1 and v2 has the same behavior.
> If possible, remove these code.
> If remove thee code would result in some problem,
> add comment to describe why need these code.
> 

I think you even said that in the first review...

Thanks for repeating, and sorry for missing that in v2, will be done
for v3

Cheers,
Angelo

> Regards,
> CK
> 
>> +
>> +       /* signal the connect event to audio codec */
>> +       mtk_hdmi_v2_handle_plugged_change(hdmi, true);
>> +
>> +       hdmi->enabled = true;
>> +}
>> +
> 

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type)

parameter hdmi is redundant, so drop it.

Regards,
CK

> +{
> +       switch (channel_type) {
> +       case HDMI_AUD_CHAN_TYPE_1_1:
> +       case HDMI_AUD_CHAN_TYPE_2_1:
> +               return 0x01;
> +       case HDMI_AUD_CHAN_TYPE_3_0:
> +               return 0x02;
> +       case HDMI_AUD_CHAN_TYPE_3_1:
> +               return 0x03;
> +       case HDMI_AUD_CHAN_TYPE_3_0_LRS:
> +       case HDMI_AUD_CHAN_TYPE_4_0:
> +               return 0x08;
> +       case HDMI_AUD_CHAN_TYPE_5_1:
> +               return 0x0b;
> +       case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
> +       case HDMI_AUD_CHAN_TYPE_6_0:
> +       case HDMI_AUD_CHAN_TYPE_6_0_CS:
> +       case HDMI_AUD_CHAN_TYPE_6_0_CH:
> +       case HDMI_AUD_CHAN_TYPE_6_0_OH:
> +       case HDMI_AUD_CHAN_TYPE_6_0_CHR:
> +               return 0x0e;
> +       case HDMI_AUD_CHAN_TYPE_1_0:
> +       case HDMI_AUD_CHAN_TYPE_2_0:
> +       case HDMI_AUD_CHAN_TYPE_3_1_LRS:
> +       case HDMI_AUD_CHAN_TYPE_4_1:
> +       case HDMI_AUD_CHAN_TYPE_5_0:
> +       case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
> +       case HDMI_AUD_CHAN_TYPE_6_1:
> +       case HDMI_AUD_CHAN_TYPE_6_1_CS:
> +       case HDMI_AUD_CHAN_TYPE_6_1_CH:
> +       case HDMI_AUD_CHAN_TYPE_6_1_OH:
> +       case HDMI_AUD_CHAN_TYPE_6_1_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_0:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
> +       case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
> +       case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
> +       case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
> +       case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
> +       case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
> +       case HDMI_AUD_CHAN_TYPE_7_1:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
> +       case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
> +       case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
> +       case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
> +       case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
> +       case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
> +       default:
> +               return 0;
> +       }
> +
> +       return 0;
> +}
> +

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> +                                          struct drm_bridge_state *bridge_state,
> +                                          struct drm_crtc_state *crtc_state,
> +                                          struct drm_connector_state *conn_state)
> +{

I would like v1 and v2 has the same behavior.
Why v2 has atomic check but v1 has no?
If this is better to have, add atomic check to v1, and this function would be common function.

Regards,
CK

> +       return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> +                                                     conn_state->state);
> +}
> +

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Il 16/12/24 09:57, CK Hu (胡俊光) ha scritto:
> Hi, Angelo:
> 
> On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
>> found in MediaTek's MT8195, MT8188 SoC and their variants, and
>> including support for display modes up to 4k60 and for HDMI
>> Audio, as per the HDMI 2.0 spec.
>>
>> HDCP and CEC functionalities are also supported by this hardware,
>> but are not included in this commit and that also poses a slight
>> difference between the V2 and V1 controllers in how they handle
>> Hotplug Detection (HPD).
>>
>> While the v1 controller was using the CEC controller to check
>> HDMI cable connection and disconnection, in this driver the v2
>> one does not.
>>
>> This is due to the fact that on parts with v2 designs, like the
>> MT8195 SoC, there is one CEC controller shared between the HDMI
>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
>> adding support to use the CEC HW to wake up the HDMI controllers
>> it is necessary to have support for one TX, one RX *and* for both
>> at the same time.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
> 
> [snip]
> 
>> +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
>> +                                          struct drm_bridge_state *bridge_state,
>> +                                          struct drm_crtc_state *crtc_state,
>> +                                          struct drm_connector_state *conn_state)
>> +{
> 
> I would like v1 and v2 has the same behavior.
> Why v2 has atomic check but v1 has no?
> If this is better to have, add atomic check to v1, and this function would be common function.
> 

That's because v2 uses the new helpers, while v1 does not.
The v1 must be converted to the new helpers in order to use atomic_check() like v2.

Cheers,
Angelo

> Regards,
> CK
> 
>> +       return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
>> +                                                     conn_state->state);
>> +}
>> +
> 
> 

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

On Mon, 2024-12-16 at 12:04 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Il 16/12/24 09:57, CK Hu (胡俊光) ha scritto:
> > Hi, Angelo:
> > 
> > On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> > > External email : Please do not click links or open attachments until you have verified the sender or the content.
> > > 
> > > 
> > > Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> > > found in MediaTek's MT8195, MT8188 SoC and their variants, and
> > > including support for display modes up to 4k60 and for HDMI
> > > Audio, as per the HDMI 2.0 spec.
> > > 
> > > HDCP and CEC functionalities are also supported by this hardware,
> > > but are not included in this commit and that also poses a slight
> > > difference between the V2 and V1 controllers in how they handle
> > > Hotplug Detection (HPD).
> > > 
> > > While the v1 controller was using the CEC controller to check
> > > HDMI cable connection and disconnection, in this driver the v2
> > > one does not.
> > > 
> > > This is due to the fact that on parts with v2 designs, like the
> > > MT8195 SoC, there is one CEC controller shared between the HDMI
> > > Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> > > adding support to use the CEC HW to wake up the HDMI controllers
> > > it is necessary to have support for one TX, one RX *and* for both
> > > at the same time.
> > > 
> > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > ---
> > 
> > [snip]
> > 
> > > +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> > > +                                          struct drm_bridge_state *bridge_state,
> > > +                                          struct drm_crtc_state *crtc_state,
> > > +                                          struct drm_connector_state *conn_state)
> > > +{
> > 
> > I would like v1 and v2 has the same behavior.
> > Why v2 has atomic check but v1 has no?
> > If this is better to have, add atomic check to v1, and this function would be common function.
> > 
> 
> That's because v2 uses the new helpers, while v1 does not.
> The v1 must be converted to the new helpers in order to use atomic_check() like v2.

I just find the description here, and I don't know why new helper need atomic_check().
Would you provide more information how new helper need atomic_check()?
For example, the call stack to atomic_check(). (You could use dump_stack() to show it)

        /**
        * @atomic_check:
        *
        * This method is responsible for checking bridge state correctness.
        * It can also check the state of the surrounding components in chain
        * to make sure the whole pipeline can work properly.
        *
        * &drm_bridge_funcs.atomic_check() hooks are called in reverse
        * order (from the last to the first bridge).
        *
        * This method is optional. &drm_bridge_funcs.mode_fixup() is not
        * called when &drm_bridge_funcs.atomic_check() is implemented, so only
        * one of them should be provided.
        *
        * If drivers need to tweak &drm_bridge_state.input_bus_cfg.flags or
        * &drm_bridge_state.output_bus_cfg.flags it should happen in
        * this function. By default the &drm_bridge_state.output_bus_cfg.flags
        * field is set to the next bridge
        * &drm_bridge_state.input_bus_cfg.flags value or
        * &drm_connector.display_info.bus_flags if the bridge is the last
        * element in the chain.
        *
        * RETURNS:
        * zero if the check passed, a negative error code otherwise.
        */

Regards,
CK

> 
> Cheers,
> Angelo
> 
> > Regards,
> > CK
> > 
> > > +       return drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> > > +                                                     conn_state->state);
> > > +}
> > > +
> > 
> > 
> 
> 
> 

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[Dmitry Baryshkov]

On Tue, Dec 17, 2024 at 06:40:11AM +0000, CK Hu (胡俊光) wrote:
> On Mon, 2024-12-16 at 12:04 +0100, AngeloGioacchino Del Regno wrote:
> > External email : Please do not click links or open attachments until you have verified the sender or the content.
> > 
> > 
> > Il 16/12/24 09:57, CK Hu (胡俊光) ha scritto:
> > > Hi, Angelo:
> > > 
> > > On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> > > > External email : Please do not click links or open attachments until you have verified the sender or the content.
> > > > 
> > > > 
> > > > Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> > > > found in MediaTek's MT8195, MT8188 SoC and their variants, and
> > > > including support for display modes up to 4k60 and for HDMI
> > > > Audio, as per the HDMI 2.0 spec.
> > > > 
> > > > HDCP and CEC functionalities are also supported by this hardware,
> > > > but are not included in this commit and that also poses a slight
> > > > difference between the V2 and V1 controllers in how they handle
> > > > Hotplug Detection (HPD).
> > > > 
> > > > While the v1 controller was using the CEC controller to check
> > > > HDMI cable connection and disconnection, in this driver the v2
> > > > one does not.
> > > > 
> > > > This is due to the fact that on parts with v2 designs, like the
> > > > MT8195 SoC, there is one CEC controller shared between the HDMI
> > > > Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> > > > adding support to use the CEC HW to wake up the HDMI controllers
> > > > it is necessary to have support for one TX, one RX *and* for both
> > > > at the same time.
> > > > 
> > > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> > > > ---
> > > 
> > > [snip]
> > > 
> > > > +static int mtk_hdmi_v2_bridge_atomic_check(struct drm_bridge *bridge,
> > > > +                                          struct drm_bridge_state *bridge_state,
> > > > +                                          struct drm_crtc_state *crtc_state,
> > > > +                                          struct drm_connector_state *conn_state)
> > > > +{
> > > 
> > > I would like v1 and v2 has the same behavior.
> > > Why v2 has atomic check but v1 has no?
> > > If this is better to have, add atomic check to v1, and this function would be common function.
> > > 
> > 
> > That's because v2 uses the new helpers, while v1 does not.
> > The v1 must be converted to the new helpers in order to use atomic_check() like v2.
> 
> I just find the description here, and I don't know why new helper need atomic_check().
> Would you provide more information how new helper need atomic_check()?

The HDMI helpers requires the driver to use
drm_atomic_helper_connector_hdmi_check() in order to maintain
HDMI-specific connector and CRTC state. Thus drivers using HDMI
Connector framework have to provide .atomic_check() callback which calls
the mentioned function.

> For example, the call stack to atomic_check(). (You could use dump_stack() to show it)

-- 
With best wishes
Dmitry

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
> +       .attach = mtk_hdmi_v2_bridge_attach,
> +       .detach = mtk_hdmi_v2_bridge_detach,
> +       .mode_fixup = mtk_hdmi_bridge_mode_fixup,
> +       .mode_set = mtk_hdmi_bridge_mode_set,
> +       .mode_valid = mtk_hdmi_v2_bridge_mode_valid,
> +       .atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable,
> +       .atomic_enable = mtk_hdmi_v2_bridge_enable,
> +       .atomic_disable = mtk_hdmi_v2_bridge_disable,
> +       .atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
> +       .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> +       .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> +       .atomic_check = mtk_hdmi_v2_bridge_atomic_check,
> +       .atomic_reset = drm_atomic_helper_bridge_reset,
> +       .detect = mtk_hdmi_v2_bridge_detect,
> +       .edid_read = mtk_hdmi_v2_bridge_edid_read,
> +       .hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
> +       .hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
> +       .hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
> +       .debugfs_init = mtk_hdmi_v2_debugfs_init,

I would like this patch to be smaller, so separate debugfs to an independent patch.

Regards,
CK

> +};
> +

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[CK Hu (胡俊光)]

Hi, Angelo:

On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until you have verified the sender or the content.
> 
> 
> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
> found in MediaTek's MT8195, MT8188 SoC and their variants, and
> including support for display modes up to 4k60 and for HDMI
> Audio, as per the HDMI 2.0 spec.
> 
> HDCP and CEC functionalities are also supported by this hardware,
> but are not included in this commit and that also poses a slight
> difference between the V2 and V1 controllers in how they handle
> Hotplug Detection (HPD).
> 
> While the v1 controller was using the CEC controller to check
> HDMI cable connection and disconnection, in this driver the v2
> one does not.
> 
> This is due to the fact that on parts with v2 designs, like the
> MT8195 SoC, there is one CEC controller shared between the HDMI
> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
> adding support to use the CEC HW to wake up the HDMI controllers
> it is necessary to have support for one TX, one RX *and* for both
> at the same time.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

[snip]

> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
> +                                         struct drm_bridge_state *old_state)
> +{
> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
> +       struct drm_atomic_state *state = old_state->base.state;
> +       struct drm_connector_state *conn_state;
> +       union phy_configure_opts opts = {
> +               .dp = { .link_rate = hdmi->mode.clock * KILO }
> +       };
> +
> +       /* Retrieve the connector through the atomic state */
> +       hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
> +
> +       conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
> +       if (WARN_ON(!conn_state))
> +               return;
> +
> +       /*
> +        * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
> +        * stage to make sure that this IP is ready and clocked before the
> +        * mtk_dpi gets powered on and before it enables the output.

In patch [6/15], you does not power on DPI power in DPI driver.
Could you point out the code about 'mtk_dpi gets powered on'?

Regards,
CK

> +        */
> +       hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
> +       mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
> +
> +       /* Reconfigure phy clock link with appropriate rate */
> +       phy_configure(hdmi->phy, &opts);
> +
> +       /* Power on the PHY here to make sure that DPI_HDMI is clocked */
> +       phy_power_on(hdmi->phy);
> +
> +       hdmi->powered = true;
> +}
> +

Re: [PATCH v2 15/15] drm/mediatek: Introduce HDMI/DDC v2 for MT8195/MT8188

[AngeloGioacchino Del Regno]

Il 17/12/24 10:21, CK Hu (胡俊光) ha scritto:
> Hi, Angelo:
> 
> On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until you have verified the sender or the content.
>>
>>
>> Add support for the newer HDMI-TX (Encoder) v2 and DDC v2 IPs
>> found in MediaTek's MT8195, MT8188 SoC and their variants, and
>> including support for display modes up to 4k60 and for HDMI
>> Audio, as per the HDMI 2.0 spec.
>>
>> HDCP and CEC functionalities are also supported by this hardware,
>> but are not included in this commit and that also poses a slight
>> difference between the V2 and V1 controllers in how they handle
>> Hotplug Detection (HPD).
>>
>> While the v1 controller was using the CEC controller to check
>> HDMI cable connection and disconnection, in this driver the v2
>> one does not.
>>
>> This is due to the fact that on parts with v2 designs, like the
>> MT8195 SoC, there is one CEC controller shared between the HDMI
>> Transmitter (HDMI-TX) and Receiver (HDMI-RX): before eventually
>> adding support to use the CEC HW to wake up the HDMI controllers
>> it is necessary to have support for one TX, one RX *and* for both
>> at the same time.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
> 
> [snip]
> 
>> +static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
>> +                                         struct drm_bridge_state *old_state)
>> +{
>> +       struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
>> +       struct drm_atomic_state *state = old_state->base.state;
>> +       struct drm_connector_state *conn_state;
>> +       union phy_configure_opts opts = {
>> +               .dp = { .link_rate = hdmi->mode.clock * KILO }
>> +       };
>> +
>> +       /* Retrieve the connector through the atomic state */
>> +       hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
>> +
>> +       conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn);
>> +       if (WARN_ON(!conn_state))
>> +               return;
>> +
>> +       /*
>> +        * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
>> +        * stage to make sure that this IP is ready and clocked before the
>> +        * mtk_dpi gets powered on and before it enables the output.
> 
> In patch [6/15], you does not power on DPI power in DPI driver.
> Could you point out the code about 'mtk_dpi gets powered on'?
> 

DPI gets powered on in mtk_dpi_bridge_enable() -> mtk_dpi_power_on(dpi)

Cheers,
Angelo

> Regards,
> CK
> 
>> +        */
>> +       hdmi->dvi_mode = !hdmi->curr_conn->display_info.is_hdmi;
>> +       mtk_hdmi_v2_output_set_display_mode(hdmi, &hdmi->mode);
>> +
>> +       /* Reconfigure phy clock link with appropriate rate */
>> +       phy_configure(hdmi->phy, &opts);
>> +
>> +       /* Power on the PHY here to make sure that DPI_HDMI is clocked */
>> +       phy_power_on(hdmi->phy);
>> +
>> +       hdmi->powered = true;
>> +}
>> +
> 
>