[PATCH v2 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[PATCH v2 0/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Pufan Jin]

This series adds device tree support for the ALINX AX7Z020B development
board, based on the Xilinx Zynq-7000 SoC (XC7Z020-2CLG400I).

Changes in v2:
- Add an explicit mdio subnode under gem0, placing the PHY as its child
  (suggested by Andrew Lunn).
- Use hexadecimal unit-addresses for the XADC channel nodes
  (channel@a, channel@d), matching their reg values 0xa and 0xd.
- Move the pmu@f8891000 node into the initial root node block instead of
  opening a second one.
- Drop the standalone "alinx,ac7z020" compatible from the board enum: the
  SoM cannot boot on its own and is already documented as part of the
  three-entry board compatible.

Note on the vendor prefix: "alinx" is documented by a separate patch that
is already queued in linux-next, commit 1f06cd374a60 ("dt-bindings:
vendor-prefixes: Add ALINX vendor prefix"), so it is not part of this
series. A checkpatch run against a tree without that patch will report an
undocumented vendor prefix; that report is expected.

The platform consists of two physical layers:

1. ALINX AC7Z020 system on module (SoM), in zynq-alinx-ac7z020.dtsi:
   - Xilinx XC7Z020-2CLG400I SoC (dual ARM Cortex-A9, 33.333333MHz PS_CLK)
   - 1024 MiB DDR3 SDRAM (2x MT41K256M16RE-125, 32-bit bus)
   - 32 MiB QSPI Flash (Winbond W25Q256FVEI) with 4 MTD partitions
   - DevCFG FPGA manager

2. The AX7Z020B board (AC7Z020 SoM plus carrier board), described in
   zynq-alinx-ax7z020b.dts:
   - Serial console via USB-UART bridge (CP2102, MIO 48-49)
   - MicroSD slot on SDHCI0 (MIO 40-45)
   - Gigabit Ethernet via GEM0 (MIO 16-27 RGMII, MIO 52-53 MDIO)
     with JLSemi JL2121 PHY at MDIO address 1 and RJ45 link/activity LEDs
   - USB 2.0 host via USB3320C ULPI PHY (MIO 28-39), reset on MIO 46
   - Dual CAN buses (CAN0 on MIO 10-11, CAN1 on MIO 12-13) with
     SN65HVD232 transceivers
   - I2C bus on MIO 50-51 with 24LC04 EEPROM, DS1338 RTC and LM75 sensor
   - 2x SMA AD inputs and a spare differential pair wired to XADC aux
     channels VAUX1/VAUX9/VAUX12. XADC is a hard macro accessible from the
     PS without PL configuration, the channels are enabled via the
     xlnx,channels property.

Tested on hardware: boot from SD card, UART console, SD card, GbE with
iperf3 (940+ Mbps) and netdev LED trigger hardware offload, USB host,
dual CAN (SocketCAN at 500 kbps), I2C sensors, QSPI flash MTD partitions,
and XADC temperature/voltage plus the external AD aux channels via IIO.

The DTB passes CHECK_DTBS=y with no new warnings compared to the other
Zynq board files, and the bindings pass dt_binding_check.

Pufan Jin (2):
  dt-bindings: soc: xilinx: Add ALINX AX7Z020B board
  ARM: dts: zynq: Add ALINX AX7Z020B development board

 .../bindings/soc/xilinx/xilinx.yaml           |   5 +
 arch/arm/boot/dts/xilinx/Makefile             |   1 +
 .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  70 +++++++++++
 .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 142 ++++++++++++++++++
 4 files changed, 218 insertions(+)
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

-- 
2.56.0

[PATCH v2 1/2] dt-bindings: soc: xilinx: Add ALINX AX7Z020B board

[Pufan Jin]

Document the ALINX AX7Z020B development board, built around the ALINX
AC7Z020 system on module.

Link: https://www.alinx.com/
Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
---
 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df2..e3bd3d7660 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -34,6 +34,11 @@ properties:
               - xlnx,zynq-zc770-xm013
           - const: xlnx,zynq-7000
 
+      - items:
+          - const: alinx,ax7z020b
+          - const: alinx,ac7z020
+          - const: xlnx,zynq-7000
+
       - items:
           - const: avnet,zynq-microzed
           - const: xlnx,zynq-microzed
-- 
2.56.0

Re: [PATCH v2 1/2] dt-bindings: soc: xilinx: Add ALINX AX7Z020B board

[Krzysztof Kozlowski]

On Wed, Nov 11, 2026 at 11:29:16AM -0500, Pufan Jin wrote:
> Document the ALINX AX7Z020B development board, built around the ALINX
> AC7Z020 system on module.
> 
> Link: https://www.alinx.com/

Drop link, pointless in this context.

> Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
> ---

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Pufan Jin]

Add devicetree support for the ALINX AX7Z020B development board.
The board is built around the ALINX AC7Z020 system on module with a
Zynq-7000 (XC7Z020-2CLG400I) SoC, 1 GB DDR3 SDRAM and 32 MB QSPI
flash, and provides Gigabit Ethernet (JLSemi JL2121 PHY), USB 2.0
host, MicroSD slot, dual CAN buses (SN65HVD232 transceivers on
MIO 10-13), I2C RTC/EEPROM/LM75 and the serial console on UART1.
DevCFG FPGA manager is also enabled.

The two SMA AD inputs and the spare differential pair are wired to
XADC aux channels VAUX1, VAUX9 and VAUX12. The XADC hard macro is
always accessible from the PS, so expose these channels via the
driver's xlnx,channels property.

Link: https://www.alinx.com/
Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
---
 arch/arm/boot/dts/xilinx/Makefile             |   1 +
 .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  70 +++++++++
 .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 142 ++++++++++++++++++
 3 files changed, 213 insertions(+)
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
 create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

diff --git a/arch/arm/boot/dts/xilinx/Makefile b/arch/arm/boot/dts/xilinx/Makefile
index 9233e539b1..5c4bcd9492 100644
--- a/arch/arm/boot/dts/xilinx/Makefile
+++ b/arch/arm/boot/dts/xilinx/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ZYNQ) += \
+	zynq-alinx-ax7z020b.dtb \
 	zynq-cc108.dtb \
 	zynq-ebaz4205.dtb \
 	zynq-microzed.dtb \
diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
new file mode 100644
index 0000000000..1e80045cdc
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS for ALINX AC7Z020 System on Module
+ *
+ * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
+ */
+
+#include "zynq-7000.dtsi"
+
+/ {
+	compatible = "alinx,ac7z020", "xlnx,zynq-7000";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+
+	pmu@f8891000 {
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+	};
+};
+
+&clkc {
+	ps-clk-frequency = <33333333>;
+};
+
+&devcfg {
+	status = "okay";
+};
+
+&qspi {
+	bootph-all;
+	status = "okay";
+	num-cs = <1>;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "boot";
+				reg = <0x00000000 0x00500000>;
+			};
+
+			partition@500000 {
+				label = "bootenv";
+				reg = <0x00500000 0x00020000>;
+			};
+
+			partition@520000 {
+				label = "image";
+				reg = <0x00520000 0x00a80000>;
+			};
+
+			partition@fa0000 {
+				label = "spare";
+				reg = <0x00fa0000 0x01060000>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
new file mode 100644
index 0000000000..472d9fcaaf
--- /dev/null
+++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS for ALINX AX7Z020B Development Board
+ *
+ * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
+ */
+
+/dts-v1/;
+#include "zynq-alinx-ac7z020.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+	model = "ALINX AX7Z020B Development Board";
+	compatible = "alinx,ax7z020b", "alinx,ac7z020", "xlnx,zynq-7000";
+
+	aliases {
+		ethernet0 = &gem0;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		mmc0 = &sdhci0;
+		spi0 = &qspi;
+		i2c0 = &i2c0;
+	};
+
+	chosen {
+		bootargs = "";
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb_phy0: phy0 {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+		reset-gpios = <&gpio0 46 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&adc {
+	xlnx,channels {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* AD1: XADC_AD1P/N, E17/D18 */
+		channel@2 {
+			reg = <2>;
+		};
+
+		/* AD9: XADC_AD9P/N, E18/E19 */
+		channel@a {
+			reg = <10>;
+		};
+
+		/* Spare pair: XADC_AD12P/N, F19/F20 */
+		channel@d {
+			reg = <13>;
+		};
+	};
+};
+
+&can0 {
+	status = "okay";
+};
+
+&can1 {
+	status = "okay";
+};
+
+&gem0 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethernet_phy>;
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethernet_phy: ethernet-phy@1 {
+			reg = <1>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					default-state = "keep";
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_ACTIVITY;
+					default-state = "keep";
+				};
+			};
+		};
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1338";
+		reg = <0x68>;
+	};
+
+	temperature-sensor@48 {
+		compatible = "national,lm75";
+		reg = <0x48>;
+	};
+};
+
+&sdhci0 {
+	bootph-all;
+	status = "okay";
+	disable-wp;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	bootph-all;
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+	usb-phy = <&usb_phy0>;
+};
-- 
2.56.0

Re: [PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] ARM: dts: zynq: unaddressed mdio child in gem0 triggers dtc W=1
  warning
--

commit 3898a396db65d191993e3c2e496f86fb25c55e4f
Author: Pufan Jin <cyan2254650260@gmail.com>

ARM: dts: zynq: Add ALINX AX7Z020B development board

This commit adds devicetree support for the ALINX AC7Z020 system on module
and the ALINX AX7Z020B development board.

Link: https://www.alinx.com/

> diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
> new file mode 100644
> index 0000000000000..472d9fcaafa69
> --- /dev/null
> +++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

[ ... ]

> +&gem0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy>;
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethernet_phy: ethernet-phy@1 {
> +			reg = <1>;

[Severity: Low]
Does wrapping ethernet-phy@1 in an unaddressed mdio node trigger a dtc
avoid_unnecessary_addr_size warning when building with W=1?

gem0 in zynq-7000.dtsi defines #address-cells and #size-cells, so dtc warns
when its only direct child has no reg or ranges property.  Placing
ethernet-phy@1 directly under &gem0, as other Zynq-7000 boards do, or
deleting #address-cells and #size-cells on &gem0 avoids the warning.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261111162917.97532-1-cyan2254650260@gmail.com?part=2

Re: [PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Andrew Lunn]

> +&gem0 {
> +	status = "okay";
> +	phy-mode = "rgmii-id";
> +	phy-handle = <&ethernet_phy>;
> +
> +	mdio {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethernet_phy: ethernet-phy@1 {
> +			reg = <1>;
> +
> +			leds {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				led@0 {
> +					reg = <0>;
> +					color = <LED_COLOR_ID_GREEN>;
> +					function = LED_FUNCTION_LAN;
> +					default-state = "keep";
> +				};
> +
> +				led@1 {
> +					reg = <1>;
> +					color = <LED_COLOR_ID_YELLOW>;
> +					function = LED_FUNCTION_ACTIVITY;
> +					default-state = "keep";
> +				};
> +			};
> +		};
> +	};
> +};

For this part only:

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Krzysztof Kozlowski]

On Wed, Nov 11, 2026 at 11:29:17AM -0500, Pufan Jin wrote:
> Add devicetree support for the ALINX AX7Z020B development board.
> The board is built around the ALINX AC7Z020 system on module with a
> Zynq-7000 (XC7Z020-2CLG400I) SoC, 1 GB DDR3 SDRAM and 32 MB QSPI
> flash, and provides Gigabit Ethernet (JLSemi JL2121 PHY), USB 2.0
> host, MicroSD slot, dual CAN buses (SN65HVD232 transceivers on
> MIO 10-13), I2C RTC/EEPROM/LM75 and the serial console on UART1.
> DevCFG FPGA manager is also enabled.
> 
> The two SMA AD inputs and the spare differential pair are wired to
> XADC aux channels VAUX1, VAUX9 and VAUX12. The XADC hard macro is
> always accessible from the PS, so expose these channels via the
> driver's xlnx,channels property.
> 
> Link: https://www.alinx.com/

Drop link. We do not advertise websites, unless it brings some value.

> Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
> ---
>  arch/arm/boot/dts/xilinx/Makefile             |   1 +
>  .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  70 +++++++++
>  .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 142 ++++++++++++++++++
>  3 files changed, 213 insertions(+)
>  create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
>  create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts

...

> diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
> new file mode 100644
> index 0000000000..472d9fcaaf
> --- /dev/null
> +++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
> @@ -0,0 +1,142 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DTS for ALINX AX7Z020B Development Board
> + *
> + * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
> + */
> +
> +/dts-v1/;
> +#include "zynq-alinx-ac7z020.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> +	model = "ALINX AX7Z020B Development Board";
> +	compatible = "alinx,ax7z020b", "alinx,ac7z020", "xlnx,zynq-7000";
> +
> +	aliases {
> +		ethernet0 = &gem0;
> +		serial0 = &uart1;
> +		serial1 = &uart0;
> +		mmc0 = &sdhci0;
> +		spi0 = &qspi;
> +		i2c0 = &i2c0;
> +	};
> +
> +	chosen {
> +		bootargs = "";

Drop bootargs, why do you need empty ones anyway?


> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	usb_phy0: phy0 {

just "phy" or is there phy-1?

Best regards,
Krzysztof

Re: [PATCH v2 2/2] ARM: dts: zynq: Add ALINX AX7Z020B development board

[Pufan Jin]

On 11/12/26 7:08 PM, Krzysztof Kozlowski wrote:
> On Wed, Nov 11, 2026 at 11:29:17AM -0500, Pufan Jin wrote:
>> Add devicetree support for the ALINX AX7Z020B development board.
>> The board is built around the ALINX AC7Z020 system on module with a
>> Zynq-7000 (XC7Z020-2CLG400I) SoC, 1 GB DDR3 SDRAM and 32 MB QSPI
>> flash, and provides Gigabit Ethernet (JLSemi JL2121 PHY), USB 2.0
>> host, MicroSD slot, dual CAN buses (SN65HVD232 transceivers on
>> MIO 10-13), I2C RTC/EEPROM/LM75 and the serial console on UART1.
>> DevCFG FPGA manager is also enabled.
>>
>> The two SMA AD inputs and the spare differential pair are wired to
>> XADC aux channels VAUX1, VAUX9 and VAUX12. The XADC hard macro is
>> always accessible from the PS, so expose these channels via the
>> driver's xlnx,channels property.
>>
>> Link: https://www.alinx.com/
> Drop link. We do not advertise websites, unless it brings some value.
>
>> Signed-off-by: Pufan Jin <cyan2254650260@gmail.com>
>> ---
>>   arch/arm/boot/dts/xilinx/Makefile             |   1 +
>>   .../boot/dts/xilinx/zynq-alinx-ac7z020.dtsi   |  70 +++++++++
>>   .../boot/dts/xilinx/zynq-alinx-ax7z020b.dts   | 142 ++++++++++++++++++
>>   3 files changed, 213 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ac7z020.dtsi
>>   create mode 100644 arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
> ...
>
>> diff --git a/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
>> new file mode 100644
>> index 0000000000..472d9fcaaf
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/xilinx/zynq-alinx-ax7z020b.dts
>> @@ -0,0 +1,142 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * DTS for ALINX AX7Z020B Development Board
>> + *
>> + * Copyright (C) 2026 Pufan Jin <cyan2254650260@gmail.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include "zynq-alinx-ac7z020.dtsi"
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +
>> +/ {
>> +	model = "ALINX AX7Z020B Development Board";
>> +	compatible = "alinx,ax7z020b", "alinx,ac7z020", "xlnx,zynq-7000";
>> +
>> +	aliases {
>> +		ethernet0 = &gem0;
>> +		serial0 = &uart1;
>> +		serial1 = &uart0;
>> +		mmc0 = &sdhci0;
>> +		spi0 = &qspi;
>> +		i2c0 = &i2c0;
>> +	};
>> +
>> +	chosen {
>> +		bootargs = "";
> Drop bootargs, why do you need empty ones anyway?
>
>
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +
>> +	usb_phy0: phy0 {
> just "phy" or is there phy-1?
>
> Best regards,
> Krzysztof


> Drop link. We do not advertise websites, unless it brings some value.
Agreed. I've removed the link in v3.

> Drop bootargs, why do you need empty ones anyway?

The empty bootargs is not needed. I've removed it.

> just "phy" or is there phy-1?

There is only one USB PHY on this board. I've renamed the node to "phy".

Thanks for the review!

Pufan Jin