* Re: [PATCH v2 4/4] ARM64: dts: TM2: comply to the samsung pinctrl naming convention
From: Krzysztof Kozlowski @ 2017-01-06 6:49 UTC (permalink / raw)
To: Andi Shyti
Cc: Mark Rutland, devicetree, linux-samsung-soc, Andi Shyti,
Javier Martinez Canillas, Catalin Marinas, Linus Walleij,
Will Deacon, Tomasz Figa, Krzysztof Kozlowski, linux-kernel,
Chanwoo Choi, Rob Herring, Kukjin Kim, Sylwester Nawrocki, stable,
linux-arm-kernel
In-Reply-To: <20161230041421.24448-5-andi.shyti@samsung.com>
On Fri, Dec 30, 2016 at 01:14:21PM +0900, Andi Shyti wrote:
> Change the PIN() macro definition so that it can use the macros
> from pinctrl/samsung.h header file.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 25 +-
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 254 ++++++++++-----------
> 2 files changed, 133 insertions(+), 146 deletions(-)
>
Thanks, applied (here and in 3/4 with fixed subject).
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH 1/3] dt-bindings: Update QorIQ TMU thermal bindings
From: Y.T. Tang @ 2017-01-06 6:56 UTC (permalink / raw)
To: Troy Jia, Scott Wood, rui.zhang@intel.com, edubezval@gmail.com,
robh+dt@kernel.org
Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <AM4PR0401MB184304CF8DAB4FE6B6ECC13DEB600@AM4PR0401MB1843.eurprd04.prod.outlook.com>
Seems like Troy's email client has issues which causes his reply is unreadable in patchwork.
Please ignore it in patchwork.
Regards,
Yuantian
> -----Original Message-----
> From: Troy Jia
> Sent: Thursday, January 05, 2017 10:29 AM
> To: Scott Wood <oss@buserror.net>; rui.zhang@intel.com;
> edubezval@gmail.com; Y.T. Tang <yuantian.tang@nxp.com>;
> robh+dt@kernel.org
> Cc: linux-pm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: RE: [PATCH 1/3] dt-bindings: Update QorIQ TMU thermal bindings
>
>
>
> > -----Original Message-----
> > From: Scott Wood [mailto:oss@buserror.net]
> > Sent: Wednesday, January 04, 2017 6:38 PM
> > To: Troy Jia <hongtao.jia@nxp.com>; rui.zhang@intel.com;
> > edubezval@gmail.com; Y.T. Tang <yuantian.tang@nxp.com>;
> > robh+dt@kernel.org
> > Cc: linux-pm@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH 1/3] dt-bindings: Update QorIQ TMU thermal
> > bindings
> >
> > On Wed, 2017-01-04 at 16:57 +0800, Jia Hongtao wrote:
> > > For different types of SoC the sensor id and endianness may vary.
> > > "#thermal-sensor-cells" is used to provide sensor id information.
> > > "little-endian" property is to tell the endianness of TMU.
> > >
> > > Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
> > > Acked-by: Rob Herring <robh@kernel.org>
> > > ---
> > > Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 7
> > > +++++++
> > > 1 file changed, 7 insertions(+)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > > b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > > index 66223d5..20ca4ef 100644
> > > --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > > +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> > > @@ -17,6 +17,12 @@ Required properties:
> > > calibration data, as specified by the SoC reference manual.
> > > The first cell of each pair is the value to be written to TTCFGR,
> > > and the second is the value to be written to TSCFGR.
> > > +- #thermal-sensor-cells : Must be 1. The sensor specifier is the
> monitoring
> > > + site ID, and represents the "n" in TRITSRn and TRATSRn.
> >
> > I assume the driver will continue to work with existing device trees
> > where this information is absent? If so, ACK for the whole series.
>
> Yes. The driver works for all existing device trees.
>
> Thanks for the ACK.
>
> >
> > -Scott
^ permalink raw reply
* Re: [RFC 0/1] Platform driver support for 'amd5536udc' driver
From: Raviteja Garimella @ 2017-01-06 6:59 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rob Herring, Mark Rutland, Greg Kroah-Hartman, Felipe Balbi,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, BCM Kernel Feedback,
linux-usb-u79uwXL29TY76Z2rM5mHXA, John Youn
In-Reply-To: <1861880.7pouM4E6RB@wuerfel>
Hi Arnd,
On Fri, Jan 6, 2017 at 3:33 AM, Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> wrote:
> On Thursday, January 5, 2017 1:53:16 PM CET Raviteja Garimella wrote:
>> The UDC is based on Synopsys Designware core USB (2.0) Device controller
>> IP.
> ...
>> This is a request for comments from maintainers/others regarding approach
>> on whether to have 2 different drivers (one each for AMD and Broadcom)
>> with a common library (3 files in total), or have a single driver like
>> it's done in this patch and have the driver filename changed to some
>> common name based on ther underlying IP, like snps_udc.c.
>
> I have not looked at the code at all, so sorry for my ignorance, but
> isn't the IP block you describe the one that drivers/usb/dwc2/ is for?
> Could you add support for the Broadcom hardware there instead?
The current driver I submitted is for a different Synopsys IP (USB
Device Controller IP,
not the HS OTG). It's confirmed by John Youn (from Synopsys) earlier.
Thanks,
Ravi
>
> Arnd
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^ permalink raw reply
* [PATCH 0/3] ARM: at91: fix cpuidle crash on SAMA5D4 Xplained board
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: Alexandre Belloni, Russell King, Nicolas Ferre, Rob Herring,
Mark Rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Wenyou Yang,
Wenyou Yang
Fix cpuidle crash on SAMA5D4 Xplained board when enable
CONFIG_ARM_AT91_CPUIDLE. Because some SoCs have the L2 cache,
we should flush the L2 cache before entering the cpu idle.
Wenyou Yang (3):
ARM: at91: flush the L2 cache before entering cpu idle
doc: binding: add new compatible for SDRAM/DDR Controller
ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
5 files changed, 23 insertions(+), 2 deletions(-)
--
2.11.0
^ permalink raw reply
* [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: Alexandre Belloni, Russell King, Nicolas Ferre, Rob Herring,
Mark Rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Wenyou Yang,
Wenyou Yang
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache,
flush the L2 cache first before entering the cpu idle.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++
drivers/memory/atmel-sdramc.c | 1 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index b4332b727e9c..1a60dede1a01 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -289,6 +289,24 @@ static void at91_ddr_standby(void)
at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}
+static void at91_ddr_cache_standby(void)
+{
+ u32 saved_lpr;
+
+ flush_cache_all();
+ outer_disable();
+
+ saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr &
+ (~AT91_DDRSDRC_LPCB)) | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+
+ cpu_do_idle();
+
+ at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr);
+
+ outer_resume();
+}
+
/* We manage both DDRAM/SDRAM controllers, we need more than one value to
* remember.
*/
@@ -324,6 +342,7 @@ static const struct of_device_id const ramc_ids[] __initconst = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
+ { .compatible = "atmel,sama5d4-ddramc", .data = at91_ddr_cache_standby },
{ /*sentinel*/ }
};
diff --git a/drivers/memory/atmel-sdramc.c b/drivers/memory/atmel-sdramc.c
index b418b39af180..7e5c5c6c1348 100644
--- a/drivers/memory/atmel-sdramc.c
+++ b/drivers/memory/atmel-sdramc.c
@@ -48,6 +48,7 @@ static const struct of_device_id atmel_ramc_of_match[] = {
{ .compatible = "atmel,at91sam9260-sdramc", .data = &at91rm9200_caps, },
{ .compatible = "atmel,at91sam9g45-ddramc", .data = &at91sam9g45_caps, },
{ .compatible = "atmel,sama5d3-ddramc", .data = &sama5d3_caps, },
+ { .compatible = "atmel,sama5d4-ddramc", .data = &sama5d3_caps, },
{},
};
--
2.11.0
^ permalink raw reply related
* [PATCH 2/3] doc: binding: add new compatible for SDRAM/DDR Controller
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: Alexandre Belloni, Russell King, Nicolas Ferre, Rob Herring,
Mark Rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Wenyou Yang,
Wenyou Yang
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
Add the new compatible "atmel,sama5d4-ddramc" for the SDRAM/DDR
Controller.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
Documentation/devicetree/bindings/arm/atmel-at91.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 29737b9b616e..9b5de6397666 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -111,6 +111,7 @@ RAMC SDRAM/DDR Controller required properties:
"atmel,at91sam9260-sdramc",
"atmel,at91sam9g45-ddramc",
"atmel,sama5d3-ddramc",
+ "atmel,sama5d4-ddramc",
- reg: Should contain registers location and length
Examples:
--
2.11.0
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: at91: use "atmel,sama5d4-ddramc" for ramc
From: Wenyou Yang @ 2017-01-06 6:59 UTC (permalink / raw)
To: Alexandre Belloni, Russell King, Nicolas Ferre, Rob Herring,
Mark Rutland
Cc: linux-arm-kernel, devicetree, linux-kernel, Wenyou Yang,
Wenyou Yang
In-Reply-To: <20170106065947.30631-1-wenyou.yang@atmel.com>
Use the new compatible "atmel,sama5d4-ddramc" for the ramc of
SAMA5D2 and SAMA5D4.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
arch/arm/boot/dts/sama5d2.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index ceb9783ff7e1..b5259d85737d 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -380,7 +380,7 @@
};
ramc0: ramc@f000c000 {
- compatible = "atmel,sama5d3-ddramc";
+ compatible = "atmel,sama5d4-ddramc";
reg = <0xf000c000 0x200>;
clocks = <&ddrck>, <&mpddr_clk>;
clock-names = "ddrck", "mpddr";
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 4f60c1b7b137..603ba986858c 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -370,7 +370,7 @@
};
ramc0: ramc@f0010000 {
- compatible = "atmel,sama5d3-ddramc";
+ compatible = "atmel,sama5d4-ddramc";
reg = <0xf0010000 0x200>;
clocks = <&ddrck>, <&mpddr_clk>;
clock-names = "ddrck", "mpddr";
--
2.11.0
^ permalink raw reply related
* [PATCH] arm64: dts: exynos: Remove unsupported regulator-always-off property from TM2E
From: Krzysztof Kozlowski @ 2017-01-06 7:02 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Jaechul Lee
The regulator property 'regulator-always-off' is not documented and not
supported.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
index 1db4e7f363a9..398f5e092b02 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
@@ -25,7 +25,6 @@
&ldo25_reg {
regulator-name = "UNUSED_LDO25";
- regulator-always-off;
};
&ldo31_reg {
--
2.9.3
^ permalink raw reply related
* Re: [PATCH v3 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong information of ldo23 and ldo25
From: Krzysztof Kozlowski @ 2017-01-06 7:05 UTC (permalink / raw)
To: Jaechul Lee
Cc: Mark Rutland, devicetree, linux-samsung-soc, Andi Shyti,
Chanwoo Choi, Catalin Marinas, Dmitry Torokhov, Will Deacon,
linux-kernel, Rob Herring, Javier Martinez Canillas, Kukjin Kim,
Krzysztof Kozlowski, linux-input, galaxyra, beomho.seo,
linux-arm-kernel
In-Reply-To: <1483675149-32598-2-git-send-email-jcsing.lee@samsung.com>
On Fri, Jan 06, 2017 at 12:59:05PM +0900, Jaechul Lee wrote:
> From: Chanwoo Choi <cw00.choi@samsung.com>
>
> This patch fixes the wrong information of ldo23 and ldo25 on both TM2 and TM2E.
Please describe what is exactly wrong and how it affects the
system/user. This is going to the fixes so it needs a good explanation.
>
> Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 7 ++++---
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 10 ----------
> 2 files changed, 4 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> index 3b5215c..e8971f4 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -504,9 +504,9 @@
> };
>
> ldo23_reg: LDO23 {
> - regulator-name = "CAM_SEN_CORE_1.2V_AP";
> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
> regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1200000>;
> + regulator-max-microvolt = <1050000>;
> };
>
> ldo24_reg: LDO24 {
> @@ -516,9 +516,10 @@
> };
>
> ldo25_reg: LDO25 {
> - regulator-name = "CAM_SEN_A2.8V_AP";
> + regulator-name = "UNUSED_LDO25";
> regulator-min-microvolt = <2800000>;
> regulator-max-microvolt = <2800000>;
> + regulator-always-off;
Don't add it. See my other patch.
Best regards,
Krzysztof
> };
>
> ldo26_reg: LDO26 {
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 1db4e7f..854c583 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -18,16 +18,6 @@
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> -&ldo23_reg {
> - regulator-name = "CAM_SEN_CORE_1.025V_AP";
> - regulator-max-microvolt = <1050000>;
> -};
> -
> -&ldo25_reg {
> - regulator-name = "UNUSED_LDO25";
> - regulator-always-off;
> -};
> -
> &ldo31_reg {
> regulator-name = "TSP_VDD_1.8V_AP";
> regulator-min-microvolt = <1800000>;
> --
> 2.7.4
>
^ permalink raw reply
* Re: [RFC 1/1] Changes to support the driver for platform device registration
From: Raviteja Garimella @ 2017-01-06 7:09 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Mark Rutland, Greg Kroah-Hartman, Felipe Balbi,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, BCM Kernel Feedback,
linux-usb-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3d3e9fce-faae-3ff0-c42c-20f4bced663a-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi Florian,
On Thu, Jan 5, 2017 at 11:13 PM, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 01/05/2017 12:23 AM, Raviteja Garimella wrote:
>> -- Add OF based platform device registration
>> -- Modify debug prints to be compatible with both pci and platform devices
>> -- Add members to 'struct udc' for extcon and phy support
>> -- Add checks to not process repeated calls to udc connect and
>> disconnect routines
>> -- Kconfig changes
>
> What you are doing in this patch is all well and good, but since you are
> listing these changes, that means we should see 4/5 patches submitted to
> this driver each one doing what you have as a bullet point.
>
> Since you are adding Device Tree probing support to the driver, you also
> need to create a proper binding document which describes the properties
> and nodes.
I will split this patch into multiple patches, and also create the
binding document.
Thanks. I will wait a bit for any other comments.
Ravi
>
> Thank you
> --
> Florian
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^ permalink raw reply
* Re: [PATCH v3 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Krzysztof Kozlowski @ 2017-01-06 7:09 UTC (permalink / raw)
To: Jaechul Lee
Cc: Dmitry Torokhov, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Kukjin Kim, Krzysztof Kozlowski,
Javier Martinez Canillas, Andi Shyti, Chanwoo Choi, beomho.seo,
galaxyra, linux-arm-kernel, linux-input, devicetree, linux-kernel,
linux-samsung-soc
In-Reply-To: <1483675149-32598-3-git-send-email-jcsing.lee@samsung.com>
On Fri, Jan 06, 2017 at 12:59:06PM +0900, Jaechul Lee wrote:
> From: Andi Shyti <andi.shyti@samsung.com>
>
> Currently tm2e dts includes tm2 but there are some differences
> between the two boards and tm2 has some properties that tm2e
> doesn't have.
>
> That's why it's important to keep the two dts files independent
> and put all the commonalities in a tm2-common.dtsi file.
>
> At the current status the only two differences between the two
> dts files (besides the board name) are ldo31 and ldo38.
>
> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> ---
> .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1118 +++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
Like talking to a wall. Without any feedback. If my instructions were
wrong (and it is not possible to detect rename) then please say it (you
can add personal comments after separator ---).
As of now because it is third time without any explanation: NACK.
Best regards,
Krzysztof
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 22 +-
> 3 files changed, 1163 insertions(+), 1130 deletions(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> rewrite arch/arm64/boot/dts/exynos/exynos5433-tm2.dts (98%)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> new file mode 100644
> index 0000000..c43f9a3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -0,0 +1,1118 @@
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Common device tree source file for Samsung's TM2 and TM2E boards
> + * which are based on Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5433.dtsi"
> +#include <dt-bindings/clock/samsung,s2mps11.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "Samsung TM2 board";
> + compatible = "samsung,tm2", "samsung,exynos5433";
> +
> + aliases {
> + gsc0 = &gsc_0;
> + gsc1 = &gsc_1;
> + gsc2 = &gsc_2;
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_aud;
> + pinctrl2 = &pinctrl_cpif;
> + pinctrl3 = &pinctrl_ese;
> + pinctrl4 = &pinctrl_finger;
> + pinctrl5 = &pinctrl_fsys;
> + pinctrl6 = &pinctrl_imem;
> + pinctrl7 = &pinctrl_nfc;
> + pinctrl8 = &pinctrl_peric;
> + pinctrl9 = &pinctrl_touch;
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + serial2 = &serial_2;
> + serial3 = &serial_3;
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + spi3 = &spi_3;
> + spi4 = &spi_4;
> + mshc0 = &mshc_0;
> + mshc2 = &mshc_2;
> + };
> +
> + chosen {
> + stdout-path = &serial_1;
> + };
> +
> + memory@20000000 {
> + device_type = "memory";
> + reg = <0x0 0x20000000 0x0 0xc0000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power-key {
> + gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + label = "power key";
> + debounce-interval = <10>;
> + };
> +
> + volume-up-key {
> + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + label = "volume-up key";
> + debounce-interval = <10>;
> + };
> +
> + volume-down-key {
> + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + label = "volume-down key";
> + debounce-interval = <10>;
> + };
> +
> + homepage-key {
> + gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_MENU>;
> + label = "homepage key";
> + debounce-interval = <10>;
> + };
> + };
> +
> + i2c_max98504: i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> + &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max98504: max98504@31 {
> + compatible = "maxim,max98504";
> + reg = <0x31>;
> + maxim,rx-path = <1>;
> + maxim,tx-path = <1>;
> + maxim,tx-channel-mask = <3>;
> + maxim,tx-channel-source = <2>;
> + };
> + };
> +
> + sound {
> + compatible = "samsung,tm2-audio";
> + audio-codec = <&wm5110>;
> + i2s-controller = <&i2s0>;
> + audio-amplifier = <&max98504>;
> + mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> + model = "wm5110";
> + samsung,audio-routing =
> + /* Headphone */
> + "HP", "HPOUT1L",
> + "HP", "HPOUT1R",
> +
> + /* Speaker */
> + "SPK", "SPKOUT",
> + "SPKOUT", "HPOUT2L",
> + "SPKOUT", "HPOUT2R",
> +
> + /* Receiver */
> + "RCV", "HPOUT3L",
> + "RCV", "HPOUT3R";
> + status = "okay";
> + };
> +};
> +
> +&adc {
> + vdd-supply = <&ldo3_reg>;
> + status = "okay";
> +
> + thermistor-ap {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 0>;
> + };
> +
> + thermistor-battery {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 1>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + thermistor-charger {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 2>;
> + };
> +};
> +
> +&bus_g2d_400 {
> + devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
> + vdd-supply = <&buck4_reg>;
> + exynos,saturation-ratio = <10>;
> + status = "okay";
> +};
> +
> +&bus_g2d_266 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_gscl {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_hevc {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_jpeg {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_mfc {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_mscl {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc0 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc1 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&bus_noc2 {
> + devfreq = <&bus_g2d_400>;
> + status = "okay";
> +};
> +
> +&cmu_aud {
> + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> +};
> +
> +&cmu_fsys {
> + assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> + <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
> + <&cmu_top CLK_DIV_SCLK_USBDRD30>,
> + <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> + assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> + assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> + <66700000>, <66700000>;
> +};
> +
> +&cmu_gscl {
> + assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
> + <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
> + <&cmu_top CLK_ACLK_GSCL_333>;
> +};
> +
> +&cmu_mfc {
> + assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
> +};
> +
> +&cmu_mscl {
> + assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
> + <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
> + assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
> + <&cmu_top CLK_SCLK_JPEG_MSCL>,
> + <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> +};
> +
> +&cpu0 {
> + cpu-supply = <&buck3_reg>;
> +};
> +
> +&cpu4 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&decon {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&dsi {
> + status = "okay";
> + vddcore-supply = <&ldo6_reg>;
> + vddio-supply = <&ldo7_reg>;
> + samsung,pll-clock-frequency = <24000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&te_irq>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + dsi_out: endpoint {
> + samsung,burst-clock-frequency = <512000000>;
> + samsung,esc-clock-frequency = <16000000>;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_0 {
> + status = "okay";
> + clock-frequency = <2500000>;
> +
> + s2mps13-pmic@66 {
> + compatible = "samsung,s2mps13-pmic";
> + interrupt-parent = <&gpa0>;
> + interrupts = <7 IRQ_TYPE_NONE>;
> + reg = <0x66>;
> + samsung,s2mps11-wrstbi-ground;
> +
> + s2mps13_osc: clocks {
> + compatible = "samsung,s2mps13-clk";
> + #clock-cells = <1>;
> + clock-output-names = "s2mps13_ap", "s2mps13_cp",
> + "s2mps13_bt";
> + };
> +
> + regulators: regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VDD_ALIVE_0.9V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "VDDQ_MMC2_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VDD1_E_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "VDD10_DPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VDD10_MIPI2L_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VDD18_MIPI2L_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VDD18_LLI_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VDD33_USB30_3.0V_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VDD_INT_M_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VDD_KFC_M_1.1V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + ldo13_reg: LDO13 {
> + regulator-name = "VDD_G3D_M_0.95V_AP";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VDDQ_EFUSE";
> + regulator-min-microvolt = <1400000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-always-on;
> + };
> +
> + ldo17_reg: LDO17 {
> + regulator-name = "V_TFLASH_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo18_reg: LDO18 {
> + regulator-name = "V_CODEC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19_reg: LDO19 {
> + regulator-name = "VDDA_1.8V_COMP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VCC_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VT_CAM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "CAM_IO_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1050000>;
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "VT_CAM_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo25_reg: LDO25 {
> + regulator-name = "UNUSED_LDO25";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-off;
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "CAM_AF_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo27_reg: LDO27 {
> + regulator-name = "VCC_3.0V_LCD_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo28_reg: LDO28 {
> + regulator-name = "VCC_1.8V_LCD_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo29_reg: LDO29 {
> + regulator-name = "VT_CAM_2.8V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo30_reg: LDO30 {
> + regulator-name = "TSP_AVDD_3.3V_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + /*
> + * LDO31 differs from target to target,
> + * its definition is in the .dts
> + */
> +
> + ldo32_reg: LDO32 {
> + regulator-name = "VTOUCH_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo33_reg: LDO33 {
> + regulator-name = "VTOUCH_LED_3.3V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <12500>;
> + };
> +
> + ldo34_reg: LDO34 {
> + regulator-name = "VCC_1.8V_MHL_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2100000>;
> + };
> +
> + ldo35_reg: LDO35 {
> + regulator-name = "OIS_VM_2.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo36_reg: LDO36 {
> + regulator-name = "VSIL_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + };
> +
> + ldo37_reg: LDO37 {
> + regulator-name = "VF_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + /*
> + * LDO38 differs from target to target,
> + * its definition is in the .dts
> + */
> +
> + ldo39_reg: LDO39 {
> + regulator-name = "V_HRM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo40_reg: LDO40 {
> + regulator-name = "V_HRM_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "VDD_MIF_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "VDD_EGL_1.0V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "VDD_KFC_1.0V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "VDD_INT_0.95V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "VDD_G3D_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "VDD_MEM1_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "VDD_LLDO_1.35V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "VDD_MLDO_2.0V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck10_reg: BUCK10 {
> + regulator-name = "vdd_mem2";
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_8 {
> + status = "okay";
> +
> + max77843@66 {
> + compatible = "maxim,max77843";
> + interrupt-parent = <&gpa1>;
> + interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> + reg = <0x66>;
> +
> + muic: max77843-muic {
> + compatible = "maxim,max77843-muic";
> + };
> +
> + regulators {
> + compatible = "maxim,max77843-regulator";
> + safeout1_reg: SAFEOUT1 {
> + regulator-name = "SAFEOUT1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + safeout2_reg: SAFEOUT2 {
> + regulator-name = "SAFEOUT2";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + charger_reg: CHARGER {
> + regulator-name = "CHARGER";
> + regulator-min-microamp = <100000>;
> + regulator-max-microamp = <3150000>;
> + };
> + };
> +
> + haptic: max77843-haptic {
> + compatible = "maxim,max77843-haptic";
> + haptic-supply = <&ldo38_reg>;
> + pwms = <&pwm 0 33670 0>;
> + pwm-names = "haptic";
> + };
> + };
> +};
> +
> +&i2s0 {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + status = "okay";
> + num-slots = <1>;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + cap-mmc-highspeed;
> + non-removable;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + samsung,dw-mshc-hs400-timing = <0 3>;
> + samsung,read-strobe-delay = <90>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> + &sd0_bus8 &sd0_rdqs>;
> + bus-width = <8>;
> + assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> + assigned-clock-rates = <800000000>;
> +};
> +
> +&mshc_2 {
> + status = "okay";
> + num-slots = <1>;
> + cap-sd-highspeed;
> + disable-wp;
> + cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
> + bus-width = <4>;
> +};
> +
> +&ppmu_d0_general {
> + status = "okay";
> + events {
> + ppmu_event0_d0_general: ppmu-event0-d0-general {
> + event-name = "ppmu-event0-d0-general";
> + };
> + };
> +};
> +
> +&ppmu_d1_general {
> + status = "okay";
> + events {
> + ppmu_event0_d1_general: ppmu-event0-d1-general {
> + event-name = "ppmu-event0-d1-general";
> + };
> + };
> +};
> +
> +&pinctrl_alive {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_alive>;
> +
> + initial_alive: initial-state {
> + PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-3, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa0-6, NONE, FAST_SR1);
> + PIN(INPUT, gpa0-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa1-0, UP, FAST_SR1);
> + PIN(INPUT, gpa1-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpa1-5, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-6, NONE, FAST_SR1);
> + PIN(INPUT, gpa1-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa2-0, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-1, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpa2-7, NONE, FAST_SR1);
> +
> + PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-2, NONE, FAST_SR1);
> + PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-4, NONE, FAST_SR1);
> + PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf1-0, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-1, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf1-4, UP, FAST_SR1);
> + PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
> + PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf3-2, NONE, FAST_SR1);
> + PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
> + PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
> + PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
> + };
> +
> + te_irq: te_irq {
> + samsung,pins = "gpf1-3";
> + samsung,pin-function = <0xf>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_cpif>;
> +
> + initial_cpif: initial-state {
> + PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_ese {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_ese>;
> +
> + initial_ese: initial-state {
> + PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_fsys {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_fsys>;
> +
> + initial_fsys: initial-state {
> + PIN(INPUT, gpr3-0, NONE, FAST_SR1);
> + PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpr3-7, NONE, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_imem {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_imem>;
> +
> + initial_imem: initial-state {
> + PIN(INPUT, gpf0-0, UP, FAST_SR1);
> + PIN(INPUT, gpf0-1, UP, FAST_SR1);
> + PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-3, UP, FAST_SR1);
> + PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-5, NONE, FAST_SR1);
> + PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
> + PIN(INPUT, gpf0-7, UP, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_nfc>;
> +
> + initial_nfc: initial-state {
> + PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_peric {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_peric>;
> +
> + initial_peric: initial-state {
> + PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-2, NONE, FAST_SR1);
> + PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
> + PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpc3-4, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-5, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-6, NONE, FAST_SR1);
> + PIN(INPUT, gpc3-7, NONE, FAST_SR1);
> +
> + PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
> + PIN(2, gpg0-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd4-0, NONE, FAST_SR1);
> + PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpd8-1, UP, FAST_SR1);
> +
> + PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
> + PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
> +
> + PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
> + PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pinctrl_touch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_touch>;
> +
> + initial_touch: initial-state {
> + PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm0_out>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mic {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&pmu_system_controller {
> + assigned-clocks = <&pmu_system_controller 0>;
> + assigned-clock-parents = <&xxti>;
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&spi_1 {
> + cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + wm5110: wm5110-codec@0 {
> + compatible = "wlf,wm5110";
> + reg = <0x0>;
> + spi-max-frequency = <20000000>;
> + interrupt-parent = <&gpa0>;
> + interrupts = <4 IRQ_TYPE_NONE>;
> + clocks = <&pmu_system_controller 0>,
> + <&s2mps13_osc S2MPS11_CLK_BT>;
> + clock-names = "mclk1", "mclk2";
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + wlf,micd-detect-debounce = <300>;
> + wlf,micd-bias-start-time = <0x1>;
> + wlf,micd-rate = <0x7>;
> + wlf,micd-dbtime = <0x1>;
> + wlf,micd-force-micbias;
> + wlf,micd-configs = <0x0 1 0>;
> + wlf,hpdet-channel = <1>;
> + wlf,gpsw = <0x1>;
> + wlf,inmode = <2 0 2 0>;
> +
> + wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> + wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> +
> + /* core supplies */
> + AVDD-supply = <&ldo18_reg>;
> + DBVDD1-supply = <&ldo18_reg>;
> + CPVDD-supply = <&ldo18_reg>;
> + DBVDD2-supply = <&ldo18_reg>;
> + DBVDD3-supply = <&ldo18_reg>;
> +
> + controller-data {
> + samsung,spi-feedback-delay = <0>;
> + };
> + };
> +};
> +
> +&timer {
> + clock-frequency = <24000000>;
> +};
> +
> +&tmu_atlas0 {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_apollo {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_g3d {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd30 {
> + vdd33-supply = <&ldo10_reg>;
> + vdd10-supply = <&ldo6_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd_dwc3_0 {
> + dr_mode = "otg";
> +};
> +
> +&usbdrd30_phy {
> + vbus-supply = <&safeout1_reg>;
> + status = "okay";
> +};
> +
> +&xxti {
> + clock-frequency = <24000000>;
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> dissimilarity index 98%
> index e8971f4..d30b45a 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -1,1120 +1,33 @@
> -/*
> - * SAMSUNG Exynos5433 TM2 board device tree source
> - *
> - * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> - *
> - * Device tree source file for Samsung's TM2 board which is based on
> - * Samsung Exynos5433 SoC.
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -/dts-v1/;
> -#include "exynos5433.dtsi"
> -#include <dt-bindings/clock/samsung,s2mps11.h>
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/input/input.h>
> -#include <dt-bindings/interrupt-controller/irq.h>
> -
> -/ {
> - model = "Samsung TM2 board";
> - compatible = "samsung,tm2", "samsung,exynos5433";
> -
> - aliases {
> - gsc0 = &gsc_0;
> - gsc1 = &gsc_1;
> - gsc2 = &gsc_2;
> - pinctrl0 = &pinctrl_alive;
> - pinctrl1 = &pinctrl_aud;
> - pinctrl2 = &pinctrl_cpif;
> - pinctrl3 = &pinctrl_ese;
> - pinctrl4 = &pinctrl_finger;
> - pinctrl5 = &pinctrl_fsys;
> - pinctrl6 = &pinctrl_imem;
> - pinctrl7 = &pinctrl_nfc;
> - pinctrl8 = &pinctrl_peric;
> - pinctrl9 = &pinctrl_touch;
> - serial0 = &serial_0;
> - serial1 = &serial_1;
> - serial2 = &serial_2;
> - serial3 = &serial_3;
> - spi0 = &spi_0;
> - spi1 = &spi_1;
> - spi2 = &spi_2;
> - spi3 = &spi_3;
> - spi4 = &spi_4;
> - mshc0 = &mshc_0;
> - mshc2 = &mshc_2;
> - };
> -
> - chosen {
> - stdout-path = &serial_1;
> - };
> -
> - memory@20000000 {
> - device_type = "memory";
> - reg = <0x0 0x20000000 0x0 0xc0000000>;
> - };
> -
> - gpio-keys {
> - compatible = "gpio-keys";
> -
> - power-key {
> - gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_POWER>;
> - label = "power key";
> - debounce-interval = <10>;
> - };
> -
> - volume-up-key {
> - gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEUP>;
> - label = "volume-up key";
> - debounce-interval = <10>;
> - };
> -
> - volume-down-key {
> - gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_VOLUMEDOWN>;
> - label = "volume-down key";
> - debounce-interval = <10>;
> - };
> -
> - homepage-key {
> - gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> - linux,code = <KEY_MENU>;
> - label = "homepage key";
> - debounce-interval = <10>;
> - };
> - };
> -
> - i2c_max98504: i2c-gpio-0 {
> - compatible = "i2c-gpio";
> - gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> - &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> - i2c-gpio,delay-us = <2>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> - status = "okay";
> -
> - max98504: max98504@31 {
> - compatible = "maxim,max98504";
> - reg = <0x31>;
> - maxim,rx-path = <1>;
> - maxim,tx-path = <1>;
> - maxim,tx-channel-mask = <3>;
> - maxim,tx-channel-source = <2>;
> - };
> - };
> -
> - sound {
> - compatible = "samsung,tm2-audio";
> - audio-codec = <&wm5110>;
> - i2s-controller = <&i2s0>;
> - audio-amplifier = <&max98504>;
> - mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> - model = "wm5110";
> - samsung,audio-routing =
> - /* Headphone */
> - "HP", "HPOUT1L",
> - "HP", "HPOUT1R",
> -
> - /* Speaker */
> - "SPK", "SPKOUT",
> - "SPKOUT", "HPOUT2L",
> - "SPKOUT", "HPOUT2R",
> -
> - /* Receiver */
> - "RCV", "HPOUT3L",
> - "RCV", "HPOUT3R";
> - status = "okay";
> - };
> -};
> -
> -&adc {
> - vdd-supply = <&ldo3_reg>;
> - status = "okay";
> -
> - thermistor-ap {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 0>;
> - };
> -
> - thermistor-battery {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 1>;
> - #thermal-sensor-cells = <0>;
> - };
> -
> - thermistor-charger {
> - compatible = "murata,ncp03wf104";
> - pullup-uv = <1800000>;
> - pullup-ohm = <100000>;
> - pulldown-ohm = <0>;
> - io-channels = <&adc 2>;
> - };
> -};
> -
> -&bus_g2d_400 {
> - devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
> - vdd-supply = <&buck4_reg>;
> - exynos,saturation-ratio = <10>;
> - status = "okay";
> -};
> -
> -&bus_g2d_266 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_gscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_hevc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_jpeg {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mfc {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_mscl {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc0 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc1 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&bus_noc2 {
> - devfreq = <&bus_g2d_400>;
> - status = "okay";
> -};
> -
> -&cmu_aud {
> - assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> - assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> -};
> -
> -&cmu_fsys {
> - assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> - <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> - <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
> - <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
> - <&cmu_top CLK_DIV_SCLK_USBDRD30>,
> - <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> - assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>,
> - <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> - <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
> - <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> - assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
> - <66700000>, <66700000>;
> -};
> -
> -&cmu_gscl {
> - assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
> - <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
> - <&cmu_top CLK_ACLK_GSCL_333>;
> -};
> -
> -&cmu_mfc {
> - assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
> -};
> -
> -&cmu_mscl {
> - assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
> - <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
> - assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
> - <&cmu_top CLK_SCLK_JPEG_MSCL>,
> - <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
> - <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> -};
> -
> -&cpu0 {
> - cpu-supply = <&buck3_reg>;
> -};
> -
> -&cpu4 {
> - cpu-supply = <&buck2_reg>;
> -};
> -
> -&decon {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&dsi {
> - status = "okay";
> - vddcore-supply = <&ldo6_reg>;
> - vddio-supply = <&ldo7_reg>;
> - samsung,pll-clock-frequency = <24000000>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&te_irq>;
> -
> - ports {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - port@1 {
> - reg = <1>;
> -
> - dsi_out: endpoint {
> - samsung,burst-clock-frequency = <512000000>;
> - samsung,esc-clock-frequency = <16000000>;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_0 {
> - status = "okay";
> - clock-frequency = <2500000>;
> -
> - s2mps13-pmic@66 {
> - compatible = "samsung,s2mps13-pmic";
> - interrupt-parent = <&gpa0>;
> - interrupts = <7 IRQ_TYPE_NONE>;
> - reg = <0x66>;
> - samsung,s2mps11-wrstbi-ground;
> -
> - s2mps13_osc: clocks {
> - compatible = "samsung,s2mps13-clk";
> - #clock-cells = <1>;
> - clock-output-names = "s2mps13_ap", "s2mps13_cp",
> - "s2mps13_bt";
> - };
> -
> - regulators {
> - ldo1_reg: LDO1 {
> - regulator-name = "VDD_ALIVE_0.9V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <900000>;
> - regulator-always-on;
> - };
> -
> - ldo2_reg: LDO2 {
> - regulator-name = "VDDQ_MMC2_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo3_reg: LDO3 {
> - regulator-name = "VDD1_E_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo4_reg: LDO4 {
> - regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> - regulator-min-microvolt = <1300000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo5_reg: LDO5 {
> - regulator-name = "VDD10_DPLL_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo6_reg: LDO6 {
> - regulator-name = "VDD10_MIPI2L_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo7_reg: LDO7 {
> - regulator-name = "VDD18_MIPI2L_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo8_reg: LDO8 {
> - regulator-name = "VDD18_LLI_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo9_reg: LDO9 {
> - regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo10_reg: LDO10 {
> - regulator-name = "VDD33_USB30_3.0V_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo11_reg: LDO11 {
> - regulator-name = "VDD_INT_M_1.0V_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo12_reg: LDO12 {
> - regulator-name = "VDD_KFC_M_1.1V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1350000>;
> - regulator-always-on;
> - };
> -
> - ldo13_reg: LDO13 {
> - regulator-name = "VDD_G3D_M_0.95V_AP";
> - regulator-min-microvolt = <950000>;
> - regulator-max-microvolt = <950000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo14_reg: LDO14 {
> - regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo15_reg: LDO15 {
> - regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - ldo16_reg: LDO16 {
> - regulator-name = "VDDQ_EFUSE";
> - regulator-min-microvolt = <1400000>;
> - regulator-max-microvolt = <3400000>;
> - regulator-always-on;
> - };
> -
> - ldo17_reg: LDO17 {
> - regulator-name = "V_TFLASH_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo18_reg: LDO18 {
> - regulator-name = "V_CODEC_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo19_reg: LDO19 {
> - regulator-name = "VDDA_1.8V_COMP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - regulator-always-on;
> - };
> -
> - ldo20_reg: LDO20 {
> - regulator-name = "VCC_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-on;
> - };
> -
> - ldo21_reg: LDO21 {
> - regulator-name = "VT_CAM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo22_reg: LDO22 {
> - regulator-name = "CAM_IO_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo23_reg: LDO23 {
> - regulator-name = "CAM_SEN_CORE_1.05V_AP";
> - regulator-min-microvolt = <1050000>;
> - regulator-max-microvolt = <1050000>;
> - };
> -
> - ldo24_reg: LDO24 {
> - regulator-name = "VT_CAM_1.2V";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - };
> -
> - ldo25_reg: LDO25 {
> - regulator-name = "UNUSED_LDO25";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - regulator-always-off;
> - };
> -
> - ldo26_reg: LDO26 {
> - regulator-name = "CAM_AF_2.8V_AP";
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo27_reg: LDO27 {
> - regulator-name = "VCC_3.0V_LCD_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo28_reg: LDO28 {
> - regulator-name = "VCC_1.8V_LCD_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo29_reg: LDO29 {
> - regulator-name = "VT_CAM_2.8V";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo30_reg: LDO30 {
> - regulator-name = "TSP_AVDD_3.3V_AP";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - ldo31_reg: LDO31 {
> - regulator-name = "TSP_VDD_1.85V_AP";
> - regulator-min-microvolt = <1850000>;
> - regulator-max-microvolt = <1850000>;
> - };
> -
> - ldo32_reg: LDO32 {
> - regulator-name = "VTOUCH_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo33_reg: LDO33 {
> - regulator-name = "VTOUCH_LED_3.3V";
> - regulator-min-microvolt = <2500000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-ramp-delay = <12500>;
> - };
> -
> - ldo34_reg: LDO34 {
> - regulator-name = "VCC_1.8V_MHL_AP";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <2100000>;
> - };
> -
> - ldo35_reg: LDO35 {
> - regulator-name = "OIS_VM_2.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <2800000>;
> - };
> -
> - ldo36_reg: LDO36 {
> - regulator-name = "VSIL_1.0V";
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1000000>;
> - };
> -
> - ldo37_reg: LDO37 {
> - regulator-name = "VF_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo38_reg: LDO38 {
> - regulator-name = "VCC_3.0V_MOTOR_AP";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - };
> -
> - ldo39_reg: LDO39 {
> - regulator-name = "V_HRM_1.8V";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> - };
> -
> - ldo40_reg: LDO40 {
> - regulator-name = "V_HRM_3.3V";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - buck1_reg: BUCK1 {
> - regulator-name = "VDD_MIF_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck2_reg: BUCK2 {
> - regulator-name = "VDD_EGL_1.0V_AP";
> - regulator-min-microvolt = <900000>;
> - regulator-max-microvolt = <1300000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck3_reg: BUCK3 {
> - regulator-name = "VDD_KFC_1.0V_AP";
> - regulator-min-microvolt = <800000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck4_reg: BUCK4 {
> - regulator-name = "VDD_INT_0.95V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck5_reg: BUCK5 {
> - regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck6_reg: BUCK6 {
> - regulator-name = "VDD_G3D_0.9V_AP";
> - regulator-min-microvolt = <600000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - regulator-state-mem {
> - regulator-off-in-suspend;
> - };
> - };
> -
> - buck7_reg: BUCK7 {
> - regulator-name = "VDD_MEM1_1.2V_AP";
> - regulator-min-microvolt = <1200000>;
> - regulator-max-microvolt = <1200000>;
> - regulator-always-on;
> - };
> -
> - buck8_reg: BUCK8 {
> - regulator-name = "VDD_LLDO_1.35V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck9_reg: BUCK9 {
> - regulator-name = "VDD_MLDO_2.0V_AP";
> - regulator-min-microvolt = <1350000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-always-on;
> - };
> -
> - buck10_reg: BUCK10 {
> - regulator-name = "vdd_mem2";
> - regulator-min-microvolt = <550000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-always-on;
> - };
> - };
> - };
> -};
> -
> -&hsi2c_8 {
> - status = "okay";
> -
> - max77843@66 {
> - compatible = "maxim,max77843";
> - interrupt-parent = <&gpa1>;
> - interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> - reg = <0x66>;
> -
> - muic: max77843-muic {
> - compatible = "maxim,max77843-muic";
> - };
> -
> - regulators {
> - compatible = "maxim,max77843-regulator";
> - safeout1_reg: SAFEOUT1 {
> - regulator-name = "SAFEOUT1";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - safeout2_reg: SAFEOUT2 {
> - regulator-name = "SAFEOUT2";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <4950000>;
> - };
> -
> - charger_reg: CHARGER {
> - regulator-name = "CHARGER";
> - regulator-min-microamp = <100000>;
> - regulator-max-microamp = <3150000>;
> - };
> - };
> -
> - haptic: max77843-haptic {
> - compatible = "maxim,max77843-haptic";
> - haptic-supply = <&ldo38_reg>;
> - pwms = <&pwm 0 33670 0>;
> - pwm-names = "haptic";
> - };
> - };
> -};
> -
> -&i2s0 {
> - status = "okay";
> -};
> -
> -&mshc_0 {
> - status = "okay";
> - num-slots = <1>;
> - mmc-hs200-1_8v;
> - mmc-hs400-1_8v;
> - cap-mmc-highspeed;
> - non-removable;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - samsung,dw-mshc-hs400-timing = <0 3>;
> - samsung,read-strobe-delay = <90>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> - &sd0_bus8 &sd0_rdqs>;
> - bus-width = <8>;
> - assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> - assigned-clock-rates = <800000000>;
> -};
> -
> -&mshc_2 {
> - status = "okay";
> - num-slots = <1>;
> - cap-sd-highspeed;
> - disable-wp;
> - cd-gpios = <&gpa2 4 GPIO_ACTIVE_HIGH>;
> - cd-inverted;
> - card-detect-delay = <200>;
> - samsung,dw-mshc-ciu-div = <3>;
> - samsung,dw-mshc-sdr-timing = <0 4>;
> - samsung,dw-mshc-ddr-timing = <0 2>;
> - fifo-depth = <0x80>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
> - bus-width = <4>;
> -};
> -
> -&ppmu_d0_general {
> - status = "okay";
> - events {
> - ppmu_event0_d0_general: ppmu-event0-d0-general {
> - event-name = "ppmu-event0-d0-general";
> - };
> - };
> -};
> -
> -&ppmu_d1_general {
> - status = "okay";
> - events {
> - ppmu_event0_d1_general: ppmu-event0-d1-general {
> - event-name = "ppmu-event0-d1-general";
> - };
> - };
> -};
> -
> -&pinctrl_alive {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_alive>;
> -
> - initial_alive: initial-state {
> - PIN(INPUT, gpa0-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-3, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa0-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa0-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa1-0, UP, FAST_SR1);
> - PIN(INPUT, gpa1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpa1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-6, NONE, FAST_SR1);
> - PIN(INPUT, gpa1-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa2-0, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-1, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa2-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa2-7, NONE, FAST_SR1);
> -
> - PIN(INPUT, gpa3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpa3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpa3-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf1-0, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-1, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-4, UP, FAST_SR1);
> - PIN(OUTPUT, gpf1-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf1-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf1-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf2-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf3-2, NONE, FAST_SR1);
> - PIN(INPUT, gpf3-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf4-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf4-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpf5-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-3, DOWN, FAST_SR1);
> - PIN(OUTPUT, gpf5-4, NONE, FAST_SR1);
> - PIN(INPUT, gpf5-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf5-7, DOWN, FAST_SR1);
> - };
> -
> - te_irq: te_irq {
> - samsung,pins = "gpf1-3";
> - samsung,pin-function = <0xf>;
> - };
> -};
> -
> -&pinctrl_cpif {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_cpif>;
> -
> - initial_cpif: initial-state {
> - PIN(INPUT, gpv6-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv6-1, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_ese {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_ese>;
> -
> - initial_ese: initial-state {
> - PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_fsys {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_fsys>;
> -
> - initial_fsys: initial-state {
> - PIN(INPUT, gpr3-0, NONE, FAST_SR1);
> - PIN(INPUT, gpr3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpr3-7, NONE, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_imem {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_imem>;
> -
> - initial_imem: initial-state {
> - PIN(INPUT, gpf0-0, UP, FAST_SR1);
> - PIN(INPUT, gpf0-1, UP, FAST_SR1);
> - PIN(INPUT, gpf0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-3, UP, FAST_SR1);
> - PIN(INPUT, gpf0-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-5, NONE, FAST_SR1);
> - PIN(INPUT, gpf0-6, DOWN, FAST_SR1);
> - PIN(INPUT, gpf0-7, UP, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_nfc {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_nfc>;
> -
> - initial_nfc: initial-state {
> - PIN(INPUT, gpj0-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_peric {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_peric>;
> -
> - initial_peric: initial-state {
> - PIN(INPUT, gpv7-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-2, NONE, FAST_SR1);
> - PIN(INPUT, gpv7-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-4, DOWN, FAST_SR1);
> - PIN(INPUT, gpv7-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpb0-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc0-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpc0-7, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc1-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpc3-4, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-5, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-6, NONE, FAST_SR1);
> - PIN(INPUT, gpc3-7, NONE, FAST_SR1);
> -
> - PIN(OUTPUT, gpg0-0, NONE, FAST_SR1);
> - PIN(2, gpg0-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd2-5, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd4-0, NONE, FAST_SR1);
> - PIN(INPUT, gpd4-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpd4-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd6-3, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpd8-1, UP, FAST_SR1);
> -
> - PIN(INPUT, gpg1-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-2, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-3, DOWN, FAST_SR1);
> - PIN(INPUT, gpg1-4, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg2-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg2-1, DOWN, FAST_SR1);
> -
> - PIN(INPUT, gpg3-0, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-1, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-5, DOWN, FAST_SR1);
> - PIN(INPUT, gpg3-7, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pinctrl_touch {
> - pinctrl-names = "default";
> - pinctrl-0 = <&initial_touch>;
> -
> - initial_touch: initial-state {
> - PIN(INPUT, gpj1-2, DOWN, FAST_SR1);
> - };
> -};
> -
> -&pwm {
> - pinctrl-0 = <&pwm0_out>;
> - pinctrl-names = "default";
> - status = "okay";
> -};
> -
> -&mic {
> - status = "okay";
> -
> - i80-if-timings {
> - };
> -};
> -
> -&pmu_system_controller {
> - assigned-clocks = <&pmu_system_controller 0>;
> - assigned-clock-parents = <&xxti>;
> -};
> -
> -&serial_1 {
> - status = "okay";
> -};
> -
> -&spi_1 {
> - cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> - status = "okay";
> -
> - wm5110: wm5110-codec@0 {
> - compatible = "wlf,wm5110";
> - reg = <0x0>;
> - spi-max-frequency = <20000000>;
> - interrupt-parent = <&gpa0>;
> - interrupts = <4 IRQ_TYPE_NONE>;
> - clocks = <&pmu_system_controller 0>,
> - <&s2mps13_osc S2MPS11_CLK_BT>;
> - clock-names = "mclk1", "mclk2";
> -
> - gpio-controller;
> - #gpio-cells = <2>;
> -
> - wlf,micd-detect-debounce = <300>;
> - wlf,micd-bias-start-time = <0x1>;
> - wlf,micd-rate = <0x7>;
> - wlf,micd-dbtime = <0x1>;
> - wlf,micd-force-micbias;
> - wlf,micd-configs = <0x0 1 0>;
> - wlf,hpdet-channel = <1>;
> - wlf,gpsw = <0x1>;
> - wlf,inmode = <2 0 2 0>;
> -
> - wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> - wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> -
> - /* core supplies */
> - AVDD-supply = <&ldo18_reg>;
> - DBVDD1-supply = <&ldo18_reg>;
> - CPVDD-supply = <&ldo18_reg>;
> - DBVDD2-supply = <&ldo18_reg>;
> - DBVDD3-supply = <&ldo18_reg>;
> -
> - controller-data {
> - samsung,spi-feedback-delay = <0>;
> - };
> - };
> -};
> -
> -&timer {
> - clock-frequency = <24000000>;
> -};
> -
> -&tmu_atlas0 {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_apollo {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&tmu_g3d {
> - vtmu-supply = <&ldo3_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd30 {
> - vdd33-supply = <&ldo10_reg>;
> - vdd10-supply = <&ldo6_reg>;
> - status = "okay";
> -};
> -
> -&usbdrd_dwc3_0 {
> - dr_mode = "otg";
> -};
> -
> -&usbdrd30_phy {
> - vbus-supply = <&safeout1_reg>;
> - status = "okay";
> -};
> -
> -&xxti {
> - clock-frequency = <24000000>;
> -};
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2 board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos5433-tm2-common.dtsi"
> +
> +/ {
> + model = "Samsung TM2E board";
> + compatible = "samsung,tm2e", "samsung,exynos5433";
> +};
> +
> +®ulators {
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.85V_AP";
> + regulator-min-microvolt = <1850000>;
> + regulator-max-microvolt = <1850000>;
> + };
> +
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.0V_MOTOR_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> index 854c583..53e361f 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -11,21 +11,23 @@
> * published by the Free Software Foundation.
> */
>
> -#include "exynos5433-tm2.dts"
> +#include "exynos5433-tm2-common.dtsi"
>
> / {
> model = "Samsung TM2E board";
> compatible = "samsung,tm2e", "samsung,exynos5433";
> };
>
> -&ldo31_reg {
> - regulator-name = "TSP_VDD_1.8V_AP";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <1800000>;
> -};
> +®ulators {
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
>
> -&ldo38_reg {
> - regulator-name = "VCC_3.3V_MOTOR_AP";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.3V_MOTOR_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v3 4/4] phy: qcom-qmp: new qmp phy driver for qcom-chipsets
From: Bjorn Andersson @ 2017-01-06 7:18 UTC (permalink / raw)
To: Vivek Gautam
Cc: robh+dt, kishon, sboyd, linux-kernel, devicetree, mark.rutland,
srinivas.kandagatla, linux-arm-msm
In-Reply-To: <1482253431-23160-5-git-send-email-vivek.gautam@codeaurora.org>
On Tue 20 Dec 09:03 PST 2016, Vivek Gautam wrote:
> diff --git a/drivers/phy/phy-qcom-qmp.c b/drivers/phy/phy-qcom-qmp.c
[..]
> +static int qcom_qmp_phy_poweron(struct phy *phy)
[..]
> +
> +err3:
Rather than naming your labels errX, it's idiomatic to give them
descriptive names, e.g. "disable_ref_clk" here.
> + clk_disable_unprepare(qphy->ref_clk);
> +err2:
> + regulator_disable(qphy->vddp_ref_clk);
> +err1:
> + regulator_disable(qphy->vdda_pll);
> +err:
> + regulator_disable(qphy->vdda_phy);
> + return ret;
> +}
[..]
> +static int qcom_qmp_phy_com_init(struct qcom_qmp_phy *qphy)
> +{
> + const struct qmp_phy_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int ret;
> +
> + mutex_lock(&qphy->phy_mutex);
> + if (qphy->init_count++) {
> + mutex_unlock(&qphy->phy_mutex);
> + return 0;
> + }
As far as I can see phy_init() and phy_exit() already keep reference
count on the initialization and you only call this function from
phy_ops->init, so you should be able to drop this.
[..]
> +
> +/* PHY Initialization */
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
[..]
> + /* phy power down delay; given in PCIE phy programming guide only */
> + if (qphy->cfg->type == PHY_TYPE_PCIE)
Rather than basing this off "is this pcie" it's preferred if you have a
bool power_down_delay; (or optionally carrying the timeout value) to
control this.
> + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX);
> +
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(pcs + QPHY_START_CTRL, cfg->start_ctrl);
> +
> + /* Pull PHY out of reset state */
> + qphy_clrbits(pcs + QPHY_SW_RESET, SW_RESET);
> +
> + status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
> + mask = cfg->mask_pcs_ready;
> +
> + ret = !mask ? 0 : readl_poll_timeout(status, val, !(val & mask), 1,
> + PHY_INIT_COMPLETE_TIMEOUT);
I presume it's not okay to read the status register even once for pcie?
If it is you can skip the conditional as !(val & 0) will break the poll
after the first read.
[..]
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
[..]
> +}
> +
> +
Extra blank line
> +static int qcom_qmp_phy_regulator_init(struct device *dev)
[..]
> +static
> +struct qmp_phy_desc *qcom_qmp_phy_create(struct platform_device *pdev, int id)
> +{
[..]
> + phy_desc->pipe_clk = devm_clk_get(dev, prop_name);
> + if (IS_ERR(phy_desc->pipe_clk)) {
> + if (qphy->cfg->type == PHY_TYPE_PCIE ||
> + qphy->cfg->type == PHY_TYPE_USB3) {
Is this check adding any value?
> + ret = PTR_ERR(phy_desc->pipe_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev,
> + "failed to get lane%d pipe_clk, %d\n",
> + id, ret);
> + return ERR_PTR(ret);
> + }
> + phy_desc->pipe_clk = NULL;
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH v3 1/5] arm64: dts: exynos5433: TM2/E: Fix wrong information of ldo23 and ldo25
From: Chanwoo Choi @ 2017-01-06 7:20 UTC (permalink / raw)
To: Krzysztof Kozlowski, Jaechul Lee
Cc: Mark Rutland, devicetree, linux-samsung-soc, Catalin Marinas,
Dmitry Torokhov, Will Deacon, linux-kernel, Rob Herring,
Javier Martinez Canillas, Kukjin Kim, Andi Shyti, linux-input,
galaxyra, beomho.seo, linux-arm-kernel
In-Reply-To: <20170106070539.wd3kfhi77pa5ekcy@kozik-lap>
On 2017년 01월 06일 16:05, Krzysztof Kozlowski wrote:
> On Fri, Jan 06, 2017 at 12:59:05PM +0900, Jaechul Lee wrote:
>> From: Chanwoo Choi <cw00.choi@samsung.com>
>>
>> This patch fixes the wrong information of ldo23 and ldo25 on both TM2 and TM2E.
>
> Please describe what is exactly wrong and how it affects the
> system/user. This is going to the fixes so it needs a good explanation.
When I posted the patch[1], I refer to the old schematic document of both TM2 and TM2E.
[1] 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
After checking the highest version of schematic document of both TM2 and TM2E,
there is no difference of ldo23/ldo25 on both TM2 and TM2E.
- ldo23 is used on TM2/TM2E, but the name/max-microvolt are wrong.
- ldo25 isn't used on TM2/TM2E. (not connected)
Because ldo23 and lod25 are not used on other device in Exynos5433 and TM2 board.
this patch does not affect the operation to system/user.
>
>>
>> Fixes: 01e5d2352152 ("arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board")
>> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
>> Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
>> Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
>> ---
>> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 7 ++++---
>> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 10 ----------
>> 2 files changed, 4 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> index 3b5215c..e8971f4 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>> @@ -504,9 +504,9 @@
>> };
>>
>> ldo23_reg: LDO23 {
>> - regulator-name = "CAM_SEN_CORE_1.2V_AP";
>> + regulator-name = "CAM_SEN_CORE_1.05V_AP";
>> regulator-min-microvolt = <1050000>;
>> - regulator-max-microvolt = <1200000>;
>> + regulator-max-microvolt = <1050000>;
>> };
>>
>> ldo24_reg: LDO24 {
>> @@ -516,9 +516,10 @@
>> };
>>
>> ldo25_reg: LDO25 {
>> - regulator-name = "CAM_SEN_A2.8V_AP";
>> + regulator-name = "UNUSED_LDO25";
>> regulator-min-microvolt = <2800000>;
>> regulator-max-microvolt = <2800000>;
>> + regulator-always-off;
>
> Don't add it. See my other patch.
OK. After completing the kernel booting, the unused regulators will be off.
>
> Best regards,
> Krzysztof
>
>> };
>>
>> ldo26_reg: LDO26 {
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> index 1db4e7f..854c583 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>> @@ -18,16 +18,6 @@
>> compatible = "samsung,tm2e", "samsung,exynos5433";
>> };
>>
>> -&ldo23_reg {
>> - regulator-name = "CAM_SEN_CORE_1.025V_AP";
>> - regulator-max-microvolt = <1050000>;
>> -};
>> -
>> -&ldo25_reg {
>> - regulator-name = "UNUSED_LDO25";
>> - regulator-always-off;
>> -};
>> -
>> &ldo31_reg {
>> regulator-name = "TSP_VDD_1.8V_AP";
>> regulator-min-microvolt = <1800000>;
>> --
>> 2.7.4
>>
>
>
>
--
Best Regards,
Chanwoo Choi
S/W Center, Samsung Electronics
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 2/2] media: rc: add driver for IR remote receiver on MT7623 SoC
From: Sean Wang @ 2017-01-06 7:31 UTC (permalink / raw)
To: Sean Young
Cc: mchehab-JPH+aEBZ4P+UEJcrhfAQsw, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
hkallweit1-Re5JQEeQqe8AvxtiuMwx3w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
andi.shyti-Sze3O3UU22JBDgjK7y7TUQ,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw,
ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170105171240.GA9136-3XSxi2G4b3iXFJAUJl40Xg@public.gmane.org>
Hi Sean,
Thanks for your effort for code reviewing. I add comments inline.
On Thu, 2017-01-05 at 17:12 +0000, Sean Young wrote:
> Hi Sean,
>
> Some review comments.
>
> On Fri, Jan 06, 2017 at 12:06:24AM +0800, sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org wrote:
> > From: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> >
> > This patch adds driver for IR controller on
> > Mediatek MT7623 SoC. Currently testing successfully
> > on NEC and SONY remote controller only but it should
> > work on others (lirc, rc-5 and rc-6).
> >
> > Signed-off-by: Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > drivers/media/rc/Kconfig | 10 ++
> > drivers/media/rc/Makefile | 1 +
> > drivers/media/rc/mtk-cir.c | 319 +++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 330 insertions(+)
> > create mode 100644 linux-4.8.rc1_p0/drivers/media/rc/mtk-cir.c
> >
> > diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
> > index 370e16e..626c500 100644
> > --- a/drivers/media/rc/Kconfig
> > +++ b/drivers/media/rc/Kconfig
> > @@ -389,4 +389,14 @@ config IR_SUNXI
> > To compile this driver as a module, choose M here: the module will
> > be called sunxi-ir.
> >
> > +config IR_MTK
> > + tristate "Mediatek IR remote control"
> > + depends on RC_CORE
> > + depends on ARCH_MEDIATEK || COMPILE_TEST
> > + ---help---
> > + Say Y if you want to use Mediatek internal IR Controller
> > +
> > + To compile this driver as a module, choose M here: the module will
> > + be called mtk-cir.
> > +
> > endif #RC_DEVICES
> > diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
> > index 379a5c0..505908d 100644
> > --- a/drivers/media/rc/Makefile
> > +++ b/drivers/media/rc/Makefile
> > @@ -37,3 +37,4 @@ obj-$(CONFIG_IR_TTUSBIR) += ttusbir.o
> > obj-$(CONFIG_RC_ST) += st_rc.o
> > obj-$(CONFIG_IR_SUNXI) += sunxi-cir.o
> > obj-$(CONFIG_IR_IMG) += img-ir/
> > +obj-$(CONFIG_IR_MTK) += mtk-cir.o
> > diff --git a/drivers/media/rc/mtk-cir.c b/drivers/media/rc/mtk-cir.c
> > new file mode 100644
> > index 0000000..4fa4cab
> > --- /dev/null
> > +++ b/drivers/media/rc/mtk-cir.c
> > @@ -0,0 +1,319 @@
> > +/*
> > + * Driver for Mediatek MT7623 IR Receiver Controller
> > + *
> > + * Copyright (C) 2017 Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/reset.h>
> > +#include <media/rc-core.h>
> > +
> > +#define MTK_IR_DEV "mtk-ir"
>
> KBUILD_MODNAME could be used instead. Currently the module is called
> mtk-cir but the rc device will have driver name mtk-ir.
okay. i will use this instead of this insistent coding.
> > +
> > +/* Register to enable PWM and IR */
> > +#define MTK_CONFIG_HIGH_REG 0x0c
> > +/* Enable IR pulse width detection */
> > +#define MTK_PWM_EN BIT(13)
> > +/* Enable IR hardware function */
> > +#define MTK_IR_EN BIT(0)
> > +
> > +/* Register to setting sample period */
> > +#define MTK_CONFIG_LOW_REG 0x10
> > +/* Field to set sample period */
> > +#define CHK_PERIOD 0xC00
> > +#define MTK_CHK_PERIOD (((CHK_PERIOD) << 8) & (GENMASK(20, 8)))
> > +#define MTK_CHK_PERIOD_MASK (GENMASK(20, 8))
> > +
> > +/* Register to clear state of state machine */
> > +#define MTK_IRCLR_REG 0x20
> > +/* Bit to restart IR receiving */
> > +#define MTK_IRCLR BIT(0)
> > +
> > +/* Register containing pulse width data */
> > +#define MTK_CHKDATA_REG(i) (0x88 + 4 * i)
> > +
> > +/* Register to enable IR interrupt */
> > +#define MTK_IRINT_EN_REG 0xcc
> > +/* Bit to enable interrupt */
> > +#define MTK_IRINT_EN BIT(0)
> > +
> > +/* Register to ack IR interrupt */
> > +#define MTK_IRINT_CLR_REG 0xd0
> > +/* Bit to clear interrupt status */
> > +#define MTK_IRINT_CLR BIT(0)
> > +
> > +/* Number of registers to record the pulse width */
> > +#define MTK_CHKDATA_SZ 17
> > +/* Required frequency */
> > +#define MTK_IR_BASE_CLK 273000000
> > +/* Frequency after IR internal divider */
> > +#define MTK_IR_CLK (MTK_IR_BASE_CLK / 4)
> > +/* Sample period in ns */
> > +#define MTK_IR_SAMPLE (((1000000000ul / MTK_IR_CLK) * CHK_PERIOD))
> > +/* Indicate the end of IR data*/
> > +#define MTK_IR_END(v) (v == 0xff)
> > +
> > +/* struct mtk_ir - This is the main datasructure for holding the state
> > + * of the driver
> > + * @dev: The device pointer
> > + * @ir_lock: Make sure that synchronization between remove and ISR
> > + * @rc: The rc instrance
> > + * @base: The mapped register i/o base
> > + * @irq: The IRQ that we are using
> > + * @clk: The clock that we are using
> > + * @map_name: The name for keymap lookup
> > + */
> > +struct mtk_ir {
> > + struct device *dev;
> > + /*Protect concurrency between driver removal and ISR*/
> > + spinlock_t ir_lock;
> > + struct rc_dev *rc;
> > + void __iomem *base;
> > + int irq;
> > + struct clk *clk;
> > + const char *map_name;
>
> irq and map_name don't need to be stored here, they're only used in
> mtk_ir_probe.
>
I will remove map_name , but keep irq for synchronize_irq call needs.
> > +};
> > +
> > +static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
> > +{
> > + u32 tmp;
> > +
> > + tmp = __raw_readl(ir->base + reg);
> > + tmp = (tmp & ~mask) | val;
> > + __raw_writel(tmp, ir->base + reg);
> > +}
> > +
> > +static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
> > +{
> > + __raw_writel(val, ir->base + reg);
> > +}
> > +
> > +static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
> > +{
> > + return __raw_readl(ir->base + reg);
> > +}
> > +
> > +static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
> > +{
> > + u32 val;
> > +
> > + val = mtk_r32(ir, MTK_IRINT_EN_REG);
> > + mtk_w32(ir, val & ~mask, MTK_IRINT_EN_REG);
> > +}
> > +
> > +static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
> > +{
> > + u32 val;
> > +
> > + val = mtk_r32(ir, MTK_IRINT_EN_REG);
> > + mtk_w32(ir, val | mask, MTK_IRINT_EN_REG);
> > +}
> > +
> > +static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
> > +{
> > + struct mtk_ir *ir = dev_id;
> > + u8 wid = 0;
> > + u32 i, j, val;
> > + DEFINE_IR_RAW_EVENT(rawir);
> > +
> > + spin_lock(&ir->ir_lock);
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + /* Reset decoder state machine */
> > + ir_raw_event_reset(ir->rc);
> > +
> > + /* First message must be pulse */
> > + rawir.pulse = false;
> > +
> > + /* Handle pulse and space until end of message */
> > + for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
> > + val = mtk_r32(ir, MTK_CHKDATA_REG(i));
> > + dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
> > +
> > + for (j = 0 ; j < 4 ; j++) {
> > + wid = (val & (0xff << j * 8)) >> j * 8;
> > + rawir.pulse = !rawir.pulse;
> > + rawir.duration = wid * (MTK_IR_SAMPLE + 1);
> > + ir_raw_event_store_with_filter(ir->rc, &rawir);
> > +
> > + if (MTK_IR_END(wid))
> > + goto end_msg;
> > + }
> > + }
>
> If I read this correctly, there is a maximum of 17 * 4 = 68 edges per
> IR message. The rc6 mce key 0 (scancode 0x800f0400) is 69 edges, so that
> won't work.
>
Uh, this is related to hardware limitation. Maximum number hardware
holds indeed is only 68 edges as you said :(
For the case, I will try change the logic into that the whole message
is dropped if no end of message is seen within 68 counts to avoid
wasting CPU for decoding.
> > +end_msg:
> > + /* Restart the next receive */
> > + mtk_w32_mask(ir, 0x1, MTK_IRCLR, MTK_IRCLR_REG);
> > +
> > + ir_raw_event_set_idle(ir->rc, true);
> > + ir_raw_event_handle(ir->rc);
> > +
> > + /* Clear interrupt status */
> > + mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR, MTK_IRINT_CLR_REG);
> > +
> > + /* Enable interrupt */
> > + mtk_irq_enable(ir, MTK_IRINT_EN);
> > +
> > + spin_unlock(&ir->ir_lock);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int mtk_ir_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *dn = dev->of_node;
> > + struct resource *res;
> > + struct mtk_ir *ir;
> > + u32 val;
> > + int ret = 0;
> > +
> > + ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
> > + if (!ir)
> > + return -ENOMEM;
> > +
> > + spin_lock_init(&ir->ir_lock);
> > +
> > + ir->dev = dev;
> > +
> > + if (!of_device_is_compatible(dn, "mediatek,mt7623-ir"))
> > + return -ENODEV;
> > +
> > + ir->clk = devm_clk_get(dev, "clk");
> > + if (IS_ERR(ir->clk)) {
> > + dev_err(dev, "failed to get a ir clock.\n");
> > + return PTR_ERR(ir->clk);
> > + }
> > +
> > + if (clk_prepare_enable(ir->clk)) {
> > + dev_err(dev, "try to enable ir_clk failed\n");
> > + ret = -EINVAL;
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + ir->base = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(ir->base)) {
> > + dev_err(dev, "failed to map registers\n");
> > + ret = PTR_ERR(ir->base);
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + ir->rc = rc_allocate_device();
> > + if (!ir->rc) {
> > + dev_err(dev, "failed to allocate device\n");
> > + ret = -ENOMEM;
> > + goto exit_clkdisable_clk;
> > + }
> > +
> > + ir->rc->priv = ir;
> > + ir->rc->input_name = MTK_IR_DEV;
> > + ir->rc->input_phys = "mtk-ir/input0";
> > + ir->rc->input_id.bustype = BUS_HOST;
> > + ir->rc->input_id.vendor = 0x0001;
> > + ir->rc->input_id.product = 0x0001;
> > + ir->rc->input_id.version = 0x0001;
> > + ir->map_name = of_get_property(dn, "linux,rc-map-name", NULL);
> > + ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
> > + ir->rc->dev.parent = dev;
> > + ir->rc->driver_type = RC_DRIVER_IR_RAW;
> > + ir->rc->driver_name = MTK_IR_DEV;
> > + ir->rc->allowed_protocols = RC_BIT_ALL;
> > + ir->rc->rx_resolution = MTK_IR_SAMPLE;
> > +
> > + ret = rc_register_device(ir->rc);
> > + if (ret) {
> > + dev_err(dev, "failed to register rc device\n");
> > + goto exit_free_dev;
> > + }
> > +
> > + platform_set_drvdata(pdev, ir);
> > +
> > + ir->irq = platform_get_irq(pdev, 0);
> > + if (ir->irq < 0) {
> > + dev_err(dev, "no irq resource\n");
> > + ret = ir->irq;
>
> From here on onwards the errors paths should call rc_unregister_device(),
> and no longer call rc_free_device(). Note that current master has
> devm_rc_allocate_device() and devm_rc_register_device() which would
> simplify this code.
okay, i will use devm_rc_register_device to have simplified code.
> > + goto exit_free_dev;
> > + }
> > +
> > + ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
> > + if (ret) {
> > + dev_err(dev, "failed request irq\n");
> > + goto exit_free_dev;
> > + }
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + val = mtk_r32(ir, MTK_CONFIG_HIGH_REG);
> > + val |= MTK_PWM_EN | MTK_IR_EN;
> > + mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
> > +
> > + /* Setting sample period */
> > + mtk_w32_mask(ir, MTK_CHK_PERIOD, MTK_CHK_PERIOD_MASK,
> > + MTK_CONFIG_LOW_REG);
> > +
> > + mtk_irq_enable(ir, MTK_IRINT_EN);
> > +
> > + dev_info(dev, "initialized MT7623 IR driver\n");
> > + return 0;
> > +
> > +exit_free_dev:
> > + rc_free_device(ir->rc);
> > +exit_clkdisable_clk:
> > + clk_disable_unprepare(ir->clk);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ir_remove(struct platform_device *pdev)
> > +{
> > + unsigned long flags;
> > +
> > + struct mtk_ir *ir = platform_get_drvdata(pdev);
> > +
> > + spin_lock_irqsave(&ir->ir_lock, flags);
> > +
> > + mtk_irq_disable(ir, MTK_IRINT_EN);
> > +
> > + clk_disable_unprepare(ir->clk);
> > +
> > + spin_unlock_irqrestore(&ir->ir_lock, flags);
>
> I'm not convinced the ir_lock is helping to prevent any race condition. An
> irq might still already have occurred which will now try to use ir->rc
> which is freed. You can remove the spinlock completely and call
> sychronize_irq() after disabling the mtk interrupt. That way you're sure
> the remove is safe to complete.
Okay, it's great suggestion. I will use sychronize_irq instead of the my
bad one :)
> > +
> > + rc_unregister_device(ir->rc);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_ir_match[] = {
> > + { .compatible = "mediatek,mt7623-ir" },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_ir_match);
> > +
> > +static struct platform_driver mtk_ir_driver = {
> > + .probe = mtk_ir_probe,
> > + .remove = mtk_ir_remove,
> > + .driver = {
> > + .name = MTK_IR_DEV,
> > + .of_match_table = mtk_ir_match,
> > + },
> > +};
> > +
> > +module_platform_driver(mtk_ir_driver);
> > +
> > +MODULE_DESCRIPTION("Mediatek MT7623 IR Receiver Controller Driver");
> > +MODULE_AUTHOR("Sean Wang <sean.wang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>");
> > +MODULE_LICENSE("GPL");
> > --
> > 1.9.1
> >
--
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^ permalink raw reply
* Re: [PATCH 10/12] ARM: dts: socfpga: add base fpga region and fpga bridges
From: Dinh Nguyen @ 2017-01-06 7:39 UTC (permalink / raw)
To: Alan Tull
Cc: Alan Tull, devicetree@vger.kernel.org, Dinh Nguyen,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CANk1AXRsrW1YHRPn4Rcv7Pu8jBUEcOmREOFYvvMV8D9eKLU-6g@mail.gmail.com>
On 01/05/2017 10:34 AM, Alan Tull wrote:
> On Thu, Jan 5, 2017 at 10:28 AM, Alan Tull <atull@kernel.org> wrote:
>> On Wed, Jan 4, 2017 at 6:21 PM, Dinh Nguyen <dinguyen@kernel.org> wrote:
>>> From: Alan Tull <atull@opensource.altera.com>
>>>
>>> Add h2f and lwh2f bridges.
>>> Add base FPGA Region to support DT overlays for FPGA programming.
>>> Add l3regs.
>>>
>>> Signed-off-by: Alan Tull <atull@opensource.altera.com>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> arch/arm/boot/dts/socfpga.dtsi | 31 +++++++++++++++++++++++++++++++
>>> 1 file changed, 31 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index de29172..dccc281 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>> @@ -93,6 +93,16 @@
>>> };
>>> };
>>>
>>> + base_fpga_region {
>>> + compatible = "fpga-region";
>>> + fpga-mgr = <&fpgamgr0>;
>>> + fpga-bridges = <&fpga_bridge0>, <&fpga_bridge1>;
>>
>> Hi Dinh,
>>
>> We want to get rid of the 'fpga-bridges' line.
>>
>>> +
>>> + #address-cells = <0x1>;
>>> + #size-cells = <0x1>;
>>> + ranges = <0 0xff200000 0x100000>;
>>
>> Should get rid of the ranges line here too. The 'fpga-bridges' and
>> 'ranges' line can be added in the overlay.
>>
>> Alan
>>
>>> + };
>>> +
>>> can0: can@ffc00000 {
>>> compatible = "bosch,d_can";
>>> reg = <0xffc00000 0x1000>;
>>> @@ -513,6 +523,22 @@
>>> };
>>> };
>>>
>>> + fpga_bridge0: fpga_bridge@ff400000 {
>>> + compatible = "altr,socfpga-lwhps2fpga-bridge";
>>> + reg = <0xff400000 0x100000>;
>>> + resets = <&rst LWHPS2FPGA_RESET>;
>>> + reset-names = "lwhps2fpga";
>
> The driver doesn't need 'reset-names' here or below for fpga_bridge1.
>
Ok, thanks for the review.
Dinh
^ permalink raw reply
* Re: [PATCH 2/2] media: rc: add driver for IR remote receiver on MT7623 SoC
From: Sean Wang @ 2017-01-06 7:41 UTC (permalink / raw)
To: Andi Shyti
Cc: mchehab-JPH+aEBZ4P+UEJcrhfAQsw, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
hkallweit1-Re5JQEeQqe8AvxtiuMwx3w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w,
hverkuil-qWit8jRvyhVmR6Xm/wNWPw, sean-hENCXIMQXOg,
ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
keyhaede-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20170106034346.7njhyhtsc4yado5c-8vUhnHFVuGn35fTxX1Dczw@public.gmane.org>
Hi Andi,
Thank for your reminder. I will refine the code based on your work.
to have elegant code and easy error handling.
Sean
On Fri, 2017-01-06 at 12:43 +0900, Andi Shyti wrote:
> Hi Sean,
>
> > + ir->rc = rc_allocate_device();
>
> Yes, you should use devm_rc_allocate_device(...)
>
> Besides, standing to this patch which is not in yet:
>
> https://lkml.org/lkml/2016/12/18/39
>
> rc_allocate_device should provide the driver type during
> allocation, so it should be:
>
> ir->rc = rc_allocate_device(RC_DRIVER_IR_RAW);
>
> and this line can be removed:
>
> > + ir->rc->driver_type = RC_DRIVER_IR_RAW;
>
> I don't know when Mauro will take the patch above.
>
> Andi
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^ permalink raw reply
* [PATCHv2] ARM: dts: socfpga: add base fpga region and fpga bridges
From: Dinh Nguyen @ 2017-01-06 7:48 UTC (permalink / raw)
To: devicetree; +Cc: Alan Tull, Dinh Nguyen, dinguyen, linux-arm-kernel, atull
From: Alan Tull <atull@opensource.altera.com>
Add h2f and lwh2f bridges.
Add base FPGA Region to support DT overlays for FPGA programming.
Add l3regs.
Signed-off-by: Alan Tull <atull@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: removed fpga-bridges, ranges, and reset-names
---
arch/arm/boot/dts/socfpga.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index de29172..c984f53 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -93,6 +93,14 @@
};
};
+ base_fpga_region {
+ compatible = "fpga-region";
+ fpga-mgr = <&fpgamgr0>;
+
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ };
+
can0: can@ffc00000 {
compatible = "bosch,d_can";
reg = <0xffc00000 0x1000>;
@@ -513,6 +521,20 @@
};
};
+ fpga_bridge0: fpga_bridge@ff400000 {
+ compatible = "altr,socfpga-lwhps2fpga-bridge";
+ reg = <0xff400000 0x100000>;
+ resets = <&rst LWHPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
+ fpga_bridge1: fpga_bridge@ff500000 {
+ compatible = "altr,socfpga-hps2fpga-bridge";
+ reg = <0xff500000 0x10000>;
+ resets = <&rst HPS2FPGA_RESET>;
+ clocks = <&l4_main_clk>;
+ };
+
fpgamgr0: fpgamgr@ff706000 {
compatible = "altr,socfpga-fpga-mgr";
reg = <0xff706000 0x1000
@@ -694,6 +716,11 @@
arm,prefetch-offset = <7>;
};
+ l3regs@0xff800000 {
+ compatible = "altr,l3regs", "syscon";
+ reg = <0xff800000 0x1000>;
+ };
+
mmc: dwmmc0@ff704000 {
compatible = "altr,socfpga-dw-mshc";
reg = <0xff704000 0x1000>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v7 0/8] Add PWM and IIO timer drivers for STM32
From: Benjamin Gaignard @ 2017-01-06 7:58 UTC (permalink / raw)
To: Lee Jones
Cc: robh+dt, Mark Rutland, Alexandre Torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, Linux PWM List,
Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, linux-iio, linux-arm-kernel,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <20170105144953.GT24225@dell>
2017-01-05 15:49 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Thu, 05 Jan 2017, Benjamin Gaignard wrote:
>
>> version 7:
>> - rebase on v4.10-rc2
>> - remove iio_device code from driver and keep only the trigger part
>>
>> version 6:
>> - rename stm32-gptimer in stm32-timers.
>> - change "st,stm32-gptimer" compatible to "st,stm32-timers".
>> - modify "st,breakinput" parameter in pwm part.
>> - split DT patch in 2
>>
>> version 5:
>> - fix comments done on version 4
>> - rebased on kernel 4.9-rc8
>> - change nodes names and re-order then by addresses
>>
>> version 4:
>> - fix comments done on version 3
>> - don't use interrupts anymore in IIO timer
>> - detect hardware capabilities at probe time to simplify binding
>>
>> version 3:
>> - no change on mfd and pwm divers patches
>> - add cross reference between bindings
>> - change compatible to "st,stm32-timer-trigger"
>> - fix attributes access rights
>> - use string instead of int for master_mode and slave_mode
>> - document device attributes in sysfs-bus-iio-timer-stm32
>> - update DT with the new compatible
>>
>> version 2:
>> - keep only one compatible per driver
>> - use DT parameters to describe hardware block configuration:
>> - pwm channels, complementary output, counter size, break input
>> - triggers accepted and create by IIO timers
>> - change DT to limite use of reference to the node
>> - interrupt is now in IIO timer driver
>> - rename stm32-mfd-timer to stm32-timers (for general purpose timer)
>>
>> The following patches enable PWM and IIO Timer features for STM32 platforms.
>>
>> Those two features are mixed into the registers of the same hardware block
>> (named general purpose timer) which lead to introduce a multifunctions driver
>> on the top of them to be able to share the registers.
>>
>> In STM32f4 14 instances of timer hardware block exist, even if they all have
>> the same register mapping they could have a different number of pwm channels
>> and/or different triggers capabilities. We use various parameters in DT to
>> describe the differences between hardware blocks
>>
>> The MFD (stm32-timers.c) takes care of clock and register mapping
>> by using regmap. stm32_timers structure is provided to its sub-node to
>> share those information.
>>
>> PWM driver is implemented into pwm-stm32.c. Depending of the instance we may
>> have up to 4 channels, sometime with complementary outputs or 32 bits counter
>> instead of 16 bits. Some hardware blocks may also have a break input function
>> which allows to stop pwm depending of a level, defined in devicetree, on an
>> external pin.
>>
>> IIO timer driver (stm32-timer-trigger.c and stm32-timer-trigger.h) define a list
>> of hardware triggers usable by hardware blocks like ADC, DAC or other timers.
>>
>> The matrix of possible connections between blocks is quite complex so we use
>> trigger names and is_stm32_iio_timer_trigger() function to be sure that
>> triggers are valid and configure the IPs.
>>
>> At run time IIO timer hardware blocks can configure (through "master_mode"
>> IIO device attribute) which internal signal (counter enable, reset,
>> comparison block, etc...) is used to generate the trigger.
>>
>> Benjamin Gaignard (8):
>> MFD: add bindings for STM32 Timers driver
>> MFD: add STM32 Timers driver
>> PWM: add pwm-stm32 DT bindings
>> PWM: add PWM driver for STM32 plaftorm
>> IIO: add bindings for STM32 timer trigger driver
>> IIO: add STM32 timer trigger driver
>> ARM: dts: stm32: add Timers driver for stm32f429 MCU
>> ARM: dts: stm32: Enable pwm1 and pwm3 for stm32f469-disco
>
> Any reason why you've dropped all your Acks?
>
> I don't really want to review it again if little is different.
>
> How much MFD related code has changed since the last review?
All my apologies I forgot to add your Acks for MFD parts.
Sorry for that
>
>> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 29 ++
>> .../bindings/iio/timer/stm32-timer-trigger.txt | 23 ++
>> .../devicetree/bindings/mfd/stm32-timers.txt | 46 +++
>> .../devicetree/bindings/pwm/pwm-stm32.txt | 33 ++
>> arch/arm/boot/dts/stm32f429.dtsi | 275 +++++++++++++
>> arch/arm/boot/dts/stm32f469-disco.dts | 28 ++
>> drivers/iio/Kconfig | 1 -
>> drivers/iio/trigger/Kconfig | 10 +
>> drivers/iio/trigger/Makefile | 1 +
>> drivers/iio/trigger/stm32-timer-trigger.c | 340 ++++++++++++++++
>> drivers/mfd/Kconfig | 11 +
>> drivers/mfd/Makefile | 2 +
>> drivers/mfd/stm32-timers.c | 80 ++++
>> drivers/pwm/Kconfig | 9 +
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-stm32.c | 434 +++++++++++++++++++++
>> include/linux/iio/timer/stm32-timer-trigger.h | 62 +++
>> include/linux/mfd/stm32-timers.h | 71 ++++
>> 18 files changed, 1455 insertions(+), 1 deletion(-)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timers.txt
>> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>> create mode 100644 drivers/iio/trigger/stm32-timer-trigger.c
>> create mode 100644 drivers/mfd/stm32-timers.c
>> create mode 100644 drivers/pwm/pwm-stm32.c
>> create mode 100644 include/linux/iio/timer/stm32-timer-trigger.h
>> create mode 100644 include/linux/mfd/stm32-timers.h
>>
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
Graphic Study Group
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v3 2/5] arm64: dts: exynos: make tm2 and tm2e independent from each other
From: Andi Shyti @ 2017-01-06 7:59 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Jaechul Lee, Dmitry Torokhov, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, Kukjin Kim,
Javier Martinez Canillas, Chanwoo Choi, beomho.seo, galaxyra,
linux-arm-kernel, linux-input, devicetree, linux-kernel,
linux-samsung-soc
In-Reply-To: <20170106070911.sj6qjd5akyxnazsl@kozik-lap>
Hi,
On Fri, Jan 06, 2017 at 09:09:11AM +0200, Krzysztof Kozlowski wrote:
> On Fri, Jan 06, 2017 at 12:59:06PM +0900, Jaechul Lee wrote:
> > From: Andi Shyti <andi.shyti@samsung.com>
> >
> > Currently tm2e dts includes tm2 but there are some differences
> > between the two boards and tm2 has some properties that tm2e
> > doesn't have.
> >
> > That's why it's important to keep the two dts files independent
> > and put all the commonalities in a tm2-common.dtsi file.
> >
> > At the current status the only two differences between the two
> > dts files (besides the board name) are ldo31 and ldo38.
> >
> > Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
> > Signed-off-by: Jaechul Lee <jcsing.lee@samsung.com>
> > ---
> > .../boot/dts/exynos/exynos5433-tm2-common.dtsi | 1118 +++++++++++++++++++
> > arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 1153 +-------------------
>
> Like talking to a wall. Without any feedback. If my instructions were
> wrong (and it is not possible to detect rename) then please say it (you
> can add personal comments after separator ---).
no Krzysztof, I'm sorry, but this patch has been formatted with
the diff algorithm *you* asked, -B50% both version 2 (where you
didn't comment) and version 3. If you still don't like it, please
don't blame me, blame the algorithm.
Now we can stay here at trying random diff algorithms (as they
give more or less the same result) or you tell me which exact
algorithm you want me to use. Besides, for me it's clear,
tm2-common is all new, while in tm2 you have on one side the '-'
(if it applies nothing has changed) on the bottom the '+'.
Andi
^ permalink raw reply
* Re: [PATCH] ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
From: Neil Armstrong @ 2017-01-06 8:04 UTC (permalink / raw)
To: Michał Zegan, khilman-rdvid1DuHRBWk0Htik3J/w,
carlo-KA+7E9HrN00dnm+yROfE0A
Cc: linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <9f508097-f605-ebd8-20af-c3e798c6fdcc-wo4oW1Pw1HF3vZ0LZ0W7Rg@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 2653 bytes --]
On 01/05/2017 08:04 PM, Michał Zegan wrote:
> Hello.
>
> The patch causes cpufreq module (scpi-cpufreq) not to detect cpufreq, so
> it actually works, but...
> Loading the module causes few errors because of not found frequencies or
> something, then it is all okay. However after loading scpi-cpufreq you
> cannot actually power the cpu off and on. You will power it off
> successfully, but when trying to power it on, the cpufreq driver will
> error out, and then after it happens, the cpu that was trying to go
> online will be offline again, and that is a little... unfortunate. The
> question is, and I cannot really test that: will the module actually
> autoload after this change?
Hi Michal,
You are right, it breaks cpufreq and the cpu hotplug feature, I will send a v2 completely disabling cpufreq instead.
For the module autoloading, the arm_scpi.ko must be loaded before the other scpi modules.
Please ask Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> if module autoloading for scpi is meant to work.
Neil
>
> W dniu 05.01.2017 o 16:02, Neil Armstrong pisze:
>> The current hardware is not able to run with all cores enabled at a
>> cluster frequency superior at 1536MHz.
>> But the currently shipped u-boot for the platform still reports an OPP
>> table with possible DVFS frequency up to 2GHz, and will not change since
>> the off-tree linux tree supports limiting the OPPs with a kernel parameter.
>> A recent u-boot change reports the boot-time DVFS around 100MHz and
>> the default performance cpufreq governor sets the maximum frequency.
>> Previous version of u-boot reported to be already at the max OPP and
>> left the OPP as is.
>> Nevertheless, other governors like ondemand could setup the max frequency
>> and make the system crash.
>>
>> This patch disables the DVFS clock and disables cpufreq.
>>
>> Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
>> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> index 238fbea..5e63e3b 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
>> @@ -137,6 +137,10 @@
>> };
>> };
>>
>> +&scpi_dvfs {
>> + status = "disabled";
>> +};
>> +
>> &uart_AO {
>> status = "okay";
>> pinctrl-0 = <&uart_ao_a_pins>;
>>
>
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply
* [PATCH v2] ARM64: dts: meson-gxbb-odroidc2: Disable SCPI DVFS
From: Neil Armstrong @ 2017-01-06 8:04 UTC (permalink / raw)
To: khilman-rdvid1DuHRBWk0Htik3J/w, carlo-KA+7E9HrN00dnm+yROfE0A
Cc: Neil Armstrong, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
The current hardware is not able to run with all cores enabled at a
cluster frequency superior at 1536MHz.
But the currently shipped u-boot for the platform still reports an OPP
table with possible DVFS frequency up to 2GHz, and will not change since
the off-tree linux tree supports limiting the OPPs with a kernel parameter.
A recent u-boot change reports the boot-time DVFS around 100MHz and
the default performance cpufreq governor sets the maximum frequency.
Previous version of u-boot reported to be already at the max OPP and
left the OPP as is.
Nevertheless, other governors like ondemand could setup the max frequency
and make the system crash.
This patch disables the DVFS clock and disables cpufreq.
Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes")
Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 4 ++++
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
Changes since v1 at [1] :
- Disable scpi_clocks instead of scpi_dvfs_clock
[1] http://lkml.kernel.org/r/1483628549-29486-1-git-send-email-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 238fbea..5d28e1c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -137,6 +137,10 @@
};
};
+&scpi_clocks {
+ status = "disabled";
+};
+
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 51edd5b5..77caedd8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -55,7 +55,7 @@
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
- clocks {
+ scpi_clocks: clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH v7 3/4] drm/panel: Add support for S6E3HA2 panel driver on TM2 board
From: Andi Shyti @ 2017-01-06 8:18 UTC (permalink / raw)
To: Inki Dae
Cc: Hoegeun Kwon, robh-DgEjT+Ai2ygdnm+yROfE0A,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w, airlied-cv59FeDIM0c,
kgene-DgEjT+Ai2ygdnm+yROfE0A, krzk-DgEjT+Ai2ygdnm+yROfE0A,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
a.hajda-Sze3O3UU22JBDgjK7y7TUQ, cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ, Donghwa Lee, Hyungwon Hwang
In-Reply-To: <586F2BF3.8080400-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi Inki,
Thanks for the reply, but...
> >> +static const struct drm_display_mode default_mode = {
> >> + .clock = 222372,
> >> + .hdisplay = 1440,
> >> + .hsync_start = 1440 + 1,
> >> + .hsync_end = 1440 + 1 + 1,
> >> + .htotal = 1440 + 1 + 1 + 1,
> >> + .vdisplay = 2560,
> >> + .vsync_start = 2560 + 1,
> >> + .vsync_end = 2560 + 1 + 1,
> >> + .vtotal = 2560 + 1 + 1 + 15,
> >> + .vrefresh = 60,
> >> + .flags = 0,
> >> +};
> >
> > how is this working with tm2e? Are these values valid for both
> > the boards?
>
> We don't need to consider tm2e board with two reasones,
> 1. there is no tm2e board support in mainline
> 2. the panel on tm2 would be a little bit different from one on tm2e
... this display in the Tizen Kernel is supported by both:
tm2 [1] and tm2e [2]. The only differences are:
TM2:
clock-frequency = <14874444>;
hactive = <1440>;
TM2E:
clock-frequency = <16523724>;
hactive = <1600>;
I don't know much about the differences you mention in point 2,
but it's a pity to drop support only because we don't want to put
in the dts the 'hactive', and 'clock-frequency' properties.
Andi
[1] https://git.tizen.org/cgit/platform/kernel/linux-exynos/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts?h=tizen#n1284
[2] https://git.tizen.org/cgit/platform/kernel/linux-exynos/tree/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts?h=tizen#n1270
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^ permalink raw reply
* Re: [PATCH v6 5/5] soc: zte: pm_domains: Add support for zx296718
From: Baoyou Xie @ 2017-01-06 8:23 UTC (permalink / raw)
To: Shawn Guo
Cc: Jun Nie, Rob Herring, mark.rutland, krzk, Arnd Bergmann,
Ulf Hansson, amit daniel, claudiu.manoil, yangbo.lu, pankaj.dubey,
geert+renesas, laurent.pinchart, linux-arm-kernel, devicetree,
Linux Kernel Mailing List, xie.baoyou, chen.chaokai, wang.qiang01
In-Reply-To: <20170105073846.GD4667@x250>
[-- Attachment #1: Type: text/plain, Size: 7727 bytes --]
On 5 January 2017 at 15:38, Shawn Guo <shawnguo@kernel.org> wrote:
> On Wed, Jan 04, 2017 at 07:48:14PM +0800, Baoyou Xie wrote:
> > This patch introduces the power domain driver of zx296718
> > which belongs to zte's zx2967 family.
> >
> > Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> > Reviewed-by: Jun Nie <jun.nie@linaro.org>
> > ---
> > drivers/soc/zte/Makefile | 1 +
> > drivers/soc/zte/zx296718_pm_domains.c | 181
> ++++++++++++++++++++++++++++++++++
> > 2 files changed, 182 insertions(+)
> > create mode 100644 drivers/soc/zte/zx296718_pm_domains.c
> >
> > diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile
> > index 8a37f2f..96b7cd4 100644
> > --- a/drivers/soc/zte/Makefile
> > +++ b/drivers/soc/zte/Makefile
> > @@ -2,3 +2,4 @@
> > # ZTE SOC drivers
> > #
> > obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx2967_pm_domains.o
> > +obj-$(CONFIG_ZX2967_PM_DOMAINS) += zx296718_pm_domains.o
> > diff --git a/drivers/soc/zte/zx296718_pm_domains.c
> b/drivers/soc/zte/zx296718_pm_domains.c
> > new file mode 100644
> > index 0000000..52003ee
> > --- /dev/null
> > +++ b/drivers/soc/zte/zx296718_pm_domains.c
> > @@ -0,0 +1,181 @@
> > +/*
> > + * Copyright (C) 2017 ZTE Ltd.
> > + *
> > + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> > + * License terms: GNU General Public License (GPL) version 2
> > + */
>
> Please have a newline between licence declaration and headers to improve
> the readability. Same for zx2967_pm_domains.c.
>
> > +#include <dt-bindings/soc/zte,pm_domains.h>
> > +#include "zx2967_pm_domains.h"
> > +
> > +static u16 zx296718_offsets[REG_ARRAY_SIZE] = {
> > + [REG_CLKEN] = 0x18,
> > + [REG_ISOEN] = 0x1c,
> > + [REG_RSTEN] = 0x20,
> > + [REG_PWREN] = 0x24,
> > + [REG_ACK_SYNC] = 0x28,
> > +};
> > +
> > +enum {
> > + PCU_DM_VOU = 0,
> > + PCU_DM_SAPPU,
> > + PCU_DM_VDE,
> > + PCU_DM_VCE,
> > + PCU_DM_HDE,
> > + PCU_DM_VIU,
> > + PCU_DM_USB20,
> > + PCU_DM_USB21,
> > + PCU_DM_USB30,
> > + PCU_DM_HSIC,
> > + PCU_DM_GMAC,
> > + PCU_DM_TS,
> > +};
>
> I think we can save this enum completely by defining those
> DM_ZX296718_xxx constants in zte,pm_domains.h in the same order of this
> enum (hardware bit position order), so that DM_ZX296718_xxx can directly
> be used as .bit field of struct zx2967_pm_domain.
>
> we should not replace PCU_DM_XX with DM_ZX296718_xxx, their means are
different,
one is the array index, but another is the bit index.
I suggest to keep them strongly.
> #define DM_ZX296718_VOU 0
> #define DM_ZX296718_SAPPU 1
> #define DM_ZX296718_VDE 2 /* g1v6 */
> #define DM_ZX296718_VCE 3 /* h1v6 */
> #define DM_ZX296718_HDE 4 /* g2v2 */
> #define DM_ZX296718_VIU 5
> #define DM_ZX296718_USB20 6
> #define DM_ZX296718_USB21 7
> #define DM_ZX296718_USB30 8
> #define DM_ZX296718_HSIC 9
> #define DM_ZX296718_GMAC 10
> #define DM_ZX296718_TS 11
>
> > +
> > +static struct zx2967_pm_domain vou_domain = {
> > + .dm = {
> > + .name = "vou_domain",
> > + },
> > + .bit = PCU_DM_VOU,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain sappu_domain = {
> > + .dm = {
> > + .name = "sappu_domain",
> > + },
> > + .bit = PCU_DM_SAPPU,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain vde_domain = {
> > + .dm = {
> > + .name = "vde_domain",
> > + },
> > + .bit = PCU_DM_VDE,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain vce_domain = {
> > + .dm = {
> > + .name = "vce_domain",
> > + },
> > + .bit = PCU_DM_VCE,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain hde_domain = {
> > + .dm = {
> > + .name = "hde_domain",
> > + },
> > + .bit = PCU_DM_HDE,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain viu_domain = {
> > + .dm = {
> > + .name = "viu_domain",
> > + },
> > + .bit = PCU_DM_VIU,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain usb20_domain = {
> > + .dm = {
> > + .name = "usb20_domain",
> > + },
> > + .bit = PCU_DM_USB20,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain usb21_domain = {
> > + .dm = {
> > + .name = "usb21_domain",
> > + },
> > + .bit = PCU_DM_USB21,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain usb30_domain = {
> > + .dm = {
> > + .name = "usb30_domain",
> > + },
> > + .bit = PCU_DM_USB30,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain hsic_domain = {
> > + .dm = {
> > + .name = "hsic_domain",
> > + },
> > + .bit = PCU_DM_HSIC,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain gmac_domain = {
> > + .dm = {
> > + .name = "gmac_domain",
> > + },
> > + .bit = PCU_DM_GMAC,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct zx2967_pm_domain ts_domain = {
> > + .dm = {
> > + .name = "ts_domain",
> > + },
> > + .bit = PCU_DM_TS,
> > + .polarity = PWREN,
> > + .reg_offset = zx296718_offsets,
> > +};
> > +
> > +static struct generic_pm_domain *zx296718_pm_domains[] = {
> > + [DM_ZX296718_SAPPU] = &sappu_domain.dm,
> > + [DM_ZX296718_VDE] = &vde_domain.dm,
> > + [DM_ZX296718_VCE] = &vce_domain.dm,
> > + [DM_ZX296718_HDE] = &hde_domain.dm,
> > + [DM_ZX296718_VIU] = &viu_domain.dm,
> > + [DM_ZX296718_USB20] = &usb20_domain.dm,
> > + [DM_ZX296718_USB21] = &usb21_domain.dm,
> > + [DM_ZX296718_USB30] = &usb30_domain.dm,
> > + [DM_ZX296718_HSIC] = &hsic_domain.dm,
> > + [DM_ZX296718_GMAC] = &gmac_domain.dm,
> > + [DM_ZX296718_TS] = &ts_domain.dm,
> > + [DM_ZX296718_VOU] = &vou_domain.dm,
>
> If you update the order of DM_ZX296718_xxx in zte,pm_domains.h, it would
> be nice to update this list accordingly as well.
>
> > +};
> > +
> > +static int zx296718_pd_probe(struct platform_device *pdev)
> > +{
> > + return zx2967_pd_probe(pdev,
> > + zx296718_pm_domains,
> > + ARRAY_SIZE(zx296718_pm_domains));
> > +}
> > +
> > +static const struct of_device_id zx296718_pm_domain_matches[] = {
> > + { .compatible = "zte,zx296718-pcu", },
> > + { },
> > +};
> > +
> > +static struct platform_driver zx296718_pd_driver = {
> > + .driver = {
> > + .name = "zx-powerdomain",
>
> This is a zx296718 specific driver. So zx296718-powerdomain should
> be a better name?
>
> Shawn
>
> > + .owner = THIS_MODULE,
> > + .of_match_table = zx296718_pm_domain_matches,
> > + },
> > + .probe = zx296718_pd_probe,
> > +};
> > +
> > +static int __init zx296718_pd_init(void)
> > +{
> > + return platform_driver_register(&zx296718_pd_driver);
> > +}
> > +subsys_initcall(zx296718_pd_init);
> > --
> > 2.7.4
> >
>
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^ permalink raw reply
* RE: [PATCH v2,9/9] irqchip/ls-scfg-msi: add MSI affinity support
From: M.H. Lian @ 2017-01-06 8:23 UTC (permalink / raw)
To: Marc Zyngier,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Rob Herring, Jason Cooper, Roy Zang, Mingkai Hu, Stuart Yoder,
Leo Li, Scott Wood
In-Reply-To: <7888f3a1-ae4a-f2b6-f41b-fc414f7ca968-5wv7dgnIgG8@public.gmane.org>
Hi Marc,
Thanks for your review.
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Marc Zyngier [mailto:marc.zyngier-5wv7dgnIgG8@public.gmane.org]
> Sent: Thursday, January 05, 2017 11:33 PM
> To: M.H. Lian <minghuan.lian-3arQi8VN3Tc@public.gmane.org>; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>; Jason Cooper
> <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>; Roy Zang <roy.zang-3arQi8VN3Tc@public.gmane.org>; Mingkai Hu
> <mingkai.hu-3arQi8VN3Tc@public.gmane.org>; Stuart Yoder <stuart.yoder-3arQi8VN3Tc@public.gmane.org>; Leo Li
> <leoyang.li-3arQi8VN3Tc@public.gmane.org>; Scott Wood <scott.wood-3arQi8VN3Tc@public.gmane.org>
> Subject: Re: [PATCH v2,9/9] irqchip/ls-scfg-msi: add MSI affinity support
>
> On 05/01/17 08:10, Minghuan Lian wrote:
> > For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4
> > CPUs. A GIC SPI interrupt of MSIR can be associated with a CPU.
> > When changing MSI interrupt affinity, this MSI will be moved to the
> > corresponding MSIR and MSI message data will be changed according to
> > MSIR. when requesting a MSI, the bits of all 4 MSIR will be reserved.
> > The parameter 'msi_affinity_flag' is provide to change this mode.
> > "lsmsi=no-affinity" will disable affinity, all MSI can only be
> > associated with CPU 0.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian-3arQi8VN3Tc@public.gmane.org>
> > ---
> > v2-v1:
> > - None
> >
> > drivers/irqchip/irq-ls-scfg-msi.c | 75
> > ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 70 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-ls-scfg-msi.c
> > b/drivers/irqchip/irq-ls-scfg-msi.c
> > index dc19569..753fe39 100644
> > --- a/drivers/irqchip/irq-ls-scfg-msi.c
> > +++ b/drivers/irqchip/irq-ls-scfg-msi.c
> > @@ -40,6 +40,7 @@ struct ls_scfg_msir {
> > unsigned int gic_irq;
> > unsigned int bit_start;
> > unsigned int bit_end;
> > + unsigned int srs; /* Shared interrupt register select */
> > void __iomem *reg;
> > };
> >
> > @@ -70,6 +71,19 @@ struct ls_scfg_msi {
> > .chip = &ls_scfg_msi_irq_chip,
> > };
> >
> > +static int msi_affinity_flag = 1;
> > +
> > +static int __init early_parse_ls_scfg_msi(char *p) {
> > + if (p && strncmp(p, "no-affinity", 11) == 0)
> > + msi_affinity_flag = 0;
> > + else
> > + msi_affinity_flag = 1;
> > +
> > + return 0;
> > +}
> > +early_param("lsmsi", early_parse_ls_scfg_msi);
>
> What is the point of this option? If feels like an unnecessary complexity.
[Minghuan Lian] For LS1043a rev1.1, there are only 8 MSI interrupts for each MSI controller when enable affinity.
(32 MSI interrupts are evenly distributed to 4 cores). 3 MSI controllers can only provide 32 MSI interrupts.
When disable affinity, the MSI interrupts number of 3 controllers can up to 32*3= 96.
32 MSI interrupts may be not enough.
For example: an Ethernet card with 4 ports, each port needs 4 RX, 4TX and 1 error interrupts, totally need 4*(4+4+1)
36 MSI interrupts.
With the parameter "lsmsi=no-affinity" this Ethernet card can work well, although the performance is poor.
>
> > +
> > static void ls_scfg_msi_compose_msg(struct irq_data *data, struct
> > msi_msg *msg) {
> > struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
> @@
> > -77,12 +91,43 @@ static void ls_scfg_msi_compose_msg(struct irq_data
> *data, struct msi_msg *msg)
> > msg->address_hi = upper_32_bits(msi_data->msiir_addr);
> > msg->address_lo = lower_32_bits(msi_data->msiir_addr);
> > msg->data = data->hwirq;
> > +
> > + if (msi_affinity_flag) {
> > + u32 msir_index;
> > +
> > + msir_index = cpumask_first(data->common->affinity);
> > + if (msir_index >= msi_data->msir_num)
> > + msir_index = 0;
>
> How can this happen?
[Minghuan Lian] This will never happen. I will remove this "if" sentence.
>
> > +
> > + msg->data |= msir_index;
>
> How do you guarantee that the low bits were clear? Please document the
> way you encode your MSI payload.
[Minghuan Lian] the available message data is a bytes.
7 6 5 4 3 2 1 0
| - | ibs | srs |
SRS bit 0-1 is used to select MSIR register/CPU. A MSIR is associated with a CPU.
IBS bit2-6 of ls1046, bit2-4 for ls1043 is used to select bit of the MSIR.
When enable affinity, only bits of MSIR0(srs = 0 cpu0) is be freed for requesting MSI.
all bits of the MSIR1-3(cpu1-3) are reserved to be sure this MSI can be successfully associated with cpu 1-3.
So, When requesting a MSI interrupt, srs always is 0.
The hwirq always equals bits number of the MSIR0(SRS = 0).
First, MSI message data payload equals hwirq, and then plus the real SRS according to smp_affinity.
This MSI interrupt will be routed to the corresponding the MSIR/CPU.
>
> > + }
> > }
> >
> > static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
> > const struct cpumask *mask, bool force) {
> > - return -EINVAL;
> > + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
> > + u32 cpu;
> > +
> > + if (!msi_affinity_flag)
> > + return -EINVAL;
> > +
> > + if (!force)
> > + cpu = cpumask_any_and(mask, cpu_online_mask);
> > + else
> > + cpu = cpumask_first(mask);
> > +
> > + if (cpu >= msi_data->msir_num)
> > + return -EINVAL;
> > +
> > + if (msi_data->msir[cpu].gic_irq <= 0) {
> > + pr_warn("cannot bind the irq to cpu%d\n", cpu);
>
> Please don't. Returning an error is enough. If you really want to have
> something, turn it into a proper debug message.
[Minghuan Lian] ok, I will change it.
>
> > + return -EINVAL;
> > + }
> > +
> > + cpumask_copy(irq_data->common->affinity, mask);
> > +
> > + return IRQ_SET_MASK_OK;
> > }
> >
> > static struct irq_chip ls_scfg_msi_parent_chip = { @@ -158,7 +203,7
> > @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
> >
> > for_each_set_bit_from(pos, &val, size) {
> > hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
> > - msir->index;
> > + msir->srs;
> > virq = irq_find_mapping(msi_data->parent, hwirq);
> > if (virq)
> > generic_handle_irq(virq);
> > @@ -221,10 +266,19 @@ static int ls_scfg_msi_setup_hwirq(struct
> ls_scfg_msi *msi_data, int index)
> > ls_scfg_msi_irq_handler,
> > msir);
> >
> > + if (msi_affinity_flag) {
> > + /* Associate MSIR interrupt to the cpu */
> > + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
> > + msir->srs = 0; /* This value is determined by the CPU */
> > + } else
> > + msir->srs = index;
> > +
> > /* Release the hwirqs corresponding to this MSIR */
> > - for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
> > - hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > - bitmap_clear(msi_data->used, hwirq, 1);
> > + if (!msi_affinity_flag || msir->index == 0) {
> > + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
> > + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > + bitmap_clear(msi_data->used, hwirq, 1);
> > + }
> > }
> >
> > return 0;
> > @@ -316,6 +370,17 @@ static int ls_scfg_msi_probe(struct
> platform_device *pdev)
> > bitmap_set(msi_data->used, 0, msi_data->irqs_num);
> >
> > msi_data->msir_num = of_irq_count(pdev->dev.of_node);
> > +
> > + if (msi_affinity_flag) {
> > + u32 cpu_num;
> > +
> > + cpu_num = num_possible_cpus();
> > + if (msi_data->msir_num >= cpu_num)
> > + msi_data->msir_num = cpu_num;
> > + else
> > + msi_affinity_flag = 0;
> > + }
> > +
> > msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
> > sizeof(*msi_data->msir),
> > GFP_KERNEL);
> >
>
> This is a very confusing patch. Please get rid of this useless option and
> document how you encode the routing in the hwirq.
[Minghuan Lian] Both LS1021a and LS1043av1.0 have only a MSIR, a gic interrupt.
MSI controllers cannot support affinity.
Then LS1046a/LS1043av1.1 extends MSIR number to 4 same to cpu number. So each MSIR with a GIC interrupt can be associated with a cpu.
To keep simple, the first patch for ls1046 and ls1043av1.1 keep the same way with ls1021 and ls1043av1.0 that does not support affinity and
all interrupts of MSIR0-3 are different and can be used for requesting MSI interrupts.
This patch is to enable affinity, that means, for ls1046a and ls1043av1.1, the same bit of MSIR0-3 will be looked as one interrupt using the same hwirq. And MSIRN only is used when the MSI interrupt is associated with the corresponding cpu.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: [PATCH 17/22] power: supply: add battery driver for AXP20X and AXP22X PMICs
From: Quentin Schulz @ 2017-01-06 8:29 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Mark Rutland, devicetree, Lars-Peter Clausen, open list:THERMAL,
linux-iio, linux-kernel, Sebastian Reichel, Russell King,
Bruno Prémont, Rob Herring, linux-arm-kernel,
Peter Meerwald-Stadler, knaack.h, Maxime Ripard, Lee Jones,
Thomas Petazzoni, Jonathan Cameron, Icenowy Zheng
In-Reply-To: <CAGb2v66XnWOGcaLeRo+cb6NGqfm_cyJVoK+GURUo5iV4pdZzew@mail.gmail.com>
Hi,
On 06/01/2017 04:39, Chen-Yu Tsai wrote:
> Hi,
>
> On Tue, Jan 3, 2017 at 12:37 AM, Quentin Schulz
> <quentin.schulz@free-electrons.com> wrote:
[...]
>> + case POWER_SUPPLY_PROP_CURRENT_MAX:
>> + ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1, ®);
>> + if (ret)
>> + return ret;
>> +
>> + reg &= AXP20X_CHRG_CTRL1_TGT_CURR;
>> + val->intval = reg * 100000 + 300000;
>> + break;
>
>
> This controls the charge current. I believe the correct property to use
> is CONSTANT_CHARGE_CURRENT. And you should add CONSTANT_CHARGE_CURRENT_MAX
> which returns the highest possible setting.
>
ACK.
> Also letting the user control this might not always be a good idea.
> IIUC, LiPo batteries can only be charged at 1C, where C is the
> rated capacity (X mAh).
>
OK. Should I get the charge current from a DT property then?
Like "x-powers,charge-current = <300000>;"
It's close to what has been done in bq24257_charger for example.
[...]
>> +static enum power_supply_property axp20x_battery_props[] = {
>> + POWER_SUPPLY_PROP_PRESENT,
>> + POWER_SUPPLY_PROP_ONLINE,
>> + POWER_SUPPLY_PROP_STATUS,
>> + POWER_SUPPLY_PROP_VOLTAGE_NOW,
>> + POWER_SUPPLY_PROP_CURRENT_NOW,
>> + POWER_SUPPLY_PROP_CURRENT_MAX,
>> + POWER_SUPPLY_PROP_HEALTH,
>> + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
>> + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN,
>> + POWER_SUPPLY_PROP_CAPACITY,
>
> You can also add POWER_SUPPLY_PROP_TECHNOLOGY, which would return
> POWER_SUPPLY_TECHNOLOGY_LIPO.
>
Hum.. There are also POWER_SUPPLY_TECHNOLOGY_LION,
POWER_SUPPLY_TECHNOLOGY_LiFe and POWER_SUPPLY_TECHNOLOGY_LiMn which are
all Lithium-based batteries. From the datasheet, it can take a "single
cell Li-battery (Li-Ion/Polymer)". So I guess it's either
POWER_SUPPLY_TECHNOLOGY_LION or POWER_SUPPLY_TECHNOLOGY_LIPO.
> It is also possible to do POWER_SUPPLY_PROP_CHARGE_TYPE. According
> to the manual, if the battery is charging, it is in constant current
> mode (POWER_SUPPLY_CHARGE_TYPE_FAST) when V_battery < V_target.
> When V_battery == V_target, it is in constant voltage mode, though
> I don't think this is the same as POWER_SUPPLY_CHARGE_TYPE_TRICKLE.
> When it is not charging, you can return POWER_SUPPLY_CHARGE_TYPE_NONE.
>
ACK, I'll look into that.
Thanks,
Quentin
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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