* Re: [PATCHv2 2/2] drm/panel: simple: Add support for Winstar WF35LTIACD
From: Rob Herring @ 2017-03-24 15:58 UTC (permalink / raw)
To: Richard Genoud; +Cc: Mark Rutland, devicetree, linux-kernel, dri-devel
In-Reply-To: <20170320133222.21773-1-richard.genoud@gmail.com>
On Mon, Mar 20, 2017 at 02:32:22PM +0100, Richard Genoud wrote:
> This adds support for the Winstar Display Co. WF35LTIACD 3.5" QVGA TFT
> LCD panel, which can be supported by the simple panel driver.
>
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> ---
>
> Changes since v1:
> Add power-supply property and an example in documentation
>
> .../bindings/display/panel/winstar,wf35ltiacd | 53 ++++++++++++++++++++++
> drivers/gpu/drm/panel/panel-simple.c | 28 ++++++++++++
> 2 files changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd
>
> diff --git a/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd b/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd
> new file mode 100644
> index 000000000000..9ff59b868b28
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/winstar,wf35ltiacd
> @@ -0,0 +1,53 @@
> +Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel
> +
> +Required properties:
> +- compatible: should be "winstar,wf35ltiacd"
> +- power-supply: regulator to provide the VCC supply voltage (3.3 volts)
> +
> +This binding is compatible with the simple-panel binding, which is specified
> +in simple-panel.txt in this directory.
> +
> +Example:
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&hlcdc_pwm 0 50000 PWM_POLARITY_INVERTED>;
> + brightness-levels = <0 31 63 95 127 159 191 223 255>;
> + default-brightness-level = <191>;
> + power-supply = <&bl_reg>;
> + status = "okay";
Drop status from examples.
> + };
> +
> + bl_reg: backlight_regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "backlight-power-supply";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + status = "okay";
> + };
> +
> + panel: panel {
> + compatible = "winstar,wf35ltiacd", "simple-panel";
> + backlight = <&backlight>;
> + power-supply = <&panel_reg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + panel_input: endpoint@0 {
> + reg = <0>;
You don't need reg and unit-addresses for these.
With that,
Acked-by: Rob Herring <robh@kernel.org>
> + remote-endpoint = <&hlcdc_panel_output>;
> + };
> + };
> + };
> +
> + panel_reg: panel_regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "panel-power-supply";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + status = "okay";
> + };
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v3, 4/4] dt-bindings: mtd: Add Octal SPI support to Cadence QSPI.
From: Rob Herring @ 2017-03-24 15:56 UTC (permalink / raw)
To: Artur Jedrysek
Cc: Mark Rutland, devicetree, Boris Brezillon, Richard Weinberger,
linux-kernel, Marek Vasut, linux-mtd, Cyrille Pitchen,
Brian Norris, David Woodhouse
In-Reply-To: <1490009254-4284-1-git-send-email-jartur@cadence.com>
On Mon, Mar 20, 2017 at 11:27:34AM +0000, Artur Jedrysek wrote:
> This patch updates Cadence QSPI Device Tree documentation to include
> information about new compatible used to indicate, whether or not
> Octal SPI transfers are supported by the device.
>
> Signed-off-by: Artur Jedrysek <jartur@cadence.com>
> ---
> Changelog:
> v2: Use new compatible, instead of boolean property, to indicate
> Octal SPI support.
> ---
> v3: Changes according to comments.
> ---
> Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply
* Re: [PATCH v11 01/10] devicetree: power: Add battery.txt
From: Rob Herring @ 2017-03-24 15:55 UTC (permalink / raw)
To: Liam Breck
Cc: Sebastian Reichel, Andrew F. Davis, linux-pm, Matt Ranostay,
devicetree, Liam Breck
In-Reply-To: <20170320094335.19224-2-liam@networkimprov.net>
On Mon, Mar 20, 2017 at 02:43:26AM -0700, Liam Breck wrote:
> From: Liam Breck <kernel@networkimprov.net>
>
> Documentation of static battery characteristics that can be defined
> for batteries which cannot self-identify. This information is required
> by fuel-gauge and charger chips for proper handling of the battery.
>
> Cc: Rob Herring <robh@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Matt Ranostay <matt@ranostay.consulting>
> Signed-off-by: Liam Breck <kernel@networkimprov.net>
> ---
> .../devicetree/bindings/power/supply/battery.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/supply/battery.txt
While "simple" is not generally something I like to see in a compatible
string, we've beat this one to death.
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: sun8i: add device tree for Lichee Pi Zero with Dock
From: Maxime Ripard @ 2017-03-24 15:55 UTC (permalink / raw)
To: Icenowy Zheng
Cc: linux-kernel, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Chen-Yu Tsai
In-Reply-To: <20170322223427.YNp8w8sn-jDEamKawf7I0PDqKvflMoHmW9unr2Ajn@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 5627 bytes --]
On Thu, Mar 23, 2017 at 03:34:18AM +0800, Icenowy Zheng wrote:
>
> 2017年3月23日 03:24于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
> >
> > On Fri, Mar 17, 2017 at 11:43:43PM +0800, Icenowy Zheng wrote:
> > > Lichee Pi Zero features a dock, which adds some functions, and should be
> > > soldered with the core board of Lichee Pi Zero.
> > >
> > > Add support for the dock as a new dts, as soldering is needed to make
> > > the dock usable and there's functions enabled on the dock that is
> > > unavailable at the 2.54mm pins of the core board.
> > >
> > > Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> > > ---
> > > arch/arm/boot/dts/Makefile | 3 +-
> > > arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 98 ++++++++++++++++++++++
> > > 2 files changed, 100 insertions(+), 1 deletion(-)
> > > create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
> > >
> > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > > index 43c27b624f94..de52d403f818 100644
> > > --- a/arch/arm/boot/dts/Makefile
> > > +++ b/arch/arm/boot/dts/Makefile
> > > @@ -878,7 +878,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> > > sun8i-h3-orangepi-plus.dtb \
> > > sun8i-h3-orangepi-plus2e.dtb \
> > > sun8i-r16-parrot.dtb \
> > > - sun8i-v3s-licheepi-zero.dtb
> > > + sun8i-v3s-licheepi-zero.dtb \
> > > + sun8i-v3s-licheepi-zero-dock.dtb
> > > dtb-$(CONFIG_MACH_SUN9I) += \
> > > sun9i-a80-optimus.dtb \
> > > sun9i-a80-cubieboard4.dtb
> > > diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
> > > new file mode 100644
> > > index 000000000000..956fa47fde53
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
> > > @@ -0,0 +1,98 @@
> > > +/*
> > > + * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> > > + *
> > > + * This file is dual-licensed: you can use it either under the terms
> > > + * of the GPL or the X11 license, at your option. Note that this dual
> > > + * licensing only applies to this file, and not this project as a
> > > + * whole.
> > > + *
> > > + * a) This file is free software; you can redistribute it and/or
> > > + * modify it under the terms of the GNU General Public License as
> > > + * published by the Free Software Foundation; either version 2 of the
> > > + * License, or (at your option) any later version.
> > > + *
> > > + * This file is distributed in the hope that it will be useful,
> > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > > + * GNU General Public License for more details.
> > > + *
> > > + * Or, alternatively,
> > > + *
> > > + * b) Permission is hereby granted, free of charge, to any person
> > > + * obtaining a copy of this software and associated documentation
> > > + * files (the "Software"), to deal in the Software without
> > > + * restriction, including without limitation the rights to use,
> > > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > > + * sell copies of the Software, and to permit persons to whom the
> > > + * Software is furnished to do so, subject to the following
> > > + * conditions:
> > > + *
> > > + * The above copyright notice and this permission notice shall be
> > > + * included in all copies or substantial portions of the Software.
> > > + *
> > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > > + * OTHER DEALINGS IN THE SOFTWARE.
> > > + */
> > > +
> > > +#include "sun8i-v3s-licheepi-zero.dts"
> > > +
> > > +#include <dt-bindings/input/input.h>
> > > +
> > > +/ {
> > > + model = "Lichee Pi Zero with Dock";
> > > + compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
> > > + "allwinner,sun8i-v3s";
> > > +};
> > > +
> > > +&leds {
> > > + /* The LEDs conflict with MMC1 slot */
> >
> > How does it conflicts?
>
> They both use PGx.
So they use the same bank? How is that a conflict?
> > > +&mmc1 {
> > > + pinctrl-0 = <&mmc1_pins>;
> > > + pinctrl-names = "default";
> > > + broken-cd;
> >
> > There's no card-detect on a GPIO?
>
> Yes.
>
> All SD slots on Lichee Pi series have no card-detect.
Weird... Ok.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v2 1/1] ARM: dts: sun8i: NanoPi NEO Air add WiFi / eMMC
From: Maxime Ripard @ 2017-03-24 15:46 UTC (permalink / raw)
To: Jelle van der Waa
Cc: Rob Herring, Mark Rutland, Chen-Yu Tsai,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20170323212444.20685-2-jelle-oJJ1AqDjjO4@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1277 bytes --]
Hi,
On Thu, Mar 23, 2017 at 10:24:44PM +0100, Jelle van der Waa wrote:
> Enable the WiFi (AP6212) chip and eMMC support for the NanoPi NEO Air.
>
> Signed-off-by: Jelle van der Waa <jelle-oJJ1AqDjjO4@public.gmane.org>
> ---
> arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts | 45 +++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> index 3ba081c1f555..457a28e56514 100644
> --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
> @@ -73,6 +73,13 @@
> gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
> };
> };
> +
> + wifi-pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi-en-nanopi-neo-air>;
Could you please drop that pinctrl group for that GPIO? It will help
us prevent a bug in the future in the pinctrl driver that allows two
GPIO users to claim the same pin.
Unfortunately, that will require removing all those pinctrl properties
for the GPIOs, so we'd better not introduce them in the first place :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v5 00/13] ACPI graph support
From: Mika Westerberg @ 2017-03-24 15:45 UTC (permalink / raw)
To: Sakari Ailus
Cc: linux-acpi-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, sudeep.holla-5wv7dgnIgG8,
lorenzo.pieralisi-5wv7dgnIgG8, rafael-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, broonie-DgEjT+Ai2ygdnm+yROfE0A,
robh-DgEjT+Ai2ygdnm+yROfE0A, ahs3-H+wXaHxf7aLQT0dZR+AlfA
In-Reply-To: <1489667481-28521-1-git-send-email-sakari.ailus-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
On Thu, Mar 16, 2017 at 02:31:08PM +0200, Sakari Ailus wrote:
> Hello everyone,
>
> This is the fifth version of the ACPI graph support patchset.
>
> The previous RFC version of the set is available here:
>
> <URL:http://www.spinics.net/lists/linux-acpi/msg69547.html>
>
> There are also v1, v2, v3 and v4 which can be found here:
>
> <URL:http://www.spinics.net/lists/linux-acpi/msg71661.html>
> <URL:http://www.spinics.net/lists/linux-acpi/msg71809.html>
> <URL:http://www.spinics.net/lists/linux-acpi/msg72171.html>
> <URL:http://www.spinics.net/lists/linux-acpi/msg72346.html>
>
> This set contains patches written by Mika Westerberg and by myself. The
> patchset brings support for graphs to ACPI. The functionality achieved by
> these patches is very similar to what the Device tree provides: the port
> and the endpoint concept are being employed. The patches make use of the
> _DSD property and data extensions to achieve this. The fwnode interface is
> extended by graph functionality; this way graph information originating
> from both OF and ACPI may be accessed using the same interface, without
> being aware of the underlying firmware interface.
>
> The last patch of the set contains ASL documentation including an example.
It would be helpful if you include similar diffstat here as running 'git
format-patch --cover-letter ...' generates.
Anyway for patches 7-13,
Reviewed-by: Mika Westerberg <mika.westerberg-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH V4 1/9] PM / OPP: Allow OPP table to be used for power-domains
From: Rob Herring @ 2017-03-24 15:44 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rafael Wysocki, ulf.hansson, Kevin Hilman, Viresh Kumar,
Nishanth Menon, Stephen Boyd, linaro-kernel, linux-pm,
linux-kernel, Vincent Guittot, lina.iyer, rnayak, devicetree
In-Reply-To: <e772e67a5445319bb8e0f312846ace666adc097f.1490001099.git.viresh.kumar@linaro.org>
On Mon, Mar 20, 2017 at 03:02:13PM +0530, Viresh Kumar wrote:
> Power-domains need to express their active states in DT and what's
> better than OPP table for that.
>
> This patch allows power-domains to reuse OPP tables to express their
> active states. The "opp-hz" property isn't a required property anymore
> as power-domains may not always use them.
Then maybe you shouldn't be trying to make OPP table work here. At that
point you just need a table of voltage(s) per performance state?
> Add a new property "domain-performance-state", which will contain
> positive integer values to represent performance levels of the
> power-domains as described in this patch.
Why not reference the OPP entries from the domain:
performance-states = <&opp1>, <&opp2>;
Just thinking out loud, not saying that is what you should do. The
continual evolution of power (management) domain, idle state, and OPP
bindings is getting tiring.
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> Documentation/devicetree/bindings/opp/opp.txt | 73 ++++++++++++++++++++++++++-
> 1 file changed, 71 insertions(+), 2 deletions(-)
>
^ permalink raw reply
* Re: [PATCH v3 1/7] pinctrl: Renesas RZ/A1 pin and gpio controller
From: Linus Walleij @ 2017-03-24 15:42 UTC (permalink / raw)
To: Jacopo Mondi
Cc: Geert Uytterhoeven, Laurent Pinchart, Chris Brandt, Rob Herring,
Mark Rutland, Russell King, Linux-Renesas,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <1490368934-12494-2-git-send-email-jacopo+renesas@jmondi.org>
On Fri, Mar 24, 2017 at 4:22 PM, Jacopo Mondi <jacopo+renesas@jmondi.org> wrote:
I assume Geert will queue this driver even if it is outside of sh-pfc?
> Add combined gpio and pin controller driver for Renesas RZ/A1
> r7s72100 SoC.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-rza1.c | 961 +++++++++++++++++++++++++++++++++++++++++
So this is very different from the SH-PFC family and should not
be in drivers/pinctrl/sh-pfc?
> +config PINCTRL_RZA1
> + bool "Renesas RZ/A1 gpio and pinctrl driver"
> + depends on OF
> + depends on ARCH_R7S72100 || COMPILE_TEST
> + select GENERIC_PINCTRL_GROUPS
> + select GENERIC_PINMUX_FUNCTIONS
> + select GENERIC_PINCONF
If it is also a GPIO driver I guess it should
select GPIOLIB as well.
This was not possible in the past, but it is possible nowadays.
> +struct gpio_chip rza1_gpiochip_template = {
> + .request = rza1_gpio_request,
> + .free = rza1_gpio_free,
> + .get_direction = rza1_gpio_get_direction,
> + .direction_input = rza1_gpio_direction_input,
> + .direction_output = rza1_gpio_direction_output,
> + .get = rza1_gpio_get,
> + .set = rza1_gpio_set,
> +};
We now also have .set_multiple() and more interestingly
.set_config() which can be backed by pinctrl if you want
to e.g. support debouncing and/or open drain/open source.
Maybe this is stuff your pin controller can do, but not needed
in the initial submission for sure.
> +static int rza1_pinmux_set(struct pinctrl_dev *pctldev, unsigned int selector,
> + unsigned int group)
Please name it rza1_set_mux() to correspond with the ops field.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 2/2] ata: ahci: add support for DaVinci DM816 SATA controller
From: Tejun Heo @ 2017-03-24 15:40 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Rob Herring, Mark Rutland, Neil Armstrong, Michael Turquette,
Kevin Hilman, Patrick Titiano, Tony Lindgren, Sergei Shtylyov,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1489489491-14195-3-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On Tue, Mar 14, 2017 at 12:04:51PM +0100, Bartosz Golaszewski wrote:
> This SATA controller is quite similar to the one present on the DA850
> SoC, but the PHY configuration is different and it supports two HBA
> ports.
>
> The IP suffers from the same PMP issue the DA850 does - if we enable
> PMP but don't use it - softreset fails. Appropriate workaround was
> implemented in this driver as well.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Applied to libata/for-4.12.
Thanks.
--
tejun
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^ permalink raw reply
* Re: [PATCH 2/4 v5] PCI: add driver for Faraday Technology Host Bridge
From: Bjorn Helgaas @ 2017-03-24 15:38 UTC (permalink / raw)
To: Linus Walleij
Cc: Hans Ulli Kroll, Florian Fainelli, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Bjorn Helgaas,
Arnd Bergmann, openwrt-devel-p3rKhJxN3npAfugRpC6u6w,
Feng-Hsin Chiang, Paulius Zaleckas, linux-pci, Greentime Hu,
Janos Laube,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <CACRpkdbkhui0iwJbOeD8uwurdWvOYdPKtRPQhSkg0atpAB174Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Fri, Mar 24, 2017 at 04:14:43PM +0100, Linus Walleij wrote:
> On Fri, Mar 24, 2017 at 4:07 PM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
>
> > Acked-by: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
>
> Thanks!
>
> > I don't know enough to review the DT patch, but you have Rob's ack
> > already.
> >
> > Not sure how you want to merge these; if you want to feed the whole
> > thing via ARM SoC, that's fine with me. Otherwise, let me know if
> > you'd like me to take anything.
>
> It'd be perfect if you could merge patches 1+2 into the PCI tree,
> there are no dependencies to the ARM tree.
>
> > Noticed one trivial typo below.
> >
> >> + * Special configuration registers directly in the first few words
> >> + * in he I/O space.
> >
> > s/he//
>
> Can you fix it when applying or do you want me to resend it with
> this fixed?
I fixed it.
Applied 1 & 2 to pci/host-faraday for v4.12, thanks!
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^ permalink raw reply
* [PATCH 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler
From: Alan Tull @ 2017-03-24 15:33 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Moritz Fischer, Alan Tull, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fpga-u79uwXL29TY76Z2rM5mHXA, Moritz Fischer, Michal Simek,
Sören Brinkmann, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170324153321.4168-1-atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
From: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
This adds support for the Xilinx LogiCORE PR Decoupler
soft-ip that does decoupling of PR regions in the FPGA
fabric during partial reconfiguration.
Signed-off-by: Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Cc: Sören Brinkmann <soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Acked-by: Alan Tull <atull-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
drivers/fpga/Kconfig | 10 +++
drivers/fpga/Makefile | 1 +
drivers/fpga/xilinx-pr-decoupler.c | 161 +++++++++++++++++++++++++++++++++++++
3 files changed, 172 insertions(+)
create mode 100644 drivers/fpga/xilinx-pr-decoupler.c
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 116ee92fe034..161ba9dccede 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -95,6 +95,16 @@ config ALTERA_PR_IP_CORE_PLAT
Platform driver support for Altera Partial Reconfiguration IP
component
+config XILINX_PR_DECOUPLER
+ tristate "Xilinx LogiCORE PR Decoupler"
+ depends on FPGA_BRIDGE
+ depends on HAS_IOMEM
+ help
+ Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
+ The PR Decoupler exists in the FPGA fabric to isolate one
+ region of the FPGA from the busses while that region is
+ being reprogrammed during partial reconfig.
+
endif # FPGA
endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 530cf9410dde..2a4f0218145c 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
+obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
# High Level Interfaces
obj-$(CONFIG_FPGA_REGION) += fpga-region.o
diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
new file mode 100644
index 000000000000..e359930bebc8
--- /dev/null
+++ b/drivers/fpga/xilinx-pr-decoupler.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2017, National Instruments Corp.
+ * Copyright (c) 2017, Xilix Inc
+ *
+ * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
+ * Decoupler IP Core.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/fpga/fpga-bridge.h>
+
+#define CTRL_CMD_DECOUPLE BIT(0)
+#define CTRL_CMD_COUPLE 0
+#define CTRL_OFFSET 0
+
+struct xlnx_pr_decoupler_data {
+ void __iomem *io_base;
+ struct clk *clk;
+};
+
+static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
+ u32 offset, u32 val)
+{
+ writel(val, d->io_base + offset);
+}
+
+static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
+ u32 offset)
+{
+ return readl(d->io_base + offset);
+}
+
+static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
+{
+ int err;
+ struct xlnx_pr_decoupler_data *priv = bridge->priv;
+
+ err = clk_enable(priv->clk);
+ if (err)
+ return err;
+
+ if (enable)
+ xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
+ else
+ xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
+
+ clk_disable(priv->clk);
+
+ return 0;
+}
+
+static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
+{
+ const struct xlnx_pr_decoupler_data *priv = bridge->priv;
+ u32 status;
+ int err;
+
+ err = clk_enable(priv->clk);
+ if (err)
+ return err;
+
+ status = readl(priv->io_base);
+
+ clk_disable(priv->clk);
+
+ return !status;
+}
+
+static struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
+ .enable_set = xlnx_pr_decoupler_enable_set,
+ .enable_show = xlnx_pr_decoupler_enable_show,
+};
+
+static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
+ { .compatible = "xlnx,pr-decoupler-1.00", },
+ { .compatible = "xlnx,pr-decoupler", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
+
+static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
+{
+ struct xlnx_pr_decoupler_data *priv;
+ int err;
+ struct resource *res;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->io_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(priv->io_base))
+ return PTR_ERR(priv->io_base);
+
+ priv->clk = devm_clk_get(&pdev->dev, "aclk");
+ if (IS_ERR(priv->clk)) {
+ dev_err(&pdev->dev, "input clock not found\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ err = clk_prepare_enable(priv->clk);
+ if (err) {
+ dev_err(&pdev->dev, "unable to enable clock\n");
+ return err;
+ }
+
+ clk_disable(priv->clk);
+
+ err = fpga_bridge_register(&pdev->dev, "Xilinx PR Decoupler",
+ &xlnx_pr_decoupler_br_ops, priv);
+
+ if (err) {
+ dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
+ clk_unprepare(priv->clk);
+ return err;
+ }
+
+ return 0;
+}
+
+static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
+{
+ struct fpga_bridge *bridge = platform_get_drvdata(pdev);
+ struct xlnx_pr_decoupler_data *p = bridge->priv;
+
+ fpga_bridge_unregister(&pdev->dev);
+
+ clk_unprepare(p->clk);
+
+ return 0;
+}
+
+static struct platform_driver xlnx_pr_decoupler_driver = {
+ .probe = xlnx_pr_decoupler_probe,
+ .remove = xlnx_pr_decoupler_remove,
+ .driver = {
+ .name = "xlnx_pr_decoupler",
+ .of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
+ },
+};
+
+module_platform_driver(xlnx_pr_decoupler_driver);
+
+MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
+MODULE_AUTHOR("Moritz Fischer <mdf-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>");
+MODULE_AUTHOR("Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler
From: Alan Tull @ 2017-03-24 15:33 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Moritz Fischer, Alan Tull, linux-kernel, linux-fpga,
Moritz Fischer, Michal Simek, Sören Brinkmann, devicetree
In-Reply-To: <20170324153321.4168-1-atull@kernel.org>
From: Moritz Fischer <mdf@kernel.org>
This adds the binding documentation for the Xilinx LogiCORE PR
Decoupler soft core.
Signed-off-by: Moritz Fischer <mdf@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Alan Tull <atull@kernel.org>
Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
.../bindings/fpga/xilinx-pr-decoupler.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
new file mode 100644
index 000000000000..2c527ac30398
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge. The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+ 1 if driver should enable bridge at startup
+ Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+ "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v3 4/7] arm: dts: r7s72100: Add pin controller node
From: Sergei Shtylyov @ 2017-03-24 15:32 UTC (permalink / raw)
To: Jacopo Mondi, geert+renesas, laurent.pinchart, chris.brandt,
linus.walleij, robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-5-git-send-email-jacopo+renesas@jmondi.org>
Hello!
On 03/24/2017 06:22 PM, Jacopo Mondi wrote:
> Add pin controller node with 12 gpio controller sub-nodes to
> r7s72100 dtsi.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> arch/arm/boot/dts/r7s72100.dtsi | 80 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 80 insertions(+)
>
> diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
> index b8aa256..83e8f27 100644
> --- a/arch/arm/boot/dts/r7s72100.dtsi
> +++ b/arch/arm/boot/dts/r7s72100.dtsi
> @@ -180,6 +180,86 @@
> };
> };
>
> + pinctrl: pinctrl@fcfe3000 {
I suggest to call it "pin-controller@...", no need to reduce.
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH] ASoC: wm8903: add regulator handling
From: Rob Herring @ 2017-03-24 15:30 UTC (permalink / raw)
To: Linus Walleij
Cc: Liam Girdwood, Mark Brown, alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, Stephen Warren, Charles Keepax
In-Reply-To: <20170320091352.4115-1-linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Mon, Mar 20, 2017 at 10:13:52AM +0100, Linus Walleij wrote:
> The WM8903 has four different voltage inputs: AVDD, CPVDD, DBVDD
> and DCVDD. On the Qualcomm APQ8060 Dragonboard these are all
> supplied from proper regulators and thus need activating and
> binding.
>
> This is a quick-and-dirty solution just grabbing and enabling the
> regulator supplies on probe() and disabling them on remove() and
> the errorpath. More elaborate power management is likely possible.
>
> I assume the nVidia designs using this codec have some hard-wired
> always-on power and will be happy with using the dummy regulators
> for this. But someone from the nVidia camp should probably check
> whether they can bind these to proper regulators instead.
>
> We also amend the DT binding document. A small change like this
> does not warrant a separate patch for augmenting these.
>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Liam Girdwood <lgirdwood-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Cc: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> Cc: Charles Keepax <ckeepax-yzvPICuk2AATkU/dhu1WVueM+bqZidxxQQ4Iyu8u01E@public.gmane.org>
> Signed-off-by: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> Mark: I was thinking about adding runtime PM for disabling
> these regulators when unused, but I'm uncertain about the
> interaction with DAPM in that regard. This atleast gives us
> control over the supplies.
> ---
> Documentation/devicetree/bindings/sound/wm8903.txt | 13 +++++++++
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> sound/soc/codecs/wm8903.c | 31 ++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
--
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^ permalink raw reply
* [PATCH v3 4/4] arm64: dts: salvator-x: Add current sense amplifiers
From: Jacopo Mondi @ 2017-03-24 15:28 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490369323-13866-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add device nodes for two Maxim max961x current sense amplifiers
sensing VDD_08 and DVFS_08 lines.
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index c7f40f8..389a177 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -257,6 +257,24 @@
status = "okay";
};
+&i2c4 {
+ status = "okay";
+
+ csa_vdd: adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+
+ shunt-resistor-uohm = <5000>;
+ };
+
+ csa_dvfs: adc@7f {
+ compatible = "maxim,max9611";
+ reg = <0x7f>;
+
+ shunt-resistor-uohm = <5000>;
+ };
+};
+
&wdt0 {
timeout-sec = <60>;
status = "okay";
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v3 3/4] iio: adc: Add Maxim max9611 ADC driver
From: Jacopo Mondi @ 2017-03-24 15:28 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490369323-13866-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add iio driver for Maxim max9611 and max9612 current-sense amplifiers
with 12-bits ADC interface.
Datasheet publicly available at:
https://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
drivers/iio/adc/Kconfig | 10 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/max9611.c | 590 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 601 insertions(+)
create mode 100644 drivers/iio/adc/max9611.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index dedae7a..82f2e7b8 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -354,6 +354,16 @@ config MAX1363
To compile this driver as a module, choose M here: the module will be
called max1363.
+config MAX9611
+ tristate "Maxim max9611/max9612 ADC driver"
+ depends on I2C
+ help
+ Say yes here to build support for Maxim max9611/max9612 current sense
+ amplifier with 12-bits ADC interface.
+
+ To compile this driver as a module, choose M here: the module will be
+ called max9611.
+
config MCP320X
tristate "Microchip Technology MCP3x01/02/04/08"
depends on SPI
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d001262..149f979 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_LTC2485) += ltc2485.o
obj-$(CONFIG_MAX1027) += max1027.o
obj-$(CONFIG_MAX11100) += max11100.o
obj-$(CONFIG_MAX1363) += max1363.o
+obj-$(CONFIG_MAX9611) += max9611.o
obj-$(CONFIG_MCP320X) += mcp320x.o
obj-$(CONFIG_MCP3422) += mcp3422.o
obj-$(CONFIG_MEDIATEK_MT6577_AUXADC) += mt6577_auxadc.o
diff --git a/drivers/iio/adc/max9611.c b/drivers/iio/adc/max9611.c
new file mode 100644
index 0000000..61566ec
--- /dev/null
+++ b/drivers/iio/adc/max9611.c
@@ -0,0 +1,590 @@
+/*
+ * iio/adc/max9611.c
+ *
+ * Maxim max9611/max9612 high side current sense amplifier with
+ * 12-bit ADC interface.
+ *
+ * Copyright (C) 2017 Jacopo Mondi
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This driver supports input common-mode voltage, current-sense
+ * amplifier with programmable gains and die temperature reading from
+ * Maxim max9611/max9612.
+ *
+ * Op-amp, analog comparator, and watchdog functionalities are not
+ * supported by this driver.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/module.h>
+
+#define DRIVER_NAME "max9611"
+
+/* max9611 register addresses */
+#define MAX9611_REG_CSA_DATA 0x00
+#define MAX9611_REG_RS_DATA 0x02
+#define MAX9611_REG_TEMP_DATA 0x08
+#define MAX9611_REG_CTRL1 0x0a
+#define MAX9611_REG_CTRL2 0x0b
+
+/* max9611 REG1 mux configuration options */
+#define MAX9611_MUX_MASK 0x07
+#define MAX9611_MUX_SENSE_1x 0x00
+#define MAX9611_MUX_SENSE_4x 0x01
+#define MAX9611_MUX_SENSE_8x 0x02
+#define MAX9611_INPUT_VOLT 0x03
+#define MAX9611_MUX_TEMP 0x06
+
+/* max9611 voltage (both csa and input) helper macros */
+#define MAX9611_VOLTAGE_SHIFT 0x04
+#define MAX9611_VOLTAGE_RAW(_r) ((_r) >> MAX9611_VOLTAGE_SHIFT)
+
+/*
+ * max9611 current sense amplifier voltage output:
+ * LSB and offset values depends on selected gain (1x, 4x, 8x)
+ *
+ * GAIN LSB (nV) OFFSET (LSB steps)
+ * 1x 107500 1
+ * 4x 26880 1
+ * 8x 13440 3
+ *
+ * The complete formula to calculate current sense voltage is:
+ * (((adc_read >> 4) - offset) / ((1 / LSB) * 10^-3)
+ */
+#define CSA_VOLT_1x_LSB_nV 107500
+#define CSA_VOLT_4x_LSB_nV 26880
+#define CSA_VOLT_8x_LSB_nV 13440
+
+#define CSA_VOLT_1x_OFFS_RAW 1
+#define CSA_VOLT_4x_OFFS_RAW 1
+#define CSA_VOLT_8x_OFFS_RAW 3
+
+/*
+ * max9611 common input mode (CIM): LSB is 14mV, with 14mV offset at 25 C
+ *
+ * The complete formula to calculate input common voltage is:
+ * (((adc_read >> 4) * 1000) - offset) / (1 / 14 * 1000)
+ */
+#define CIM_VOLTAGE_LSB_mV 14
+#define CIM_VOLTAGE_OFFSET_RAW 1
+
+/*
+ * max9611 temperature reading: LSB is 0.48 degrees Celsius
+ *
+ * The complete formula to calculate temperature is:
+ * ((adc_read >> 7) * 1000) / (1 / 0.48 * 1000)
+ */
+#define TEMP_SHIFT 0x07
+#define TEMP_MAX_RAW_POS 0x7f80
+#define TEMP_MAX_RAW_NEG 0xff80
+#define TEMP_MIN_RAW_NEG 0xd980
+#define TEMP_MASK ((1 << TEMP_SHIFT) - 1)
+#define TEMP_RAW(_r) ((_r) >> TEMP_SHIFT)
+#define TEMP_LSB_mC 480
+#define TEMP_SCALE_NUM 1000
+#define TEMP_SCALE_DIV 2083
+
+struct max9611_dev {
+ struct device *dev;
+ struct i2c_client *i2c_client;
+ struct mutex lock;
+ unsigned int shunt_resistor_uohm;
+};
+
+enum max9611_conf_ids {
+ CONF_SENSE_1x,
+ CONF_SENSE_4x,
+ CONF_SENSE_8x,
+ CONF_IN_VOLT,
+ CONF_TEMP,
+};
+
+/**
+ * max9611_mux_conf - associate ADC mux configuration with register address
+ * where data shall be read from
+ */
+static unsigned int max9611_mux_conf[][2] = {
+ /* CONF_SENSE_1x */
+ { MAX9611_MUX_SENSE_1x, MAX9611_REG_CSA_DATA },
+ /* CONF_SENSE_4x */
+ { MAX9611_MUX_SENSE_4x, MAX9611_REG_CSA_DATA },
+ /* CONF_SENSE_8x */
+ { MAX9611_MUX_SENSE_8x, MAX9611_REG_CSA_DATA },
+ /* CONF_IN_VOLT */
+ { MAX9611_INPUT_VOLT, MAX9611_REG_RS_DATA },
+ /* CONF_TEMP */
+ { MAX9611_MUX_TEMP, MAX9611_REG_TEMP_DATA },
+};
+
+enum max9611_csa_gain {
+ CSA_GAIN_1x,
+ CSA_GAIN_4x,
+ CSA_GAIN_8x,
+};
+
+enum max9611_csa_gain_params {
+ CSA_GAIN_LSB_nV,
+ CSA_GAIN_OFFS_RAW,
+};
+
+/**
+ * max9611_csa_gain_conf - associate gain multiplier with LSB and
+ * offset values.
+ *
+ * Group together parameters associated with configurable gain
+ * on current sense amplifier path to ADC interface.
+ * Current sense read routine adjusts gain until it gets a meaningful
+ * value; use this structure to retrieve the correct LSB and offset values.
+ */
+static unsigned int max9611_gain_conf[][2] = {
+ { /* [0] CSA_GAIN_1x */
+ CSA_VOLT_1x_LSB_nV,
+ CSA_VOLT_1x_OFFS_RAW,
+ },
+ { /* [1] CSA_GAIN_4x */
+ CSA_VOLT_4x_LSB_nV,
+ CSA_VOLT_4x_OFFS_RAW,
+ },
+ { /* [2] CSA_GAIN_8x */
+ CSA_VOLT_8x_LSB_nV,
+ CSA_VOLT_8x_OFFS_RAW,
+ },
+};
+
+enum max9611_chan_addrs {
+ MAX9611_CHAN_VOLTAGE_INPUT,
+ MAX9611_CHAN_VOLTAGE_SENSE,
+ MAX9611_CHAN_TEMPERATURE,
+ MAX9611_CHAN_CURRENT_LOAD,
+ MAX9611_CHAN_POWER_LOAD,
+};
+
+static struct iio_chan_spec max9611_channels[] = {
+ {
+ .type = IIO_TEMP,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE),
+ .address = MAX9611_CHAN_TEMPERATURE,
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE) |
+ BIT(IIO_CHAN_INFO_OFFSET),
+ .address = MAX9611_CHAN_VOLTAGE_INPUT,
+ .indexed = 1,
+ .channel = 1,
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_VOLTAGE_SENSE,
+ .indexed = 1,
+ .channel = 0,
+ },
+ {
+ .type = IIO_CURRENT,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_CURRENT_LOAD,
+ },
+ {
+ .type = IIO_POWER,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
+ .address = MAX9611_CHAN_POWER_LOAD
+ },
+};
+
+/**
+ * max9611_read_single() - read a single vale from ADC interface
+ *
+ * Data registers are 16 bit long, spread between two 8 bit registers
+ * with consecutive addresses.
+ * Configure ADC mux first, then read register at address "reg_addr".
+ * The smbus_read_word routine asks for 16 bits and the ADC is kind enough
+ * to return values from "reg_addr" and "reg_addr + 1" consecutively.
+ *
+ * @max9611: max9611 device
+ * @selector: index for mux and register configuration
+ * @raw_val: the value returned from ADC
+ */
+static int max9611_read_single(struct max9611_dev *max9611,
+ enum max9611_conf_ids selector,
+ u16 *raw_val)
+{
+ int ret;
+
+ u8 mux_conf = max9611_mux_conf[selector][0] & MAX9611_MUX_MASK;
+ u8 reg_addr = max9611_mux_conf[selector][1];
+
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL1, mux_conf);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL1, mux_conf);
+ return ret;
+ }
+
+ /*
+ * need a delay here to make register configuration
+ * stabilize. 1 msec at least, from empirical testing.
+ */
+ usleep_range(1000, 2000);
+
+ ret = i2c_smbus_read_word_swapped(max9611->i2c_client, reg_addr);
+ if (ret < 0) {
+ dev_err(max9611->dev, "i2c read word from 0x%2x failed\n",
+ reg_addr);
+ return ret;
+ }
+ *raw_val = ret;
+
+ return 0;
+}
+
+/**
+ * max9611_read_csa_voltage() - read current sense amplifier output voltage
+ *
+ * Current sense amplifier output voltage is read through a configurable
+ * 1x, 4x or 8x gain.
+ * Start with plain 1x gain, and adjust gain control properly until a
+ * meaningful value is read from ADC output.
+ *
+ * @max9611: max9611 device
+ * @adc_raw: raw value read from ADC output
+ * @csa_gain: gain configuration option selector
+ */
+static int max9611_read_csa_voltage(struct max9611_dev *max9611,
+ u16 *adc_raw,
+ enum max9611_csa_gain *csa_gain)
+{
+ enum max9611_conf_ids gain_selectors[] = {
+ CONF_SENSE_1x,
+ CONF_SENSE_4x,
+ CONF_SENSE_8x
+ };
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < ARRAY_SIZE(gain_selectors); ++i) {
+ ret = max9611_read_single(max9611, gain_selectors[i], adc_raw);
+ if (ret)
+ return ret;
+
+ if (*adc_raw > 0) {
+ *csa_gain = gain_selectors[i];
+ return 0;
+ }
+ }
+
+ return -EIO;
+}
+
+static int max9611_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct max9611_dev *dev = iio_priv(indio_dev);
+ enum max9611_csa_gain gain_selector;
+ unsigned int *csa_gain;
+ u16 adc_data;
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&dev->lock);
+
+ switch (chan->address) {
+ case MAX9611_CHAN_TEMPERATURE:
+ ret = max9611_read_single(dev, CONF_TEMP,
+ &adc_data);
+ if (ret)
+ goto unlock_fail;
+
+ *val = TEMP_RAW(adc_data);
+
+ mutex_unlock(&dev->lock);
+ return IIO_VAL_INT;
+
+ case MAX9611_CHAN_VOLTAGE_INPUT:
+ ret = max9611_read_single(dev, CONF_IN_VOLT,
+ &adc_data);
+ if (ret)
+ goto unlock_fail;
+
+ *val = MAX9611_VOLTAGE_RAW(adc_data);
+
+ mutex_unlock(&dev->lock);
+ return IIO_VAL_INT;
+ }
+
+ case IIO_CHAN_INFO_OFFSET:
+ switch (chan->address) {
+ case MAX9611_CHAN_VOLTAGE_INPUT:
+ *val = CIM_VOLTAGE_OFFSET_RAW;
+
+ return IIO_VAL_INT;
+ }
+
+ case IIO_CHAN_INFO_SCALE:
+ switch (chan->address) {
+ case MAX9611_CHAN_TEMPERATURE:
+ *val = TEMP_SCALE_NUM;
+ *val2 = TEMP_SCALE_DIV;
+
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_VOLTAGE_INPUT:
+ *val = CIM_VOLTAGE_LSB_mV;
+ return IIO_VAL_INT;
+ }
+
+ case IIO_CHAN_INFO_PROCESSED:
+ mutex_lock(&dev->lock);
+
+ switch (chan->address) {
+ case MAX9611_CHAN_VOLTAGE_SENSE:
+ /*
+ * processed (mV): (raw - offset) * LSB (nV) / 10^6
+ *
+ * Even if max9611 can output raw csa voltage readings,
+ * use a produced value as scale depends on gain.
+ */
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ goto unlock_fail;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV];
+ *val2 = 1000000;
+
+ mutex_unlock(&dev->lock);
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_CURRENT_LOAD:
+ /* processed (mA): Vcsa (nV) / Rshunt (uOhm) */
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ goto unlock_fail;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV];
+ *val2 = dev->shunt_resistor_uohm;
+
+ mutex_unlock(&dev->lock);
+ return IIO_VAL_FRACTIONAL;
+
+ case MAX9611_CHAN_POWER_LOAD:
+ /*
+ * processed (mW): Vin (mV) * Vcsa (uV) /
+ * Rshunt (uOhm)
+ */
+ ret = max9611_read_single(dev, CONF_IN_VOLT,
+ &adc_data);
+ if (ret)
+ goto unlock_fail;
+
+ adc_data -= CIM_VOLTAGE_OFFSET_RAW;
+ *val = MAX9611_VOLTAGE_RAW(adc_data) *
+ CIM_VOLTAGE_LSB_mV;
+
+ ret = max9611_read_csa_voltage(dev, &adc_data,
+ &gain_selector);
+ if (ret)
+ goto unlock_fail;
+
+ csa_gain = max9611_gain_conf[gain_selector];
+
+ /* divide by 10^3 here to avoid 32bit overflow */
+ adc_data -= csa_gain[CSA_GAIN_OFFS_RAW];
+ *val *= MAX9611_VOLTAGE_RAW(adc_data) *
+ csa_gain[CSA_GAIN_LSB_nV] / 1000;
+ *val2 = dev->shunt_resistor_uohm;
+
+ mutex_unlock(&dev->lock);
+ return IIO_VAL_FRACTIONAL;
+ }
+ }
+
+ ret = -EINVAL;
+
+unlock_fail:
+ mutex_unlock(&dev->lock);
+ return ret;
+
+}
+
+static ssize_t max9611_shunt_resistor_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct max9611_dev *max9611 = iio_priv(dev_to_iio_dev(dev));
+
+ return sprintf(buf, "%d\n", max9611->shunt_resistor_uohm);
+}
+
+static IIO_DEVICE_ATTR(in_shunt_resistor_power, 0444,
+ max9611_shunt_resistor_show, NULL, 0);
+static IIO_DEVICE_ATTR(in_shunt_resistor_current, 0444,
+ max9611_shunt_resistor_show, NULL, 0);
+
+static struct attribute *max9611_attributes[] = {
+ &iio_dev_attr_in_shunt_resistor_power.dev_attr.attr,
+ &iio_dev_attr_in_shunt_resistor_current.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group max9611_attribute_group = {
+ .attrs = max9611_attributes,
+};
+
+static const struct iio_info indio_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = max9611_read_raw,
+ .attrs = &max9611_attribute_group,
+};
+
+static int max9611_init(struct max9611_dev *max9611)
+{
+ struct i2c_client *client = max9611->i2c_client;
+ u16 regval;
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_WRITE_BYTE |
+ I2C_FUNC_SMBUS_READ_WORD_DATA)) {
+ dev_err(max9611->dev,
+ "No smbus support in I2c adapter: aborting probe.\n");
+ return -EINVAL;
+ }
+
+ /* Configure MUX to read temperature */
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL1, MAX9611_MUX_TEMP);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL1, MAX9611_MUX_TEMP);
+ return ret;
+ }
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL2, 0);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL2, 0);
+ return ret;
+ }
+ usleep_range(1000, 2000);
+
+ /* Make sure die temperature is in range to test communications. */
+ ret = i2c_smbus_read_word_swapped(max9611->i2c_client,
+ MAX9611_REG_TEMP_DATA);
+ if (ret < 0) {
+ dev_err(max9611->dev, "i2c read word from 0x%2x failed\n",
+ MAX9611_REG_TEMP_DATA);
+ return ret;
+ }
+ regval = ret & ~TEMP_MASK;
+
+ if ((regval > TEMP_MAX_RAW_POS &&
+ regval < TEMP_MIN_RAW_NEG) ||
+ regval > TEMP_MAX_RAW_NEG) {
+ dev_err(max9611->dev,
+ "Invalid value received from ADC 0x%4x: aborting\n",
+ regval);
+ return -EIO;
+ }
+
+ /* Mux shall be zeroed back before applying other configurations */
+ ret = i2c_smbus_write_byte_data(max9611->i2c_client,
+ MAX9611_REG_CTRL1, 0);
+ if (ret) {
+ dev_err(max9611->dev, "i2c write byte failed: 0x%2x - 0x%2x\n",
+ MAX9611_REG_CTRL1, 0);
+ return ret;
+ }
+ usleep_range(1000, 2000);
+
+ return 0;
+}
+
+static int max9611_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ const char * const shunt_res_prop = "shunt-resistor-uohm";
+ struct device_node *of_node = client->dev.of_node;
+ struct max9611_dev *max9611;
+ struct iio_dev *indio_dev;
+ unsigned int of_shunt;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*max9611));
+ if (IS_ERR(indio_dev))
+ return PTR_ERR(indio_dev);
+
+ i2c_set_clientdata(client, indio_dev);
+
+ max9611 = iio_priv(indio_dev);
+ max9611->dev = &client->dev;
+ max9611->i2c_client = client;
+ mutex_init(&max9611->lock);
+
+ ret = of_property_read_u32(of_node, shunt_res_prop, &of_shunt);
+ if (ret) {
+ dev_err(&client->dev,
+ "Missing %s property for %s node\n",
+ shunt_res_prop, of_node->full_name);
+ return ret;
+ }
+ max9611->shunt_resistor_uohm = of_shunt;
+
+ ret = max9611_init(max9611);
+ if (ret)
+ return ret;
+
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->dev.of_node = client->dev.of_node;
+ indio_dev->name = client->dev.of_node->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->info = &indio_info;
+ indio_dev->channels = max9611_channels;
+ indio_dev->num_channels = ARRAY_SIZE(max9611_channels);
+
+ return devm_iio_device_register(&client->dev, indio_dev);
+}
+
+static const struct of_device_id max9611_of_table[] = {
+ {.compatible = "maxim,max9611"},
+ {.compatible = "maxim,max9612"},
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, max9611_of_table);
+
+static struct i2c_driver max9611_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = max9611_of_table,
+ },
+ .probe = max9611_probe,
+};
+module_i2c_driver(max9611_driver);
+
+MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>");
+MODULE_DESCRIPTION("Maxim max9611/12 current sense amplifier with 12bit ADC");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/4] iio: Documentation: Add max9611 sysfs documentation
From: Jacopo Mondi @ 2017-03-24 15:28 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490369323-13866-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add documentation for max9611 driver.
Document attributes describing value of shunt resistor installed between
RS+ and RS- voltage sense inputs.
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
Documentation/ABI/testing/sysfs-bus-iio-adc-max9611 | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-max9611
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-max9611 b/Documentation/ABI/testing/sysfs-bus-iio-adc-max9611
new file mode 100644
index 0000000..9c60824
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-iio-adc-max9611
@@ -0,0 +1,16 @@
+What: /sys/bus/iio/devices/iio:deviceX/in_shunt_resistor_power
+Date: March 2017
+KernelVersion: 4.12
+Contact: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+Description: The value of the shunt resistor used to compute power drain on
+ common input voltage pin (RS+). In micro Ohms.
+
+What: /sys/bus/iio/devices/iio:deviceX/in_shunt_resistor_current
+Date: March 2017
+KernelVersion: 4.12
+Contact: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+Description: The value of the shunt resistor used to compute current flowing
+ between RS+ and RS- voltage sense inputs. In micro Ohms.
+ This attributes describe a single physical component, exposed
+ as two distinct attributes as it is used to calculate two
+ different values.
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/4] Documentation: dt-bindings: iio: Add max9611 ADC
From: Jacopo Mondi @ 2017-03-24 15:28 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1490369323-13866-1-git-send-email-jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
Add device tree bindings documentation for Maxim max9611/max9612 current
sense amplifier.
Signed-off-by: Jacopo Mondi <jacopo+renesas-AW8dsiIh9cEdnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/iio/adc/max9611.txt | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/max9611.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/max9611.txt b/Documentation/devicetree/bindings/iio/adc/max9611.txt
new file mode 100644
index 0000000..8430d3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/max9611.txt
@@ -0,0 +1,26 @@
+* Maxim max9611/max9612 current sense amplifier with 12-bits ADC interface
+
+Maxim max9611/max9612 is an high-side current sense amplifier with integrated
+12-bits ADC communicating over I2c bus.
+The device node for this driver shall be a child of a I2c controller.
+
+Required properties
+ - compatible: Should be "maxim,max9611" or "maxim,max9612"
+ - reg: The 7-bits long I2c address of the device
+ - shunt-resistor-uohm: Value, in uOhm, of the current sense shunt resistor
+
+Example:
+
+&i2c4 {
+ csa: adc@7c {
+ compatible = "maxim,max9611";
+ reg = <0x7c>;
+
+ shunt-resistor-uohm = <5000>;
+ };
+};
+
+This device node describes a current sense amplifier sitting on I2c4 bus
+with address 0x7c (read address is 0xf9, write address is 0xf8).
+A sense resistor of 0,005 Ohm is installed between RS+ and RS- current-sensing
+inputs.
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/4] iio: adc: Maxim max9611 driver
From: Jacopo Mondi @ 2017-03-24 15:28 UTC (permalink / raw)
To: geert-Td1EMuHUCqxL1ZNQvxDV9g,
wsa+renesas-jBu1N2QxHDJrcw3mvpCnnVaTQe2KTcn/,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w,
laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw,
jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hello!
Third round for Maxim max9611/max9612 high-side current sense amplifier driver.
For reference, a simplified integration schematic drawing is here reported:
----o----/\/\/-----o-------|LOAD|---
| shunt |
____|______________|___
| RS+ RS- |
| |-----gain-----| |
| | |
| | |
|max9611 |->| ADC |===== I2c
|______________________|
public datasheet available at
https://datasheets.maximintegrated.com/en/ds/MAX9611-MAX9612.pdf
In v2 all channels whose values are calculated using parameters
depending on the applied gain have been transformed in "processed" channels.
In v3 fixed DT bindings to use a more generic name for ADC nodes, and shunt
resistor description property.
output reported from iio_info tool:
iio:device0: max9611_vdd
6 channels found:
voltage0: (input)
1 channel-specific attributes found:
attr 0: input value: 4.085000000
voltage1: (input)
3 channel-specific attributes found:
attr 0: scale value: 14
attr 1: offset value: 1
attr 2: raw value: 59
shunt: (input)
2 channel-specific attributes found:
attr 0: resistor_power value: 5000
attr 1: resistor_current value: 5000
power: (input)
1 channel-specific attributes found:
attr 0: input value: 663.404000000
temp: (input)
2 channel-specific attributes found:
attr 0: scale value: 0.480076812
attr 1: raw value: 59
current: (input)
1 channel-specific attributes found:
attr 0: input value: 817.000000000
Tested on Salvator-X M3-W board.
Thanks
j
v1 -> v2:
- Drop wildcard (max961x) in driver, documentation and dt-bindings. Use
max9611 instead.
- Make 3 processed channels for csa voltage, csa current and power load
- Remove wrapper functions around i2c buffer access
- Add locking in read_raw()
- Make 2 separate attributes for shunt resistor: current and power
- Renamed shunt resistor attribute
- Fixed several review comments
v2 -> v3:
- Incorporated Geert's suggestions on using a more generic name for ADC nodes
in device tree
- Changed "maxim,shunt-resistor-uohm" to "shunt-resistor-uohm"
- Update documentation accordingly to the two previous changes
Jacopo Mondi (4):
Documentation: dt-bindings: iio: Add max9611 ADC
iio: Documentation: Add max9611 sysfs documentation
iio: adc: Add Maxim max9611 ADC driver
arm64: dts: salvator-x: Add current sense amplifiers
.../ABI/testing/sysfs-bus-iio-adc-max9611 | 16 +
.../devicetree/bindings/iio/adc/max9611.txt | 26 +
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 18 +
drivers/iio/adc/Kconfig | 10 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/max9611.c | 590 +++++++++++++++++++++
6 files changed, 661 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-max9611
create mode 100644 Documentation/devicetree/bindings/iio/adc/max9611.txt
create mode 100644 drivers/iio/adc/max9611.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH] ASoC: Add support for Maxim Integrated MAX98927 Amplifier
From: Rob Herring @ 2017-03-24 15:26 UTC (permalink / raw)
To: Ryan Lee
Cc: mark.rutland, alsa-devel, kuninori.morimoto.gx, lgirdwood, tiwai,
srinivas.kandagatla, romain.perier, bardliao, lars, axel.lin,
Paul.Handrigan, devicetree, arnd, nh6z, broonie, ckeepax, dgreid,
oder_chiou, KCHSU0, linux-kernel, petr
In-Reply-To: <1489970423-29353-1-git-send-email-ryans.lee@maximintegrated.com>
On Mon, Mar 20, 2017 at 09:40:23AM +0900, Ryan Lee wrote:
> Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com>
> ---
> Resubmit the intial version of MAX98927 driver. Added all fixes into the initial patch.
>
> .../devicetree/bindings/sound/max98927.txt | 39 +
> sound/soc/codecs/Kconfig | 5 +
> sound/soc/codecs/Makefile | 2 +
> sound/soc/codecs/max98927.c | 1040 ++++++++++++++++++++
> sound/soc/codecs/max98927.h | 267 +++++
> 5 files changed, 1353 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/sound/max98927.txt
> mode change 100644 => 100755 sound/soc/codecs/Kconfig
> mode change 100644 => 100755 sound/soc/codecs/Makefile
> create mode 100755 sound/soc/codecs/max98927.c
> create mode 100755 sound/soc/codecs/max98927.h
>
> diff --git a/Documentation/devicetree/bindings/sound/max98927.txt b/Documentation/devicetree/bindings/sound/max98927.txt
> new file mode 100755
> index 0000000..d610879
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/max98927.txt
> @@ -0,0 +1,39 @@
> +max98927 audio CODEC
> +
> +This device supports I2C.
Can we combine this and the other max9892x bindings. They all look
similar.
> +
> +Required properties:
> +
> + - compatible : "maxim,max98927"
> +
> + - maxim,vmon-slot-no : slot number used to send voltage information
While vendor prefix is preferred, so is using the same property names.
Either use the existing names or deprecate the old ones in favor of
these.
> + or in inteleave mode this will be used as
> + interleave slot.
> + This property can be set to values from 0 to 15 for slot 0 to 15.
> + Default value is 0.
> +
> + - maxim,imon-slot-no : slot number used to send current information
> + This property can be set to values from 0 to 15 for slot 0 to 15.
> + Default value is 0.
> +
> + - maxim,interleave-mode : When using two MAX98927 in a system it is
> + possible to create ADC data that that will
> + overflow the frame size. Digital Audio Interleave
> + mode provides a means to output VMON and IMON data
> + from two devices on a single DOUT line when running
> + smaller frames sizes such as 32 BCLKS per LRCLK or
> + 48 BCLKS per LRCLK.
> + This property can be set to values from 0 to 1 for off and on.
> + Default value is 0.
> +
> + - reg : the I2C address of the device for I2C
> +
> +Example:
> +
> +codec: max98927@3a {
> + compatible = "maxim,max98927";
> + maxim,vmon-slot-no = <0>;
> + maxim,imon-slot-no = <1>;
> + maxim,interleave-mode = <0>;
> + reg = <0x3a>;
> +};
^ permalink raw reply
* Re: [PATCH 1/5] iio: xoadc: augment DT bindings a bit
From: Linus Walleij @ 2017-03-24 15:25 UTC (permalink / raw)
To: Rob Herring
Cc: Jonathan Cameron,
linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Bjorn Andersson,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20170324151235.cb73gokg26qy7fvc@rob-hp-laptop>
On Fri, Mar 24, 2017 at 4:12 PM, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Sat, Mar 18, 2017 at 02:33:58PM +0100, Linus Walleij wrote:
>> -- #address-cells: should be set to <1>
>> +- #address-cells: should be set to <2>, the first cell is the
>> + prescaler (on PM8058) or premux (on PM8921) with two valid bits
>> + so legal values are 0x00, 0x01 or 0x02. The second cell
>> + is the main analog mux setting (0x00..0x0f). The combination
>> + of prescaler/premux and analog mux uniquely addresses a hardware
>> + channel on all systems.
>
> 64-bits to describe 48 possible combinations... I'd just combine these
> into 1 cell.
That was what I did first but it becomes very unintuitive and
require translation using tables etc from the datasheets. You
have to shuffle and stuff bits to get that one cell value.
The addressing is really done in two steps:
premux -> mux -> channel
Example:
Premux 0x02
Mux 0x08
I guess I could of course put that into one cell using 4+4 bits
and form 0x28.
On the other hand, that is not how the hardware works, because
there premux/prescaler and analog mux are two separate things.
>> - reg: should contain the hardware channel number in the range
>> - 0 .. 0x0f (4 bits). The hardware only supports 16 channels.
>> + 0 .. 0xff (8 bits).
>> +
>> + On PM8058 the hardware only supports 16 channels, but we get the same
>> + channels repeating with its input divided down by 1 or 3. Channels 00,
>> + 10, 20, ... f0 are the raw values, 04, 14, 24 .. f4 are "unity" channels
>> + divided by 1, and 08, 18, 28 .. f8 are channels divided by 3. Bits 0
>> + and 1 of the channel index should always be 0.
>> +
>> + On PM8921 the hardware supports more than 16 channels through a complex
>> + routing matrix using a premux, so 00, 10, 20 .. f0 are the basic raw
>> + channels while another set of channels appear for 04, 14, 24 .. f4,
>> + and again some of the same channels appear again divided down by 3
>> + in 08, 18, 28 .. f8. Again bits 0 and 1 of the channel index should
>> + always be 0.
>
> Now I'm lost...
That is actually how it looks with the old scheme, which you are
kind of requesting that I use instead. In a way it's good that I left
the old documentation in there because it illustrates my problem
with what you request above: lots of "holes" in that address
space and very unituitive numbers.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v4 2/2] fpga: Add support for Xilinx LogiCORE PR Decoupler
From: Alan Tull @ 2017-03-24 15:23 UTC (permalink / raw)
To: Moritz Fischer
Cc: linux-fpga, Rob Herring, Mark Rutland, Greg Kroah-Hartman,
Michal Simek, Sören Brinkmann, linux-kernel,
devicetree@vger.kernel.org
In-Reply-To: <1490334216-31068-2-git-send-email-mdf@kernel.org>
On Fri, Mar 24, 2017 at 12:43 AM, Moritz Fischer <mdf@kernel.org> wrote:
> This adds support for the Xilinx LogiCORE PR Decoupler
> soft-ip that does decoupling of PR regions in the FPGA
> fabric during partial reconfiguration.
>
> Signed-off-by: Moritz Fischer <mdf@kernel.org>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Alan Tull <atull@kernel.org>
> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
> Cc: linux-kernel@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> Changes from v3:
> - Adressed build bot issues
>
> Changes from v2:
> - Added Michal's Signed-off-by
> - Added "xlnx,pr-decoupler" unversioned fallback
>
> Changes from v1:
> - Added Michal as Co-Author since I pulled in some of his code
> - Reworked clk handling in _remove()
> - Pulled in Michal's version of show_enable(), ditched priv->enabled
>
> ---
> drivers/fpga/Kconfig | 10 +++
> drivers/fpga/Makefile | 1 +
> drivers/fpga/xilinx-pr-decoupler.c | 161 +++++++++++++++++++++++++++++++++++++
> 3 files changed, 172 insertions(+)
> create mode 100644 drivers/fpga/xilinx-pr-decoupler.c
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2..6eabfbe 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -63,6 +63,16 @@ config ALTERA_FREEZE_BRIDGE
> isolate one region of the FPGA from the busses while that
> region is being reprogrammed.
>
> +config XILINX_PR_DECOUPLER
> + tristate "Xilinx LogiCORE PR Decoupler"
> + depends on FPGA_BRIDGE
> + depends on HAS_IOMEM
> + help
> + Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
> + The PR Decoupler exists in the FPGA fabric to isolate one
> + region of the FPGA from the busses while that region is
> + being reprogrammed during partial reconfig.
> +
> endif # FPGA
>
> endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bc..ba94b79 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
> obj-$(CONFIG_FPGA_BRIDGE) += fpga-bridge.o
> obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE) += altera-hps2fpga.o altera-fpga2sdram.o
> obj-$(CONFIG_ALTERA_FREEZE_BRIDGE) += altera-freeze-bridge.o
> +obj-$(CONFIG_XILINX_PR_DECOUPLER) += xilinx-pr-decoupler.o
>
> # High Level Interfaces
> obj-$(CONFIG_FPGA_REGION) += fpga-region.o
> diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
> new file mode 100644
> index 0000000..e359930
> --- /dev/null
> +++ b/drivers/fpga/xilinx-pr-decoupler.c
> @@ -0,0 +1,161 @@
> +/*
> + * Copyright (c) 2017, National Instruments Corp.
> + * Copyright (c) 2017, Xilix Inc
> + *
> + * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
> + * Decoupler IP Core.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/of_device.h>
> +#include <linux/module.h>
> +#include <linux/fpga/fpga-bridge.h>
> +
> +#define CTRL_CMD_DECOUPLE BIT(0)
> +#define CTRL_CMD_COUPLE 0
> +#define CTRL_OFFSET 0
> +
> +struct xlnx_pr_decoupler_data {
> + void __iomem *io_base;
> + struct clk *clk;
> +};
> +
> +static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
> + u32 offset, u32 val)
> +{
> + writel(val, d->io_base + offset);
> +}
> +
> +static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
> + u32 offset)
> +{
> + return readl(d->io_base + offset);
> +}
> +
> +static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
> +{
> + int err;
> + struct xlnx_pr_decoupler_data *priv = bridge->priv;
> +
> + err = clk_enable(priv->clk);
> + if (err)
> + return err;
> +
> + if (enable)
> + xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
> + else
> + xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
> +
> + clk_disable(priv->clk);
> +
> + return 0;
> +}
> +
> +static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
> +{
> + const struct xlnx_pr_decoupler_data *priv = bridge->priv;
> + u32 status;
> + int err;
> +
> + err = clk_enable(priv->clk);
> + if (err)
> + return err;
> +
> + status = readl(priv->io_base);
> +
> + clk_disable(priv->clk);
> +
> + return !status;
> +}
> +
> +static struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
> + .enable_set = xlnx_pr_decoupler_enable_set,
> + .enable_show = xlnx_pr_decoupler_enable_show,
> +};
> +
> +static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
> + { .compatible = "xlnx,pr-decoupler-1.00", },
> + { .compatible = "xlnx,pr-decoupler", },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
> +
> +static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
> +{
> + struct xlnx_pr_decoupler_data *priv;
> + int err;
> + struct resource *res;
> +
> + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->io_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(priv->io_base))
> + return PTR_ERR(priv->io_base);
> +
> + priv->clk = devm_clk_get(&pdev->dev, "aclk");
> + if (IS_ERR(priv->clk)) {
> + dev_err(&pdev->dev, "input clock not found\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + err = clk_prepare_enable(priv->clk);
> + if (err) {
> + dev_err(&pdev->dev, "unable to enable clock\n");
> + return err;
> + }
> +
> + clk_disable(priv->clk);
> +
> + err = fpga_bridge_register(&pdev->dev, "Xilinx PR Decoupler",
> + &xlnx_pr_decoupler_br_ops, priv);
> +
> + if (err) {
> + dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
> + clk_unprepare(priv->clk);
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
> +{
> + struct fpga_bridge *bridge = platform_get_drvdata(pdev);
> + struct xlnx_pr_decoupler_data *p = bridge->priv;
> +
> + fpga_bridge_unregister(&pdev->dev);
> +
> + clk_unprepare(p->clk);
> +
> + return 0;
> +}
> +
> +static struct platform_driver xlnx_pr_decoupler_driver = {
> + .probe = xlnx_pr_decoupler_probe,
> + .remove = xlnx_pr_decoupler_remove,
> + .driver = {
> + .name = "xlnx_pr_decoupler",
> + .of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
> + },
> +};
> +
> +module_platform_driver(xlnx_pr_decoupler_driver);
> +
> +MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
> +MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
> +MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v3 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler
From: Moritz Fischer @ 2017-03-24 15:23 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland, devicetree, gregkh, linux-fpga, Michal Simek,
linux-kernel, Moritz Fischer, Sören Brinkmann,
linux-arm-kernel
In-Reply-To: <20170324145908.aiijqixf5xcnkksa@rob-hp-laptop>
On Fri, Mar 24, 2017 at 09:59:08AM -0500, Rob Herring wrote:
> On Fri, Mar 17, 2017 at 01:11:12PM -0700, Moritz Fischer wrote:
> > This adds the binding documentation for the Xilinx LogiCORE PR
> > Decoupler soft core.
> >
> > Signed-off-by: Moritz Fischer <mdf@kernel.org>
> > Cc: Michal Simek <michal.simek@xilinx.com>
> > Cc: Sören Brinkmann <soren.brinkmann@xilinx.com>
> > Cc: linux-kernel@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
> > ---
> >
> > Changes from v2:
> > - Added refence to generic fpga-region bindings
> > - Fixed up reg property in example
> > - Added fallback to "xlnx,pr-decoupler" without version
> >
> > Changes from v1:
> > - Added clock names & clock to example
> > - Merged some of the description from Michal's version
> >
> > ---
> > .../bindings/fpga/xilinx-pr-decoupler.txt | 35 ++++++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> >
> > diff --git a/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> > new file mode 100644
> > index 0000000..16141bd
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
> > @@ -0,0 +1,35 @@
> > +Xilinx LogiCORE Partial Reconfig Decoupler Softcore
> > +
> > +The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
> > +decouplers / fpga bridges.
> > +The controller can decouple/disable the bridges which prevents signal
> > +changes from passing through the bridge. The controller can also
> > +couple / enable the bridges which allows traffic to pass through the
> > +bridge normally.
> > +
> > +The Driver supports only MMIO handling. A PR region can have multiple
> > +PR Decouples which can bhe handled independently or chaines via decouple/
>
> s/chaines/chains/
Fixed in v4.
> > +decouple_status signals.
> > +
> > +Required properties:
> > +- compatible : Should contain "xlnx,pr-decoupler-1.00"
> > +- regs : base address and size for decoupler module
> > +- clocks : input clock to IP
> > +- clock-names : should contain "aclk"
> > +
> > +Optional properties:
> > +- bridge-enable : 0 if driver should disable bridge at startup
> > + 1 if driver should enable bridge at startup
> > + Default is to leave bridge in current state.
>
> This is common and should move into a common doc. Maybe fpga-region.txt
> works?
Ok will add patch for that to v5 series.
Thanks for your feedback,
Moritz
^ permalink raw reply
* Re: [PATCH v2 2/2] ata: ahci: add support for DaVinci DM816 SATA controller
From: Bartosz Golaszewski @ 2017-03-24 15:22 UTC (permalink / raw)
To: Tejun Heo
Cc: linux-ide, Michael Turquette, Sergei Shtylyov, Kevin Hilman,
Neil Armstrong, Tony Lindgren, Rob Herring, Mark Rutland,
Patrick Titiano, linux-devicetree, LKML, Bartosz Golaszewski
In-Reply-To: <1489489491-14195-3-git-send-email-bgolaszewski@baylibre.com>
2017-03-14 12:04 GMT+01:00 Bartosz Golaszewski <bgolaszewski@baylibre.com>:
> This SATA controller is quite similar to the one present on the DA850
> SoC, but the PHY configuration is different and it supports two HBA
> ports.
>
> The IP suffers from the same PMP issue the DA850 does - if we enable
> PMP but don't use it - softreset fails. Appropriate workaround was
> implemented in this driver as well.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> drivers/ata/Kconfig | 9 +++
> drivers/ata/Makefile | 1 +
> drivers/ata/ahci_dm816.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 210 insertions(+)
> create mode 100644 drivers/ata/ahci_dm816.c
>
Hi Tejun,
the DT bindings have been acked by Rob Herring and Tony Lindgren has
picked up the arch/arm patches. If there are no objections, could you
merge this driver and DT bindings for 4.12?
Thanks,
Bartosz
^ permalink raw reply
* [PATCH v3 7/7] arm: dts: genmai: Add user led device nodes
From: Jacopo Mondi @ 2017-03-24 15:22 UTC (permalink / raw)
To: geert+renesas, laurent.pinchart, chris.brandt, linus.walleij,
robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, linux-gpio, devicetree, linux-kernel
In-Reply-To: <1490368934-12494-1-git-send-email-jacopo+renesas@jmondi.org>
Add device nodes for user leds on Genmai board.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r7s72100-genmai.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 30992b1..94b9ab7 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -11,6 +11,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
@@ -35,6 +36,19 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ leds {
+ status = "okay";
+ compatible = "gpio-leds";
+
+ led1 {
+ gpios = <&port4 10 GPIO_ACTIVE_LOW>;
+ };
+
+ led2 {
+ gpios = <&port4 11 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&pinctrl {
--
2.7.4
^ permalink raw reply related
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