* RE: [EXT] Re: [PATCH net v2 3/4] ARM: dts: imx: add ethernet stop mode property
From: Andy Duan @ 2020-05-25 15:39 UTC (permalink / raw)
To: Andrew Lunn
Cc: martin.fuzzey@flowbird.group, davem@davemloft.net,
netdev@vger.kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
devicetree@vger.kernel.org, kuba@kernel.org
In-Reply-To: <20200525135104.GB752669@lunn.ch>
From: Andrew Lunn <andrew@lunn.ch> Sent: Monday, May 25, 2020 9:51 PM
> On Mon, May 25, 2020 at 03:09:28PM +0800, fugang.duan@nxp.com wrote:
> > From: Fugang Duan <fugang.duan@nxp.com>
> >
> > - Update the imx6qdl gpr property to define gpr register
> > offset and bit in DT.
> > - Add imx6sx/imx6ul/imx7d ethernet stop mode property.
> >
> > Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
>
> Thanks for adding a user.
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
> Andrew
Andrew, thanks for your review.
^ permalink raw reply
* RE: [EXT] Re: [PATCH net v2 4/4] ARM: dts: imx6qdl-sabresd: enable fec wake-on-lan
From: Andy Duan @ 2020-05-25 15:40 UTC (permalink / raw)
To: Andrew Lunn
Cc: martin.fuzzey@flowbird.group, davem@davemloft.net,
netdev@vger.kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
devicetree@vger.kernel.org, kuba@kernel.org
In-Reply-To: <20200525135140.GC752669@lunn.ch>
From: Andrew Lunn <andrew@lunn.ch> Sent: Monday, May 25, 2020 9:52 PM
> On Mon, May 25, 2020 at 03:09:29PM +0800, fugang.duan@nxp.com wrote:
> > From: Fugang Duan <fugang.duan@nxp.com>
> >
> > Enable ethernet wake-on-lan feature for imx6q/dl/qp sabresd boards
> > since the PHY clock is supplied by exteranl osc.
>
> external
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
> Andrew
Andrew, thanks for your review.
Will send v3 by correct the typo.
^ permalink raw reply
* RE: [EXT] Re: [PATCH net v2 0/4] net: ethernet: fec: move GPR reigster offset and bit into DT
From: Andy Duan @ 2020-05-25 15:41 UTC (permalink / raw)
To: Andrew Lunn
Cc: martin.fuzzey@flowbird.group, davem@davemloft.net,
netdev@vger.kernel.org, robh+dt@kernel.org, shawnguo@kernel.org,
devicetree@vger.kernel.org, kuba@kernel.org
In-Reply-To: <20200525135433.GD752669@lunn.ch>
From: Andrew Lunn <andrew@lunn.ch> Sent: Monday, May 25, 2020 9:55 PM
> On Mon, May 25, 2020 at 03:09:25PM +0800, fugang.duan@nxp.com wrote:
> > From: Fugang Duan <fugang.duan@nxp.com>
> >
> > The commit da722186f654 (net: fec: set GPR bit on suspend by DT
> configuration) set the GPR reigster offset and bit in driver for wol feature.
>
> The cover letter gets committed as the merge commit message. So please
> wrap long longs.
>
> > It bring trouble to enable wol feature on imx6sx/imx6ul/imx7d
> > platforms that have multiple ethernet instances with different GPR bit
> > for stop mode control. So the patch set is to move GPR reigster
>
> register
>
Got it, will correct the typo in v3.
> > offset and bit define into DT, and enable
> > imx6q/imx6dl/imx6sx/imx6ul/imx7d stop mode support.
>
>
> >
> > Currently, below NXP i.MX boards support wol:
> > - imx6q/imx6dl sabresd
> > - imx6sx sabreauto
> > - imx7d sdb
> >
> > imx6q/imx6dl sarebsd board dts file miss the property "fsl,magic-packet;",
> so patch#4 is to add the property for stop mode support.
>
> sabresd?
>
> Andrew
Thanks, I will correct the typo in v3.
^ permalink raw reply
* Re: [PATCHv3 2/2] dt-bindings: arm: coresight: Add optional property to replicators
From: Mathieu Poirier @ 2020-05-25 16:01 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Suzuki K Poulose, Mike Leach, devicetree, Rob Herring,
linux-arm-kernel, Linux Kernel Mailing List, linux-arm-msm,
Stephen Boyd
In-Reply-To: <ccfe8a5ede0523436508e31085322ccdab8f972a.1590171891.git.saiprakash.ranjan@codeaurora.org>
On Fri, 22 May 2020 at 12:37, Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Add an optional boolean property "qcom,replicator-loses-context" to
> identify replicators which loses context when AMBA clocks are removed
> in certain configurable replicator designs.
>
> Reviewed-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/coresight.txt | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 846f6daae71b..b598a5f0037d 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -121,6 +121,12 @@ its hardware characteristcs.
> * interrupts : Exactly one SPI may be listed for reporting the address
> error
>
> +* Optional property for configurable replicators:
> +
> + * qcom,replicator-loses-context: boolean. Indicates that the replicator
> + will lose register context when AMBA clock is removed which is observed
> + in some replicator designs.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> +
> Graph bindings for Coresight
> -------------------------------
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply
* Re: [PATCHv3 0/2] Add support for replicators which loses context on clock removal
From: Mathieu Poirier @ 2020-05-25 16:15 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Suzuki K Poulose, Mike Leach, devicetree, Rob Herring,
linux-arm-kernel, linux-kernel, linux-arm-msm, Stephen Boyd
In-Reply-To: <cover.1590171891.git.saiprakash.ranjan@codeaurora.org>
Hi Sai,
On Sat, May 23, 2020 at 12:06:50AM +0530, Sai Prakash Ranjan wrote:
> This series is mainly to add support for replicators
> which lose context on removing AMBA clock like on SC7180
> SoC where replicator in AOSS domain loses context.
>
I am good with this set but need a reviewed-by on the DT binding before I can
add it to my tree. The same goes for your other set[1].
Thanks,
Mathieu
[1]. "coresight: etm4x: Add support to skip trace unit power up"
> v2 - https://lore.kernel.org/patchwork/cover/1244340/
> More discussion is found here - https://lore.kernel.org/patchwork/patch/1231182/
>
> Changes since v2:
> * Added DT maintainers which I missed in v2
> * Added proper kernel-doc and header as per Mathieu
>
> Sai Prakash Ranjan (2):
> coresight: replicator: Reset replicator if context is lost
> dt-bindings: arm: coresight: Add optional property to replicators
>
> .../devicetree/bindings/arm/coresight.txt | 6 ++
> .../coresight/coresight-replicator.c | 55 +++++++++++++------
> 2 files changed, 44 insertions(+), 17 deletions(-)
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply
* [PATCH net v3 0/4] net: ethernet: fec: move GPR reigster offset and bit into DT
From: fugang.duan @ 2020-05-25 16:27 UTC (permalink / raw)
To: andrew, martin.fuzzey, davem, s.hauer
Cc: netdev, robh+dt, shawnguo, devicetree, kuba, fugang.duan
From: Fugang Duan <fugang.duan@nxp.com>
The commit da722186f654 (net: fec: set GPR bit on suspend by
DT configuration) set the GPR reigster offset and bit in driver
for wol feature support.
It brings trouble to enable wol feature on imx6sx/imx6ul/imx7d
platforms that have multiple ethernet instances with different
GPR bit for stop mode control. So the patch set is to move GPR
register offset and bit define into DT, and enable imx6q/imx6dl
imx6qp/imx6sx/imx6ul/imx7d stop mode support.
Currently, below NXP i.MX boards support wol:
- imx6q/imx6dl/imx6qp sabresd
- imx6sx sabreauto
- imx7d sdb
imx6q/imx6dl/imx6qp sabresd board dts file miss the property
"fsl,magic-packet;", so patch#4 is to add the property for stop
mode support.
v1 -> v2:
- driver: switch back to store the quirks bitmask in driver_data
- dt-bindings: rename 'gpr' property string to 'fsl,stop-mode'
- imx6/7 dtsi: add imx6sx/imx6ul/imx7d ethernet stop mode property
v2 -> v3:
- driver: suggested by Sascha Hauer, use a struct fec_devinfo for
abstracting differences between different hardware variants,
it can give more freedom to describe the differences.
- imx6/7 dtsi: correct one typo pointed out by Andrew.
Thanks Martin, Andrew and Sascha Hauer for the review.
Fugang Duan (4):
net: ethernet: fec: move GPR register offset and bit into DT
dt-bindings: fec: update the gpr property
ARM: dts: imx: add ethernet stop mode property
ARM: dts: imx6qdl-sabresd: enable fec wake-on-lan
Documentation/devicetree/bindings/net/fsl-fec.txt | 7 +++++--
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 +
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
arch/arm/boot/dts/imx6sx.dtsi | 2 ++
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
arch/arm/boot/dts/imx7d.dtsi | 1 +
arch/arm/boot/dts/imx7s.dtsi | 1 +
drivers/net/ethernet/freescale/fec_main.c | 24 +++++++++++------------
8 files changed, 25 insertions(+), 15 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH net v3 1/4] net: ethernet: fec: move GPR register offset and bit into DT
From: fugang.duan @ 2020-05-25 16:27 UTC (permalink / raw)
To: andrew, martin.fuzzey, davem, s.hauer
Cc: netdev, robh+dt, shawnguo, devicetree, kuba, fugang.duan
In-Reply-To: <1590424033-16906-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
The commit da722186f654 (net: fec: set GPR bit on suspend by DT
configuration) set the GPR reigster offset and bit in driver for
wake on lan feature.
But it introduces two issues here:
- one SOC has two instances, they have different bit
- different SOCs may have different offset and bit
So to support wake-on-lan feature on other i.MX platforms, it should
configure the GPR reigster offset and bit from DT.
So the patch is to improve the commit da722186f654 (net: fec: set GPR
bit on suspend by DT configuration) to support multiple ethernet
instances on i.MX series.
v2:
* switch back to store the quirks bitmask in driver_data
v3:
* suggested by Sascha Hauer, use a struct fec_devinfo for
abstracting differences between different hardware variants,
it can give more freedom to describe the differences.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
drivers/net/ethernet/freescale/fec_main.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 2e20914..4acb91d 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -88,8 +88,6 @@ static void fec_enet_itr_coal_init(struct net_device *ndev);
struct fec_devinfo {
u32 quirks;
- u8 stop_gpr_reg;
- u8 stop_gpr_bit;
};
static const struct fec_devinfo fec_imx25_info = {
@@ -112,8 +110,6 @@ static const struct fec_devinfo fec_imx6q_info = {
FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
FEC_QUIRK_HAS_RACC,
- .stop_gpr_reg = 0x34,
- .stop_gpr_bit = 27,
};
static const struct fec_devinfo fec_mvf600_info = {
@@ -3476,19 +3472,23 @@ static int fec_enet_get_irq_cnt(struct platform_device *pdev)
}
static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
- struct fec_devinfo *dev_info,
struct device_node *np)
{
struct device_node *gpr_np;
+ u32 out_val[3];
int ret = 0;
- if (!dev_info)
- return 0;
-
- gpr_np = of_parse_phandle(np, "gpr", 0);
+ gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
if (!gpr_np)
return 0;
+ ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
+ ARRAY_SIZE(out_val));
+ if (ret) {
+ dev_dbg(&fep->pdev->dev, "no stop mode property\n");
+ return ret;
+ }
+
fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
if (IS_ERR(fep->stop_gpr.gpr)) {
dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
@@ -3497,8 +3497,8 @@ static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
goto out;
}
- fep->stop_gpr.reg = dev_info->stop_gpr_reg;
- fep->stop_gpr.bit = dev_info->stop_gpr_bit;
+ fep->stop_gpr.reg = out_val[1];
+ fep->stop_gpr.bit = out_val[2];
out:
of_node_put(gpr_np);
@@ -3575,7 +3575,7 @@ fec_probe(struct platform_device *pdev)
if (of_get_property(np, "fsl,magic-packet", NULL))
fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
- ret = fec_enet_init_stop_mode(fep, dev_info, np);
+ ret = fec_enet_init_stop_mode(fep, np);
if (ret)
goto failed_stop_mode;
--
2.7.4
^ permalink raw reply related
* [PATCH net v3 2/4] dt-bindings: fec: update the gpr property
From: fugang.duan @ 2020-05-25 16:27 UTC (permalink / raw)
To: andrew, martin.fuzzey, davem, s.hauer
Cc: netdev, robh+dt, shawnguo, devicetree, kuba, fugang.duan
In-Reply-To: <1590424033-16906-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
- rename the 'gpr' property string to 'fsl,stop-mode'.
- Update the property to define gpr register offset and
bit in DT, since different instance have different gpr bit.
v2:
* rename 'gpr' property string to 'fsl,stop-mode'.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
Documentation/devicetree/bindings/net/fsl-fec.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt
index 26c492a..9b54378 100644
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@@ -22,8 +22,11 @@ Optional properties:
- fsl,err006687-workaround-present: If present indicates that the system has
the hardware workaround for ERR006687 applied and does not need a software
workaround.
-- gpr: phandle of SoC general purpose register mode. Required for wake on LAN
- on some SoCs
+- fsl,stop-mode: register bits of stop mode control, the format is
+ <&gpr req_gpr req_bit>.
+ gpr is the phandle to general purpose register node.
+ req_gpr is the gpr register offset for ENET stop request.
+ req_bit is the gpr bit offset for ENET stop request.
-interrupt-names: names of the interrupts listed in interrupts property in
the same order. The defaults if not specified are
__Number of interrupts__ __Default__
--
2.7.4
^ permalink raw reply related
* [PATCH net v3 3/4] ARM: dts: imx: add ethernet stop mode property
From: fugang.duan @ 2020-05-25 16:27 UTC (permalink / raw)
To: andrew, martin.fuzzey, davem, s.hauer
Cc: netdev, robh+dt, shawnguo, devicetree, kuba, fugang.duan
In-Reply-To: <1590424033-16906-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
- Update the imx6qdl gpr property to define gpr register
offset and bit in DT.
- Add imx6sx/imx6ul/imx7d ethernet stop mode property.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 2 +-
arch/arm/boot/dts/imx6sx.dtsi | 2 ++
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
arch/arm/boot/dts/imx7d.dtsi | 1 +
arch/arm/boot/dts/imx7s.dtsi | 1 +
5 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 98da446..48f5016 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1045,7 +1045,7 @@
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp";
- gpr = <&gpr>;
+ fsl,stop-mode = <&gpr 0x34 27>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index d6f8317..09f21aa 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -930,6 +930,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
@@ -1039,6 +1040,7 @@
<&clks IMX6SX_CLK_ENET_PTP>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2ccf67c..345ae9b 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -520,6 +520,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
@@ -856,6 +857,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <1>;
fsl,num-rx-queues = <1>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 4c22828..cff875b 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -153,6 +153,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 4>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 76e3ffb..5bf0b39 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1190,6 +1190,7 @@
"enet_clk_ref", "enet_out";
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
+ fsl,stop-mode = <&gpr 0x10 3>;
status = "disabled";
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH net v3 4/4] ARM: dts: imx6qdl-sabresd: enable fec wake-on-lan
From: fugang.duan @ 2020-05-25 16:27 UTC (permalink / raw)
To: andrew, martin.fuzzey, davem, s.hauer
Cc: netdev, robh+dt, shawnguo, devicetree, kuba, fugang.duan
In-Reply-To: <1590424033-16906-1-git-send-email-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Enable ethernet wake-on-lan feature for imx6q/dl/qp sabresd
boards since the PHY clock is supplied by external osc.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index fe59dde..28b35cc 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -204,6 +204,7 @@
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [PATCH v4 0/5] iio: imu: bmi160: added regulator and mount-matrix support
From: Jonathan Albrieux @ 2020-05-25 16:45 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler
v4:
- add maintainer
- clean up of documentation
- added case concerning the need to add regulators, see [PATCH v4 4/5]
v3:
- separate typo fix into another patch
- clean up of documentation
- clean up of patch messages
https://lore.kernel.org/linux-iio/20200520194656.16218-1-jonathan.albrieux@gmail.com/
v2:
- fixed missing description for iio: imu: bmi160: added regulator
support
https://lore.kernel.org/linux-iio/20200519075111.6356-1-jonathan.albrieux@gmail.com/
v1:
- initial patch submission
https://lore.kernel.org/linux-iio/20200518133358.18978-1-jonathan.albrieux@gmail.com/
Convert txt format documentation to yaml.
Add documentation about vdd-supply, vddio-supply and mount-matrix.
Add vdd-supply and vddio-supply support.
Add mount-matrix binding support. As chip could have different
orientations a mount matrix support is needed to correctly translate
these differences.
Jonathan Albrieux (5):
dt-bindings: iio: imu: bmi160: convert format to yaml, add maintainer
dt-bindings: iio: imu: bmi160: add regulators and mount-matrix
iio: imu: bmi160: fix typo
iio: imu: bmi160: added regulator support
iio: imu: bmi160: added mount-matrix support
.../devicetree/bindings/iio/imu/bmi160.txt | 37 --------
.../bindings/iio/imu/bosch,bmi160.yaml | 91 +++++++++++++++++++
drivers/iio/imu/bmi160/bmi160.h | 3 +
drivers/iio/imu/bmi160/bmi160_core.c | 46 +++++++++-
4 files changed, 139 insertions(+), 38 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
create mode 100644 Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
--
2.17.1
^ permalink raw reply
* [PATCH v4 1/5] dt-bindings: iio: imu: bmi160: convert format to yaml, add maintainer
From: Jonathan Albrieux @ 2020-05-25 16:46 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron, Rob Herring
In-Reply-To: <20200525164615.14962-1-jonathan.albrieux@gmail.com>
Converts documentation from txt format to yaml.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
.../devicetree/bindings/iio/imu/bmi160.txt | 37 ---------
.../bindings/iio/imu/bosch,bmi160.yaml | 75 +++++++++++++++++++
2 files changed, 75 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
create mode 100644 Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
deleted file mode 100644
index 900c169de00f..000000000000
--- a/Documentation/devicetree/bindings/iio/imu/bmi160.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
-and externally connectable Magnetometer
-
-https://www.bosch-sensortec.com/bst/products/all_products/bmi160
-
-Required properties:
- - compatible : should be "bosch,bmi160"
- - reg : the I2C address or SPI chip select number of the sensor
- - spi-max-frequency : set maximum clock frequency (only for SPI)
-
-Optional properties:
- - interrupts : interrupt mapping for IRQ
- - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
- input, set to "INT2" if INT2 pin should be used instead
- - drive-open-drain : set if the specified interrupt pin should be configured as
- open drain. If not set, defaults to push-pull.
-
-Examples:
-
-bmi160@68 {
- compatible = "bosch,bmi160";
- reg = <0x68>;
-
- interrupt-parent = <&gpio4>;
- interrupts = <12 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "INT1";
-};
-
-bmi160@0 {
- compatible = "bosch,bmi160";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- interrupt-parent = <&gpio2>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT2";
-};
diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
new file mode 100644
index 000000000000..0d0ef84e22b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/bosch,bmi160.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMI160
+
+maintainers:
+ - Jonathan Cameron <jic23@kernel.org>
+
+description: |
+ Inertial Measurement Unit with Accelerometer, Gyroscope and externally
+ connectable Magnetometer
+ https://www.bosch-sensortec.com/bst/products/all_products/bmi160
+
+properties:
+ compatible:
+ const: bosch,bmi160
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ enum:
+ - INT1
+ - INT2
+ description: |
+ set to "INT1" if INT1 pin should be used as interrupt input, set
+ to "INT2" if INT2 pin should be used instead
+
+ drive-open-drain:
+ description: |
+ set if the specified interrupt pin should be configured as
+ open drain. If not set, defaults to push-pull.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ // Example for I2C
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bmi160@68 {
+ compatible = "bosch,bmi160";
+ reg = <0x68>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "INT1";
+ };
+ };
+ - |
+ // Example for SPI
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bmi160@0 {
+ compatible = "bosch,bmi160";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "INT2";
+ };
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v4 3/5] iio: imu: bmi160: fix typo
From: Jonathan Albrieux @ 2020-05-25 16:46 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron
In-Reply-To: <20200525164615.14962-1-jonathan.albrieux@gmail.com>
Fix a typo in MODULE_AUTHOR() argument.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
drivers/iio/imu/bmi160/bmi160_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index 6af65d6f1d28..77b05bd4a2b2 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -853,6 +853,6 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
}
EXPORT_SYMBOL_GPL(bmi160_core_probe);
-MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
+MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
MODULE_DESCRIPTION("Bosch BMI160 driver");
MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related
* [PATCH v4 2/5] dt-bindings: iio: imu: bmi160: add regulators and mount-matrix
From: Jonathan Albrieux @ 2020-05-25 16:46 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron, Rob Herring
In-Reply-To: <20200525164615.14962-1-jonathan.albrieux@gmail.com>
Add vdd-supply and vddio-supply support.
Add mount-matrix support.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
.../bindings/iio/imu/bosch,bmi160.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
index 0d0ef84e22b9..cfe40dbcd723 100644
--- a/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/bosch,bmi160.yaml
@@ -37,6 +37,17 @@ properties:
set if the specified interrupt pin should be configured as
open drain. If not set, defaults to push-pull.
+ vdd-supply:
+ maxItems: 1
+ description: provide VDD power to the sensor.
+
+ vddio-supply:
+ maxItems: 1
+ description: provide VDD IO power to the sensor.
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix
+
required:
- compatible
- reg
@@ -52,9 +63,14 @@ examples:
bmi160@68 {
compatible = "bosch,bmi160";
reg = <0x68>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
interrupt-parent = <&gpio4>;
interrupts = <12 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "INT1";
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
};
};
- |
--
2.17.1
^ permalink raw reply related
* [PATCH v4 4/5] iio: imu: bmi160: added regulator support
From: Jonathan Albrieux @ 2020-05-25 16:46 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron
In-Reply-To: <20200525164615.14962-1-jonathan.albrieux@gmail.com>
Add vdd-supply and vddio-supply support.
While working on an msm8916 device and having explicit declarations for
regulators, without setting these regulators to regulators-always-on it
happened those lines weren't ready because they could have been controlled
by other components, causing failure in module's probe.
This patch aim is to solve this situation by adding regulators control
during bmi160_chip_init() and bmi160_chip_uninit(), assuring power to
this component.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
drivers/iio/imu/bmi160/bmi160.h | 2 ++
drivers/iio/imu/bmi160/bmi160_core.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
index 621f5309d735..923c3b274fde 100644
--- a/drivers/iio/imu/bmi160/bmi160.h
+++ b/drivers/iio/imu/bmi160/bmi160.h
@@ -3,10 +3,12 @@
#define BMI160_H_
#include <linux/iio/iio.h>
+#include <linux/regulator/consumer.h>
struct bmi160_data {
struct regmap *regmap;
struct iio_trigger *trig;
+ struct regulator_bulk_data supplies[2];
};
extern const struct regmap_config bmi160_regmap_config;
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index 77b05bd4a2b2..d3316ca02fbd 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
+#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
@@ -709,6 +710,12 @@ static int bmi160_chip_init(struct bmi160_data *data, bool use_spi)
unsigned int val;
struct device *dev = regmap_get_device(data->regmap);
+ ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET);
if (ret)
return ret;
@@ -793,9 +800,16 @@ int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type)
static void bmi160_chip_uninit(void *data)
{
struct bmi160_data *bmi_data = data;
+ struct device *dev = regmap_get_device(bmi_data->regmap);
+ int ret;
bmi160_set_mode(bmi_data, BMI160_GYRO, false);
bmi160_set_mode(bmi_data, BMI160_ACCEL, false);
+
+ ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies),
+ bmi_data->supplies);
+ if (ret)
+ dev_err(dev, "Failed to disable regulators: %d\n", ret);
}
int bmi160_core_probe(struct device *dev, struct regmap *regmap,
@@ -815,6 +829,16 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
dev_set_drvdata(dev, indio_dev);
data->regmap = regmap;
+ data->supplies[0].supply = "vdd";
+ data->supplies[1].supply = "vddio";
+ ret = devm_regulator_bulk_get(dev,
+ ARRAY_SIZE(data->supplies),
+ data->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
ret = bmi160_chip_init(data, use_spi);
if (ret)
return ret;
--
2.17.1
^ permalink raw reply related
* [PATCH v4 5/5] iio: imu: bmi160: added mount-matrix support
From: Jonathan Albrieux @ 2020-05-25 16:46 UTC (permalink / raw)
To: linux-kernel
Cc: ~postmarketos/upstreaming, daniel.baluta, Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron
In-Reply-To: <20200525164615.14962-1-jonathan.albrieux@gmail.com>
Add mount-matrix binding support. As chip could have different orientations
a mount matrix support is needed to correctly translate these differences.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
drivers/iio/imu/bmi160/bmi160.h | 1 +
drivers/iio/imu/bmi160/bmi160_core.c | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
index 923c3b274fde..a82e040bd109 100644
--- a/drivers/iio/imu/bmi160/bmi160.h
+++ b/drivers/iio/imu/bmi160/bmi160.h
@@ -9,6 +9,7 @@ struct bmi160_data {
struct regmap *regmap;
struct iio_trigger *trig;
struct regulator_bulk_data supplies[2];
+ struct iio_mount_matrix orientation;
};
extern const struct regmap_config bmi160_regmap_config;
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index d3316ca02fbd..26d586daee26 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -110,6 +110,7 @@
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
+ .ext_info = bmi160_ext_info, \
}
/* scan indexes follow DATA register order */
@@ -265,6 +266,20 @@ static const struct bmi160_odr_item bmi160_odr_table[] = {
},
};
+static const struct iio_mount_matrix *
+bmi160_get_mount_matrix(const struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+
+ return &data->orientation;
+}
+
+static const struct iio_chan_spec_ext_info bmi160_ext_info[] = {
+ IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix),
+ { }
+};
+
static const struct iio_chan_spec bmi160_channels[] = {
BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X),
BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y),
@@ -839,6 +854,11 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
return ret;
}
+ ret = iio_read_mount_matrix(dev, "mount-matrix",
+ &data->orientation);
+ if (ret)
+ return ret;
+
ret = bmi160_chip_init(data, use_spi);
if (ret)
return ret;
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v3 03/16] mfd: mfd-core: match device tree node against reg property
From: Michael Walle @ 2020-05-25 17:36 UTC (permalink / raw)
To: Lee Jones
Cc: Andy Shevchenko, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Jean Delvare, Guenter Roeck, Thierry Reding,
Uwe Kleine-König, Wim Van Sebroeck, Shawn Guo, Li Yang,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Mark Brown,
Greg Kroah-Hartman, linux-gpio, devicetree, linux-kernel,
linux-hwmon, linux-pwm, linux-watchdog, linux-arm-kernel
In-Reply-To: <20200515102848.GH271301@dell>
Am 2020-05-15 12:28, schrieb Lee Jones:
> On Thu, 30 Apr 2020, Michael Walle wrote:
>
>> Hi Lee,
>>
>> Am 2020-04-23 19:45, schrieb Michael Walle:
>> > There might be multiple children with the device tree compatible, for
>> > example if a MFD has multiple instances of the same function. In this
>> > case only the first is matched and the other children get a wrong
>> > of_node reference.
>> > Add a new option to match also against the unit address of the child
>> > node. Additonally, a new helper OF_MFD_CELL_REG is added.
>>
>>
>> Do you think this is feasible? I guess this is the biggest uncertainty
>> for me at the moment in this patch series.
>
> I think it sounds fine in principle. So long as it doesn't change the
> existing behaviour when of_reg isn't set.
>
>> > Signed-off-by: Michael Walle <michael@walle.cc>
>> > ---
>> > drivers/mfd/mfd-core.c | 29 ++++++++++++++++++++---------
>> > include/linux/mfd/core.h | 26 ++++++++++++++++++++------
>> > 2 files changed, 40 insertions(+), 15 deletions(-)
>> >
>> > diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
>> > index e735565969b3..4ecb376338f7 100644
>> > --- a/drivers/mfd/mfd-core.c
>> > +++ b/drivers/mfd/mfd-core.c
>> > @@ -117,6 +117,7 @@ static int mfd_add_device(struct device *parent, int
>> > id,
>> > struct device_node *np = NULL;
>> > int ret = -ENOMEM;
>> > int platform_id;
>> > + u32 of_reg;
>> > int r;
>> >
>> > if (id == PLATFORM_DEVID_AUTO)
>> > @@ -151,16 +152,26 @@ static int mfd_add_device(struct device *parent,
>> > int id,
>> >
>> > if (parent->of_node && cell->of_compatible) {
>> > for_each_child_of_node(parent->of_node, np) {
>> > - if (of_device_is_compatible(np, cell->of_compatible)) {
>> > - if (!of_device_is_available(np)) {
>> > - /* Ignore disabled devices error free */
>> > - ret = 0;
>> > - goto fail_alias;
>> > - }
>> > - pdev->dev.of_node = np;
>> > - pdev->dev.fwnode = &np->fwnode;
>> > - break;
>> > + if (!of_device_is_compatible(np, cell->of_compatible))
>> > + continue;
>> > +
>> > + /* also match the unit address if set */
>
> Please use correct grammar in comments (leaving off the full-stop).
>
>> > + if (cell->of_reg & MFD_OF_REG_VALID) {
>> > + if (of_property_read_u32(np, "reg", &of_reg))
>> > + continue;
>> > + if ((cell->of_reg & MFD_OF_REG_MASK) != of_reg)
>> > + continue;
>> > }
>> > +
>> > + if (!of_device_is_available(np)) {
>> > + /* Ignore disabled devices error free */
>> > + ret = 0;
>> > + goto fail_alias;
>> > + }
>> > +
>> > + pdev->dev.of_node = np;
>> > + pdev->dev.fwnode = &np->fwnode;
>> > + break;
>> > }
>> > }
>> >
>> > diff --git a/include/linux/mfd/core.h b/include/linux/mfd/core.h
>> > index d01d1299e49d..c2c0ad6b14f3 100644
>> > --- a/include/linux/mfd/core.h
>> > +++ b/include/linux/mfd/core.h
>> > @@ -13,8 +13,11 @@
>> > #include <linux/platform_device.h>
>> >
>> > #define MFD_RES_SIZE(arr) (sizeof(arr) / sizeof(struct resource))
>> > +#define MFD_OF_REG_VALID BIT(31)
>
> What about 64bit platforms?
The idea was to have this as a logical number. I.e. for now you may only
have one subdevice per unique compatible string. In fact, if you have a
look at the ab8500.c, there are multiple "stericsson,ab8500-pwm"
subdevices. But there is only one DT node for all three of it. I guess
this works as long as you don't use phandles to reference the pwm node
in the device tree. Or you don't want to use device tree properties
per subdevice (for example the "timeout-sec" of a watchdog device).
So to circumvent this, I thought of having the unit-address (and thus
the "reg" property) to differentiate between multiple subdevices. Now
there is one special case for me: this board management controller
might be upgradable and it might change internally. Thus I came up
with that logical numbering of subdevices. Rob doesn't seem to be a
fan of that, though. Therefore, having bit 31 as a valid indicator
leaves you with 2^31 logical devices, which should be enough ;)
Rob proposed to have the internal offset as the unit-address. But
in that case I can also use devm_of_platform_populate() and don't
need the OF_MFD_CELL_REG; I'd just parse the reg offset in each
individual subdevice driver. But like I said, I wanted to keep the
internal offsets out of the device tree.
-michael
>
>> > +#define MFD_OF_REG_MASK GENMASK(30, 0)
>> >
>> > -#define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat,
>> > _match)\
>> > +#define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, \
>> > + _of_reg, _match) \
>> > { \
>> > .name = (_name), \
>> > .resources = (_res), \
>> > @@ -22,24 +25,32 @@
>> > .platform_data = (_pdata), \
>> > .pdata_size = (_pdsize), \
>> > .of_compatible = (_compat), \
>> > + .of_reg = (_of_reg), \
>> > .acpi_match = (_match), \
>> > .id = (_id), \
>> > }
>> >
>> > +#define OF_MFD_CELL_REG(_name, _res, _pdata, _pdsize, _id, _compat, \
>> > + _of_reg) \
>> > + MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, \
>> > + ((_of_reg) | MFD_OF_REG_VALID), NULL) \
>> > +
>> > #define OF_MFD_CELL(_name, _res, _pdata, _pdsize,_id, _compat) \
>> > - MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, NULL) \
>> > + MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, \
>> > + 0, NULL) \
>> >
>> > #define ACPI_MFD_CELL(_name, _res, _pdata, _pdsize, _id, _match) \
>> > - MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, _match) \
>> > + MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, \
>> > + _match) \
>> >
>> > #define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \
>> > - MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, NULL) \
>> > + MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, NULL, 0, NULL) \
>> >
>> > #define MFD_CELL_RES(_name, _res) \
>> > - MFD_CELL_ALL(_name, _res, NULL, 0, 0, NULL, NULL) \
>> > + MFD_CELL_ALL(_name, _res, NULL, 0, 0, NULL, 0, NULL) \
>> >
>> > #define MFD_CELL_NAME(_name) \
>> > - MFD_CELL_ALL(_name, NULL, NULL, 0, 0, NULL, NULL) \
>> > + MFD_CELL_ALL(_name, NULL, NULL, 0, 0, NULL, 0, NULL) \
>> >
>> > struct irq_domain;
>> > struct property_entry;
>> > @@ -78,6 +89,9 @@ struct mfd_cell {
>> > */
>> > const char *of_compatible;
>> >
>> > + /* matching the reg property if set */
>
> Proper grammar please.
>
> "OF unit address for device matching"
>
>> > + unsigned int of_reg;
>> > +
>> > /* Matches ACPI */
>> > const struct mfd_cell_acpi_match *acpi_match;
^ permalink raw reply
* [PATCH 1/3] MIPS: ingenic: DTS: Add memory info of GCW Zero
From: Paul Cercueil @ 2020-05-25 17:41 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: od, devicetree, linux-mips, linux-kernel, Paul Cercueil
Add memory info of the GCW Zero in its devicetree. The bootloader
generally provides this information, but since it is fixed to 512 MiB,
it doesn't hurt to have it in devicetree. It allows the kernel to boot
without any parameter passed as argument.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/gcw0.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/mips/boot/dts/ingenic/gcw0.dts b/arch/mips/boot/dts/ingenic/gcw0.dts
index c2396b5ca175..8d22828787d8 100644
--- a/arch/mips/boot/dts/ingenic/gcw0.dts
+++ b/arch/mips/boot/dts/ingenic/gcw0.dts
@@ -19,6 +19,12 @@ aliases {
serial3 = &uart3;
};
+ memory: memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>,
+ <0x30000000 0x10000000>;
+ };
+
chosen {
stdout-path = "serial2:57600n8";
};
--
2.26.2
^ permalink raw reply related
* [PATCH 2/3] MIPS: ingenic: Add support for GCW Zero prototype
From: Paul Cercueil @ 2020-05-25 17:41 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: od, devicetree, linux-mips, linux-kernel, Paul Cercueil
In-Reply-To: <20200525174155.457491-1-paul@crapouillou.net>
Add support for the GCW Zero prototype. The only (?) difference is that
it only has 256 MiB of RAM, compared to the 512 MiB of RAM of the retail
device.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/boot/dts/ingenic/gcw0_proto.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 arch/mips/boot/dts/ingenic/gcw0_proto.dts
diff --git a/arch/mips/boot/dts/ingenic/gcw0_proto.dts b/arch/mips/boot/dts/ingenic/gcw0_proto.dts
new file mode 100644
index 000000000000..02df22f8ae0f
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/gcw0_proto.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "gcw0.dts"
+
+/ {
+ model = "GCW Zero Prototype";
+};
+
+&memory {
+ /* Prototype has only 256 MiB of RAM */
+ reg = <0x0 0x10000000>;
+};
--
2.26.2
^ permalink raw reply related
* [PATCH 3/3] MIPS: ingenic: Default to a generic board
From: Paul Cercueil @ 2020-05-25 17:41 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: od, devicetree, linux-mips, linux-kernel, Paul Cercueil
In-Reply-To: <20200525174155.457491-1-paul@crapouillou.net>
Having a generic board option makes it possible to create a kernel that
will run on various Ingenic SoCs, as long as the right devicetree is
provided.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
arch/mips/jz4740/Kconfig | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 412d2faa3cdf..9c2e8c15bb97 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -2,7 +2,14 @@
choice
prompt "Machine type"
depends on MACH_INGENIC
- default JZ4740_QI_LB60
+ default INGENIC_GENERIC_BOARD
+
+config INGENIC_GENERIC_BOARD
+ bool "Generic board"
+ select MACH_JZ4740
+ select MACH_JZ4770
+ select MACH_JZ4780
+ select MACH_X1000
config JZ4740_QI_LB60
bool "Qi Hardware Ben NanoNote"
--
2.26.2
^ permalink raw reply related
* [PATCH 0/3] hwrng: add support for Silex Insight BA431
From: Olivier Sobrie @ 2020-05-25 19:56 UTC (permalink / raw)
To: Matt Mackall, Herbert Xu, Rob Herring, Arnd Bergmann,
Greg Kroah-Hartman, linux-crypto, devicetree, linux-kernel
Cc: Olivier Sobrie, Waleed Ziad, sebastien.rabou
Hello all,
This set of patches aims at introducing a linux hwrng driver for the
Silex Insight BA431 IP which is available for various FPGA.
This hardware is for instance present in Silex Insight Viper OEM boards.
The two first patches are documenting the device tree bindings.
The last one contains the BA431 hwrng driver.
Olivier Sobrie (3):
dt-bindings: vendor-prefixes: Add Silex Insight vendor prefix
dt-bindings: rng: document Silex Insight BA431 hwrng
hwrng: ba431-rng: add support for BA431 hwrng
.../bindings/rng/silex-insight,ba431-rng.yaml | 33 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
drivers/char/hw_random/Kconfig | 10 +
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/ba431-rng.c | 241 ++++++++++++++++++
5 files changed, 287 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml
create mode 100644 drivers/char/hw_random/ba431-rng.c
--
2.26.2
^ permalink raw reply
* [PATCH 1/3] dt-bindings: vendor-prefixes: Add Silex Insight vendor prefix
From: Olivier Sobrie @ 2020-05-25 19:56 UTC (permalink / raw)
To: Matt Mackall, Herbert Xu, Rob Herring, Arnd Bergmann,
Greg Kroah-Hartman, linux-crypto, devicetree, linux-kernel
Cc: Olivier Sobrie, Waleed Ziad, sebastien.rabou
In-Reply-To: <20200525195606.2941649-1-olivier.sobrie@silexinsight.com>
Silex Insight is a microelectronic company whose headquarter is located
in Belgium.
Web site of the company: https://www.silexinsight.com/
Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index d3891386d6710..45e555774be42 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -918,6 +918,8 @@ patternProperties:
description: Silead Inc.
"^silergy,.*":
description: Silergy Corp.
+ "^silex-insight,.*":
+ description: Silex Insight
"^siliconmitus,.*":
description: Silicon Mitus, Inc.
"^simtek,.*":
--
2.26.2
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: rng: document Silex Insight BA431 hwrng
From: Olivier Sobrie @ 2020-05-25 19:56 UTC (permalink / raw)
To: Matt Mackall, Herbert Xu, Rob Herring, Arnd Bergmann,
Greg Kroah-Hartman, linux-crypto, devicetree, linux-kernel
Cc: Olivier Sobrie, Waleed Ziad, sebastien.rabou
In-Reply-To: <20200525195606.2941649-1-olivier.sobrie@silexinsight.com>
This patch documents the device tree bindings of the BA431 hardware
random number generator.
This IP is for instance present in the Viper OEM boards sold by Silex
Insight.
Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
---
.../bindings/rng/silex-insight,ba431-rng.yaml | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml
diff --git a/Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml b/Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml
new file mode 100644
index 0000000000000..48ab82abf50ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/silex-insight,ba431-rng.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/silex-insight,ba431-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Silex Insight BA431 RNG bindings
+
+description: |
+ The BA431 hardware random number generator is an IP that is FIPS-140-2/3
+ certified.
+
+maintainers:
+ - Olivier Sobrie <olivier.sobrie@silexinsight.com>
+
+properties:
+ compatible:
+ const: silex-insight,ba431-rng
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ rng@42800000 {
+ compatible = "silex-insight,ba431-rng";
+ reg = <0x42800000 0x1000>;
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH 3/3] hwrng: ba431-rng: add support for BA431 hwrng
From: Olivier Sobrie @ 2020-05-25 19:56 UTC (permalink / raw)
To: Matt Mackall, Herbert Xu, Rob Herring, Arnd Bergmann,
Greg Kroah-Hartman, linux-crypto, devicetree, linux-kernel
Cc: Olivier Sobrie, Waleed Ziad, sebastien.rabou
In-Reply-To: <20200525195606.2941649-1-olivier.sobrie@silexinsight.com>
Silex insight BA431 is an IP designed to generate random numbers that
can be integrated in various FPGA.
This driver adds support for it through the hwrng interface.
This driver is used in Silex Insight Viper OEM boards.
Signed-off-by: Olivier Sobrie <olivier.sobrie@silexinsight.com>
Signed-off-by: Waleed Ziad <waleed94ziad@gmail.com>
---
drivers/char/hw_random/Kconfig | 10 ++
drivers/char/hw_random/Makefile | 1 +
drivers/char/hw_random/ba431-rng.c | 240 +++++++++++++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 drivers/char/hw_random/ba431-rng.c
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index 9bc46da8d77a8..ef8928fc9999d 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -74,6 +74,16 @@ config HW_RANDOM_ATMEL
If unsure, say Y.
+config HW_RANDOM_BA431
+ tristate "Silex Insight BA431 Random Number Generator support"
+ default HW_RANDOM
+ help
+ This driver provides kernel-side support for the Random Number
+ Generator hardware based on Silex Insight BA431 IP.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ba431-rng
+
config HW_RANDOM_BCM2835
tristate "Broadcom BCM2835/BCM63xx Random Number Generator support"
depends on ARCH_BCM2835 || ARCH_BCM_NSP || ARCH_BCM_5301X || \
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index a7801b49ce6c0..02ccadafcca99 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o
+obj-$(CONFIG_HW_RANDOM_BA431) += ba431-rng.o
obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
n2-rng-y := n2-drv.o n2-asm.o
diff --git a/drivers/char/hw_random/ba431-rng.c b/drivers/char/hw_random/ba431-rng.c
new file mode 100644
index 0000000000000..d3bec75d405e4
--- /dev/null
+++ b/drivers/char/hw_random/ba431-rng.c
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Silex Insight sa.
+
+#include <linux/delay.h>
+#include <linux/hw_random.h>
+#include <linux/io.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+
+#define BA431_RESET_DELAY 1 /* usec */
+#define BA431_RESET_READ_STATUS_RETRIES 100
+#define BA431_RESET_READ_STATUS_INTERVAL 10 /* usec */
+#define BA431_READ_RETRY_INTERVAL 1 /* usec */
+
+#define BA431_REG_CTRL 0x00
+#define BA431_REG_FIFO_LEVEL 0x04
+#define BA431_REG_STATUS 0x30
+#define BA431_REG_FIFODATA 0x80
+
+#define BA431_CTRL_ENABLE BIT(0)
+#define BA431_CTRL_SOFTRESET BIT(8)
+
+#define BA431_STATUS_STATE_MASK (BIT(1) | BIT(2) | BIT(3))
+#define BA431_STATUS_STATE_OFFSET 1
+
+enum ba431_state {
+ BA431_STATE_RESET,
+ BA431_STATE_STARTUP,
+ BA431_STATE_FIFOFULLON,
+ BA431_STATE_FIFOFULLOFF,
+ BA431_STATE_RUNNING,
+ BA431_STATE_ERROR
+};
+
+struct ba431_trng {
+ struct device *dev;
+ void __iomem *base;
+ struct hwrng rng;
+ atomic_t reset_pending;
+ struct work_struct reset_work;
+};
+
+static inline u32 ba431_trng_read_reg(struct ba431_trng *ba431, u32 reg)
+{
+ return ioread32(ba431->base + reg);
+}
+
+static inline void ba431_trng_write_reg(struct ba431_trng *ba431, u32 reg,
+ u32 val)
+{
+ iowrite32(val, ba431->base + reg);
+}
+
+static inline enum ba431_state ba431_trng_get_state(struct ba431_trng *ba431)
+{
+ u32 status = ba431_trng_read_reg(ba431, BA431_REG_STATUS);
+
+ return (status & BA431_STATUS_STATE_MASK) >> BA431_STATUS_STATE_OFFSET;
+}
+
+static int ba431_trng_is_in_error(struct ba431_trng *ba431)
+{
+ enum ba431_state state = ba431_trng_get_state(ba431);
+
+ if ((state < BA431_STATE_STARTUP) ||
+ (state >= BA431_STATE_ERROR))
+ return 1;
+
+ return 0;
+}
+
+static int ba431_trng_reset(struct ba431_trng *ba431)
+{
+ unsigned int i;
+ enum ba431_state state;
+
+ /* Disable interrupts, random generation and enable the softreset */
+ ba431_trng_write_reg(ba431, BA431_REG_CTRL, BA431_CTRL_SOFTRESET);
+ udelay(BA431_RESET_DELAY);
+ ba431_trng_write_reg(ba431, BA431_REG_CTRL, BA431_CTRL_ENABLE);
+
+ /* Wait until the state changed */
+ for (i = 0; i < BA431_RESET_READ_STATUS_RETRIES; ++i) {
+ state = ba431_trng_get_state(ba431);
+ if (state >= BA431_STATE_STARTUP)
+ break;
+
+ udelay(BA431_RESET_READ_STATUS_INTERVAL);
+ }
+
+ if ((state < BA431_STATE_STARTUP) || (state >= BA431_STATE_ERROR)) {
+ dev_err(ba431->dev, "reset failed (state: %d)\n",
+ state);
+ return -1;
+ }
+
+ dev_info(ba431->dev, "reset done\n");
+
+ return 0;
+}
+
+static void ba431_trng_reset_work(struct work_struct *work)
+{
+ struct ba431_trng *ba431 = container_of(work, struct ba431_trng,
+ reset_work);
+ ba431_trng_reset(ba431);
+ atomic_set(&ba431->reset_pending, 0);
+}
+
+static void ba431_trng_schedule_reset(struct ba431_trng *ba431)
+{
+ if (atomic_cmpxchg(&ba431->reset_pending, 0, 1))
+ return;
+
+ schedule_work(&ba431->reset_work);
+}
+
+static int ba431_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
+ u32 *data = buf;
+ unsigned int level, i;
+ int n = 0;
+
+ while (max > 0) {
+ level = ba431_trng_read_reg(ba431, BA431_REG_FIFO_LEVEL);
+ if (!level) {
+ if (ba431_trng_is_in_error(ba431)) {
+ ba431_trng_schedule_reset(ba431);
+ break;
+ }
+
+ if (!wait)
+ break;
+
+ udelay(BA431_READ_RETRY_INTERVAL);
+ continue;
+ }
+
+ i = level;
+ do {
+ data[n++] = ba431_trng_read_reg(ba431,
+ BA431_REG_FIFODATA);
+ max -= sizeof(*data);
+ } while (--i && (max > 0));
+
+ if (ba431_trng_is_in_error(ba431)) {
+ n -= (level - i);
+ ba431_trng_schedule_reset(ba431);
+ break;
+ }
+ }
+
+ n *= sizeof(data);
+ return (n || !wait) ? n : -EIO;
+}
+
+static void ba431_trng_cleanup(struct hwrng *rng)
+{
+ struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
+
+ ba431_trng_write_reg(ba431, BA431_REG_CTRL, 0);
+ cancel_work_sync(&ba431->reset_work);
+}
+
+static int ba431_trng_init(struct hwrng *rng)
+{
+ struct ba431_trng *ba431 = container_of(rng, struct ba431_trng, rng);
+
+ return ba431_trng_reset(ba431);
+}
+
+static int ba431_trng_probe(struct platform_device *pdev)
+{
+ struct ba431_trng *ba431;
+ struct resource *res;
+ int ret;
+
+ ba431 = devm_kzalloc(&pdev->dev, sizeof(*ba431), GFP_KERNEL);
+ if (!ba431)
+ return -ENOMEM;
+
+ ba431->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ba431->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ba431->base))
+ return PTR_ERR(ba431->base);
+
+ atomic_set(&ba431->reset_pending, 0);
+ INIT_WORK(&ba431->reset_work, ba431_trng_reset_work);
+ ba431->rng.name = pdev->name;
+ ba431->rng.init = ba431_trng_init;
+ ba431->rng.cleanup = ba431_trng_cleanup;
+ ba431->rng.read = ba431_trng_read;
+
+ platform_set_drvdata(pdev, ba431);
+
+ ret = hwrng_register(&ba431->rng);
+ if (ret) {
+ dev_err(&pdev->dev, "BA431 registration failed (%d)\n", ret);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "BA431 TRNG registered\n");
+
+ return 0;
+}
+
+static int ba431_trng_remove(struct platform_device *pdev)
+{
+ struct ba431_trng *ba431 = platform_get_drvdata(pdev);
+
+ hwrng_unregister(&ba431->rng);
+
+ return 0;
+}
+
+static const struct of_device_id ba431_trng_dt_ids[] = {
+ { .compatible = "silex-insight,ba431-rng", .data = NULL },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, ba431_trng_dt_ids);
+
+static struct platform_driver ba431_trng_driver = {
+ .driver = {
+ .name = "ba431-rng",
+ .of_match_table = ba431_trng_dt_ids,
+ },
+ .probe = ba431_trng_probe,
+ .remove = ba431_trng_remove,
+};
+
+module_platform_driver(ba431_trng_driver);
+
+MODULE_AUTHOR("Olivier Sobrie <olivier@sobrie.be>");
+MODULE_DESCRIPTION("TRNG driver for Silex Insight BA431");
+MODULE_LICENSE("GPL");
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v3 1/8] dt-bindings: net: meson-dwmac: Add the amlogic,rx-delay-ns property
From: Pavel Machek @ 2020-05-25 20:17 UTC (permalink / raw)
To: Andrew Lunn
Cc: Florian Fainelli, Martin Blumenstingl, robh+dt, linux-amlogic,
devicetree, jianxin.pan, davem, netdev, linux-kernel,
linux-arm-kernel
In-Reply-To: <20200525135728.GE752669@lunn.ch>
[-- Attachment #1: Type: text/plain, Size: 858 bytes --]
On Mon 2020-05-25 15:57:28, Andrew Lunn wrote:
> > > standardizing on rx-delay-ps and tx-delay-ps would make sense since that
> > > is the lowest resolution and the property would be correctly named with
> > > an unit in the name.
> >
> > Seems like similar patch is already being reviewed from Dan Murphy (?)
> > from TI.
>
> Dan is working on the PHY side. But there is probably code which can
> be shared.
>
> One question to consider, do we want the same properties names for MAC
> and PHY, or do we want to make them different, to avoid confusion?
We have same properties accross different hardware (compatible, reg),
so same property between MAC and PHY seems to make sense.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
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