* Re: [PATCH v3 07/21] drm/panel: himax-hx83102: support Waveshare 12.3" DSI panel
From: Neil Armstrong @ 2026-04-14 12:57 UTC (permalink / raw)
To: Dmitry Baryshkov, Jessica Zhang, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Cong Yang, Ondrej Jirman,
Javier Martinez Canillas, Jagan Teki, Liam Girdwood, Mark Brown,
Linus Walleij, Bartosz Golaszewski, Jie Gan
Cc: dri-devel, devicetree, linux-kernel, linux-gpio
In-Reply-To: <20260413-waveshare-dsi-touch-v3-7-3aeb53022c32@oss.qualcomm.com>
On 4/13/26 16:05, Dmitry Baryshkov wrote:
> Add support for the Waveshare 12.3" DSI TOUCH-A panel. According to the
> vendor driver, it uses different mode_flags, so let the panel
> descriptions override driver-wide defaults.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/gpu/drm/panel/panel-himax-hx83102.c | 144 +++++++++++++++++++++++++++-
> 1 file changed, 142 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/panel/panel-himax-hx83102.c
> index 8b2a68ee851e..eab67893da86 100644
> --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c
> +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c
> @@ -29,11 +29,14 @@
> #define HX83102_UNKNOWN_B8 0xb8
> #define HX83102_SETEXTC 0xb9
> #define HX83102_SETMIPI 0xba
> +#define HX83102_UNKNOWN_BB 0xbb
> #define HX83102_SETVDC 0xbc
> #define HX83102_SETBANK 0xbd
> #define HX83102_UNKNOWN_BE 0xbe
> #define HX83102_SETPTBA 0xbf
> #define HX83102_SETSTBA 0xc0
> +#define HX83102_UNKNOWN_C2 0xc2
> +#define HX83102_UNKNOWN_C6 0xc6
> #define HX83102_SETTCON 0xc7
> #define HX83102_SETRAMDMY 0xc8
> #define HX83102_SETPWM 0xc9
> @@ -78,6 +81,7 @@ struct hx83102_panel_desc {
> } size;
>
> bool has_backlight;
> + unsigned long mode_flags;
>
> int (*init)(struct hx83102 *ctx);
> };
> @@ -765,6 +769,111 @@ static int holitech_htf065h045_init(struct hx83102 *ctx)
> return dsi_ctx.accum_err;
> }
>
> +/* This is HX83102-E, assuming commands are the same as the normal HX83102 */
> +static int waveshare_12_3_a_init(struct hx83102 *ctx)
> +{
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER,
> + 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36,
> + 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP,
> + 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02,
> + 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC,
> + 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7,
> + 0x01, 0x58, 0x00, 0xff, 0x00, 0xff);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
> + 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27,
> + 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13,
> + 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00,
> + 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20,
> + 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA,
> + 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64,
> + 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d,
> + 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64,
> + 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85,
> + 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK,
> + 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0,
> + 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00,
> + 0x01);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA,
> + 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00,
> + 0x08, 0x00, 0x63, 0x63);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY,
> + 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20,
> + 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a,
> + 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18,
> + 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
> + 0x18, 0x18, 0x18, 0x18);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2,
> + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21,
> + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a,
> + 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18,
> + 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98,
> + 0x98, 0x98, 0x98, 0x98);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1,
> + 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
> + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80,
> + 0x2a, 0xaa, 0xaa, 0xaa);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
> + 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
> + 0xaa, 0xaa);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3,
> + 0xff, 0xff, 0xff, 0xff,
> + 0xff, 0xf0, 0xff, 0xff,
> + 0xff, 0xff, 0xff, 0xf0);
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00);
> +
> + return dsi_ctx.accum_err;
> +};
> +
> static const struct drm_display_mode starry_mode = {
> .clock = 162680,
> .hdisplay = 1200,
> @@ -920,6 +1029,30 @@ static const struct hx83102_panel_desc holitech_htf065h045_desc = {
> .init = holitech_htf065h045_init,
> };
>
> +static const struct drm_display_mode waveshare_12_3_a_mode = {
> + .clock = 95000,
> + .hdisplay = 720,
> + .hsync_start = 720 + 10,
> + .hsync_end = 720 + 10 + 10,
> + .htotal = 720 + 10 + 10 + 12,
> + .vdisplay = 1920,
> + .vsync_start = 1920 + 64,
> + .vsync_end = 1920 + 64 + 18,
> + .vtotal = 1920 + 64 + 18 + 4,
> + .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
> +};
> +
> +static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = {
> + .modes = &waveshare_12_3_a_mode,
> + .size = {
> + .width_mm = 109,
> + .height_mm = 292,
> + },
> + .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO |
> + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS,
> + .init = waveshare_12_3_a_init,
> +};
> +
> static int hx83102_enable(struct drm_panel *panel)
> {
> msleep(130);
> @@ -1168,8 +1301,12 @@ static int hx83102_probe(struct mipi_dsi_device *dsi)
> desc = of_device_get_match_data(&dsi->dev);
> dsi->lanes = 4;
> dsi->format = MIPI_DSI_FMT_RGB888;
> - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> - MIPI_DSI_MODE_LPM;
> + if (desc->mode_flags)
> + dsi->mode_flags = desc->mode_flags;
> + else
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
> + MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
> + MIPI_DSI_MODE_LPM;
> ctx->desc = desc;
> ctx->dsi = dsi;
> ret = hx83102_panel_add(ctx);
> @@ -1220,6 +1357,9 @@ static const struct of_device_id hx83102_of_match[] = {
> { .compatible = "holitech,htf065h045",
> .data = &holitech_htf065h045_desc
> },
> + { .compatible = "waveshare,12.3-dsi-touch-a",
> + .data = &waveshare_12_3_inch_a_desc
> + },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, hx83102_of_match);
>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: socfpga: Add the Agilex7 series SoC's
From: Krzysztof Kozlowski @ 2026-04-14 12:55 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: robh, krzk+dt, conor+dt, devicetree
In-Reply-To: <a2945037-d8c9-45b5-b161-ac55ac9b0835@kernel.org>
On 14/04/2026 14:53, Dinh Nguyen wrote:
>
>
> On 4/14/26 02:17, Krzysztof Kozlowski wrote:
>> On Mon, Apr 13, 2026 at 09:45:52AM -0500, Dinh Nguyen wrote:
>>> The Agilex7 is a series of devices from Altera that are derived from
>>> the Agilex family.
>>>
>>> The Agilex7F device supports PCIE 4.0 and DDR4. The Agilex7I device supports
>>> PCIE 5.0 and DDR4, while the Agilex7M device supports DDR4, DDR5, LPDDR5
>>> and PCIE 5.0.
>>>
>>> All other peripherals from these devices are the same as the Agilex
>>> device.
>>>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++
>>> 1 file changed, 10 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
>>> index 206686f3eebc..5ee09f8d4698 100644
>>> --- a/Documentation/devicetree/bindings/arm/altera.yaml
>>> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>>> @@ -115,6 +115,16 @@ properties:
>>> - intel,socfpga-agilex5-socdk-nand
>>> - const: intel,socfpga-agilex5
>>>
>>> + - description: Agilex7 series F, I and M boards
>>> + items:
>>> + - enum:
>>> + - intel,socfpga-agilex7m-socdk
>>> + - enum:
>>> + - intel,socfpga-agilex7f
>>> + - intel,socfpga-agilex7i
>>> + - intel,socfpga-agilex7m
>>> + - const: intel,socfpga-agilex
>>
>> And separate question - why previous soc "agilex" is used as fallback?
>> Even more confusing.
>>
>
> You're right. Sorry for the confusion. The Agilex7M, I, F devices are
> basically "agilex" devices with some few additions (PCIE, DDR5). Maybe I
> should place the Agilex7M/I/F devices into the "agilex" boards area?
Compatibles should be specific and not based on families, thus what is
"intel,socfpga-agilex"? SoC, right?
Then "intel,socfpga-agilex7f" is a new SoC, no?
Best regards,
Krzysztof
^ permalink raw reply
* RE: [PATCH v7 6/6] docs: iio: adc: ad4691: add driver documentation
From: Sabau, Radu bogdan @ 2026-04-14 12:54 UTC (permalink / raw)
To: David Lechner, Lars-Peter Clausen, Hennerich, Michael,
Jonathan Cameron, Sa, Nuno, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Uwe Kleine-König,
Liam Girdwood, Mark Brown, Linus Walleij, Bartosz Golaszewski,
Philipp Zabel, Jonathan Corbet, Shuah Khan
Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org
In-Reply-To: <9c36ee85-12da-41e8-b9ab-e32b7ec29e75@baylibre.com>
> -----Original Message-----
> From: David Lechner <dlechner@baylibre.com>
> Sent: Saturday, April 11, 2026 12:39 AM
...
> > +Buffer data format
> > +==================
> > +
> > +The IIO buffer data format (``in_voltageN_type``) is the same across all
> > +paths: 16-bit unsigned big-endian samples with no shift.
> > +
> > ++-------------------------+-------------+----------+-------+
> > +| Path | storagebits | realbits | shift |
> > ++=========================+=============+==========+=======+
> > +| Triggered buffer | 16 | 16 | 0 |
> > ++-------------------------+-------------+----------+-------+
> > +| CNV Burst offload (DMA) | 16 | 16 | 0 |
> > ++-------------------------+-------------+----------+-------+
> > +| Manual offload (DMA) | 16 | 16 | 0 |
> > ++-------------------------+-------------+----------+-------+
>
> Not sure this table is helpful since all values are the same everywhere.
>
> Also, doesn't SPI offload have storagebits == 32?
I tried using 16 storage bits for offload too, and so use the same channels
macro. For Manual its received in the next transfer and for CNV only the
receive transfers are rx streamed, and so 16 storage bits suffice for both.
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: socfpga: Add the Agilex7 series SoC's
From: Dinh Nguyen @ 2026-04-14 12:53 UTC (permalink / raw)
To: Krzysztof Kozlowski; +Cc: robh, krzk+dt, conor+dt, devicetree
In-Reply-To: <20260414-certain-puffin-from-avalon-29ceeb@quoll>
On 4/14/26 02:17, Krzysztof Kozlowski wrote:
> On Mon, Apr 13, 2026 at 09:45:52AM -0500, Dinh Nguyen wrote:
>> The Agilex7 is a series of devices from Altera that are derived from
>> the Agilex family.
>>
>> The Agilex7F device supports PCIE 4.0 and DDR4. The Agilex7I device supports
>> PCIE 5.0 and DDR4, while the Agilex7M device supports DDR4, DDR5, LPDDR5
>> and PCIE 5.0.
>>
>> All other peripherals from these devices are the same as the Agilex
>> device.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> Documentation/devicetree/bindings/arm/altera.yaml | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
>> index 206686f3eebc..5ee09f8d4698 100644
>> --- a/Documentation/devicetree/bindings/arm/altera.yaml
>> +++ b/Documentation/devicetree/bindings/arm/altera.yaml
>> @@ -115,6 +115,16 @@ properties:
>> - intel,socfpga-agilex5-socdk-nand
>> - const: intel,socfpga-agilex5
>>
>> + - description: Agilex7 series F, I and M boards
>> + items:
>> + - enum:
>> + - intel,socfpga-agilex7m-socdk
>> + - enum:
>> + - intel,socfpga-agilex7f
>> + - intel,socfpga-agilex7i
>> + - intel,socfpga-agilex7m
>> + - const: intel,socfpga-agilex
>
> And separate question - why previous soc "agilex" is used as fallback?
> Even more confusing.
>
You're right. Sorry for the confusion. The Agilex7M, I, F devices are
basically "agilex" devices with some few additions (PCIE, DDR5). Maybe I
should place the Agilex7M/I/F devices into the "agilex" boards area?
Thanks,
Dinh
^ permalink raw reply
* Re: [PATCH v2 1/8] dt-bindings: thermal: amlogic: Add support for T7
From: Ronald Claveau @ 2026-04-14 12:33 UTC (permalink / raw)
To: Conor Dooley
Cc: Guillaume La Roque, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
linux-pm, linux-amlogic, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260413-impose-cartel-bd7d18f91a24@spud>
On 4/13/26 5:42 PM, Conor Dooley wrote:
> On Mon, Apr 13, 2026 at 12:52:42PM +0200, Ronald Claveau wrote:
>> Add the amlogic,t7-thermal compatible for the Amlogic T7 thermal sensor.
>>
>> Unlike existing variants which use a phandle to the ao-secure syscon,
>> the T7 relies on a secure monitor interface described by a phandle and
>> a sensor index argument.
>>
>> The T7 integrates multiple thermal sensors, all accessed through the
>> same SMC call. The sensor index argument is required to identify which
>> sensor's calibration data the secure monitor should return, as a single
>> SM_THERMAL_CALIB_READ command serves all of them.
>>
>> Introduce the amlogic,secure-monitor property as a phandle-array and
>> make amlogic,ao-secure or amlogic,secure-monitor conditionally required
>> depending on the compatible.
>>
>> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
>> ---
>> .../bindings/thermal/amlogic,thermal.yaml | 42 ++++++++++++++++++++--
>> 1 file changed, 40 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
>> index 70b273271754b..1c096116b2dda 100644
>> --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
>> +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
>> @@ -21,7 +21,9 @@ properties:
>> - amlogic,g12a-cpu-thermal
>> - amlogic,g12a-ddr-thermal
>> - const: amlogic,g12a-thermal
>> - - const: amlogic,a1-cpu-thermal
>> + - enum:
>> + - amlogic,a1-cpu-thermal
>> + - amlogic,t7-thermal
>>
>> reg:
>> maxItems: 1
>> @@ -42,12 +44,39 @@ properties:
>> '#thermal-sensor-cells':
>> const: 0
>>
>> + amlogic,secure-monitor:
>> + description: phandle to the secure monitor
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + items:
>> + - items:
>> + - description: phandle to the secure monitor
>> + - description: sensor index to get specific calibration data
>> +
>> required:
>> - compatible
>> - reg
>> - interrupts
>> - clocks
>> - - amlogic,ao-secure
>> +
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - amlogic,a1-cpu-thermal
>> + - amlogic,g12a-thermal
>> + then:
>> + required:
>> + - amlogic,ao-secure
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: amlogic,t7-thermal
>
> This can just be replaced by a else I think.
>
Thank you for your feedback, I will replace this `if` condition by an
`else`.
>> + then:
>> + required:
>> + - amlogic,secure-monitor
>>
>> unevaluatedProperties: false
>>
>> @@ -62,4 +91,13 @@ examples:
>> #thermal-sensor-cells = <0>;
>> amlogic,ao-secure = <&sec_AO>;
>> };
>> + - |
>> + a73_tsensor: temperature-sensor@20000 {
>
> Can drop the label here, it has no users.
>
Ok, I will remove this label.
> Otherwise, seems fine.
>
> Cheers,
> Conor.
>
> pw-bot: changes-requested
>
>> + compatible = "amlogic,t7-thermal";
>> + reg = <0x0 0x20000 0x0 0x50>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&clkc_periphs CLKID_TS>;
>> + #thermal-sensor-cells = <0>;
>> + amlogic,secure-monitor = <&sm 1>;
>> + };
>> ...
>>
>> --
>> 2.49.0
>>
--
Best regards,
Ronald
^ permalink raw reply
* Re: [PATCH v7 0/8] Add support for handling PCIe M.2 Key E connectors in devicetree
From: Andy Shevchenko @ 2026-04-14 12:03 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Manivannan Sadhasivam, Manivannan Sadhasivam, Rob Herring,
Greg Kroah-Hartman, Jiri Slaby, Nathan Chancellor, Nicolas Schier,
Hans de Goede, Ilpo Järvinen, Mark Pearson, Derek J. Clark,
Krzysztof Kozlowski, Conor Dooley, Marcel Holtmann,
Luiz Augusto von Dentz, Bartosz Golaszewski, Bartosz Golaszewski,
linux-serial, linux-kernel, linux-kbuild, platform-driver-x86,
linux-pci, devicetree, linux-arm-msm, linux-bluetooth, linux-pm,
Stephan Gerhold, Dmitry Baryshkov, linux-acpi, Hans de Goede,
Bartosz Golaszewski
In-Reply-To: <CAGXv+5EGe59nJctLweEdZjb3MNmMvjuCHngGSfptzN985OiLdg@mail.gmail.com>
On Tue, Apr 14, 2026 at 06:29:02PM +0800, Chen-Yu Tsai wrote:
> On Tue, Apr 14, 2026 at 4:28 PM Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> > On Tue, Apr 14, 2026 at 01:03:19PM +0800, Chen-Yu Tsai wrote:
> > > On Tue, Apr 14, 2026 at 12:08 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > On Mon, Apr 13, 2026 at 07:33:12PM +0530, Manivannan Sadhasivam wrote:
> > > > > On Mon, Apr 13, 2026 at 03:54:59PM +0800, Chen-Yu Tsai wrote:
> > > > > > On Thu, Mar 26, 2026 at 01:36:28PM +0530, Manivannan Sadhasivam wrote:
...
> > > > > > - Given that this connector actually represents two devices, how do I
> > > > > > say I want the BT part to be a wakeup source, but not the WiFi part?
> > > > > > Does wakeup-source even work at this point?
> > > > >
> > > > > You can't use the DT property since the devices are not described in DT
> > > > > statically. But you can still use the per-device 'wakeup' sysfs knob to enable
> > > > > wakeup.
> > >
> > > I see. I think not being able to specify generic properties for the devices
> > > on the connector is going to be a bit problematic.
> >
> > This is nature of the open-connectors, especially on the busses that are
> > hotpluggable, like PCIe. We never know what is connected there _ahead_.
>
> I believe what you mean by "hotpluggable" is "user replaceable".
From the OS perspective it's the same. From platform perspective
there is a difference, granted.
> > In other words you can't describe in DT something that may not exist.
>
> But this is actually doable with the PCIe slot representation. The
> properties are put in the device node for the slot. If no card is
> actually inserted in the slot, then no device is created, and the
> device node is left as not associated with anything.
But you need to list all devices in the world if you want to support this
somehow. Yes, probably many of them (or majority) will be enumerated as is,
but some may need an assistance via (dynamic) properties or similar mechanisms.
> It's just that for this new M.2 E-key connector, there aren't separate
> nodes for each interface. And the system doesn't associate the device
> node with the device, because it's no longer a child node of the
> controller or hierarchy, but connected over the OF graph.
>
> Moving over to the E-key connector representation seems like one step
> forward and one step backward in descriptive ability. We gain proper
> power sequencing, but lose generic properties.
The "key" is property of the connector. Hence if you have an idea what can be
common for ALL "key":s, that's probably can be abstracted. Note, I'm not
familiar with the connector framework in the Linux kernel, perhaps it's already
that kind of abstraction.
> The latter part is solvable, but we likely need child nodes under the
> connector for the different interfaces. Properties that make sense for
> one type might not make sense for another.
>
> P.S. We could also just add child device nodes under the controller to
> put the generic properties, but that's splitting the description into
> multiple parts. Let's not go there if at all possible.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v1 1/4] arm64: dts: qcom: Enable secondary mi2s
From: Konrad Dybcio @ 2026-04-14 11:58 UTC (permalink / raw)
To: Kumar Anurag, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Srinivas Kandagatla,
Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai
Cc: linux-arm-msm, devicetree, linux-kernel, linux-sound
In-Reply-To: <20260413091937.134469-2-kumar.singh@oss.qualcomm.com>
On 4/13/26 11:19 AM, Kumar Anurag wrote:
> Enable secondary mi2s to support HDMI audio.
>
> Signed-off-by: Kumar Anurag <kumar.singh@oss.qualcomm.com>
> ---
[...]
> +&mi2s1_data0 {
> + drive-strength = <8>;
> + bias-disable;
> +};
> +
> +&mi2s1_mclk {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
> +};
> +
> +&mi2s1_sclk {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
> +};
> +
> +&mi2s1_ws {
> + drive-strength = <8>;
> + bias-disable;
> + output-high;
For these pins in their "mission mode" function, do we expect these
pincfg settings to ever change (i.e. across boards, will the drive-strength/
bias/output properties differ?)
Konrad
^ permalink raw reply
* Re: [PATCH v3 1/5] arm64: dts: qcom: sm8550: add PCIe MHI register regions
From: Konrad Dybcio @ 2026-04-14 11:53 UTC (permalink / raw)
To: jsandom, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260409-rb5gen2-dts-v3-1-be736355d4b4@axon.com>
On 4/9/26 5:26 PM, Joe Sandom via B4 Relay wrote:
> From: Joe Sandom <jsandom@axon.com>
>
> Add the MHI register regions to the pcie0 and pcie1 controller nodes
> to expose link power state transition counters (L0s/L1/L1.1/L1.2/L2)
> via debugfs. The PCIe host driver uses this region to read the
> link_transition_count from the MHI registers.
>
> Signed-off-by: Joe Sandom <jsandom@axon.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH 3/3] arm64: dts: mediatek: mt8395-genio-common: add MT6360 PMIC supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
The Mediatek Genio 1200-EVK board has a MT6360 PMIC, powered by the
board system power rail (VSYS) and an additional system power rail
(VSYS_BUCK).
In the board devicetree, the power supply inputs for its buck and ldo
regulators are either incorrect (LDO_VIN3) or missing (LDO_VIN1/2,
BUCK_VIN1/2).
So, add VSYS_BUCK regulator node and the proper supply inputs for this
PMIC.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
index 01e153137a6f..21dbcabe5e72 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
@@ -209,6 +209,14 @@ reg_vsys: regulator-vsys {
regulator-always-on;
regulator-boot-on;
};
+
+ reg_vsys_buck: regulator-vsys-buck {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_buck";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <®_vsys>;
+ };
};
&adsp {
@@ -486,7 +494,11 @@ otg_vbus_regulator: usb-otg-vbus-regulator {
regulator {
compatible = "mediatek,mt6360-regulator";
- LDO_VIN3-supply = <&mt6360_buck2>;
+ BUCK1_VIN-supply = <®_vsys>;
+ BUCK2_VIN-supply = <®_vsys>;
+ LDO_VIN1-supply = <®_vsys_buck>;
+ LDO_VIN2-supply = <®_vsys_buck>;
+ LDO_VIN3-supply = <®_vsys>;
mt6360_buck1: buck1 {
regulator-name = "emi_vdd2";
--
2.53.0
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: mediatek: mt8395-genio-common: add MT6315 PMIC supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
Mediatek Genio 1200-EVK board has two MT6315 PMICs, powered by the
board system power rail (VSYS) and connected to the SPMI interface.
Add VSYS regulator node for system power rail and the supply inputs of
these two PMICs.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
index 62c336e21500..01e153137a6f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-common.dtsi
@@ -201,6 +201,14 @@ wifi_fixed_3v3: regulator-2 {
enable-active-high;
regulator-always-on;
};
+
+ /* system wide 4.2V power rail */
+ reg_vsys: regulator-vsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vsys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&adsp {
@@ -1238,6 +1246,11 @@ mt6315_6: pmic@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 SPMI_USID>;
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-name = "Vbcpu";
@@ -1254,6 +1267,11 @@ mt6315_7: pmic@7 {
compatible = "mediatek,mt6315-regulator";
reg = <0x7 SPMI_USID>;
+ pvdd1-supply = <®_vsys>;
+ pvdd2-supply = <®_vsys>;
+ pvdd3-supply = <®_vsys>;
+ pvdd4-supply = <®_vsys>;
+
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-name = "Vgpu";
--
2.53.0
^ permalink raw reply related
* [PATCH 1/3] regulator: dt-bindings: mt6360: add buck regulator supplies
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
In-Reply-To: <20260414-mtk-g1200-pmic-cleanup-v1-0-2a7193ed4e93@collabora.com>
MT6360 PMIC provides 2 buck and 6 ldo regulators, that have each one a
separate supply.
Currently, the supplies for the ldo regulators are described in the
dt-bindings but the ones for the buck regulators are not.
Add the descriptions for these missing supplies.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
index 9c879bc3c360..cbb74e8e875d 100644
--- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
@@ -17,6 +17,10 @@ properties:
compatible:
const: mediatek,mt6360-regulator
+ BUCK1_VIN-supply:
+ description: Input supply phandle(s) for BUCK1
+ BUCK2_VIN-supply:
+ description: Input supply phandle(s) for BUCK2
LDO_VIN1-supply:
description: Input supply phandle(s) for LDO1/2/3
LDO_VIN2-supply:
--
2.53.0
^ permalink raw reply related
* [PATCH 0/3] Mediatek Genio 1200-EVK: MT6315/MT6360 PMIC regulator supply cleanup
From: Louis-Alexis Eyraud @ 2026-04-14 11:44 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Liam Girdwood, Mark Brown, Gene Chen
Cc: kernel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Louis-Alexis Eyraud
This series goal is to cleanup the power supplies of MT6315 and MT6360
PMIC regulators, that are either missing or incorrect in the Mediatek
Genio 1200-EVK board devicetree.
Patch 1 completes the MT6360 dt-bindings by adding the missing power
supply descriptions for its buck regulators, that already handled by
the mt6360 regulator driver.
Patch 2 adds for the board the MT6315 regulator supply properties, that
were added in the dt-bindings by [1].
Patch 3 adds for the board the MT6360 regulator supply properties and
fixes the existing one.
The series has been tested on Genio 1200-EVK board with a kernel based
on linux-next (tag: next-20260410).
[1]: https://lore.kernel.org/linux-mediatek/20260326081050.1115201-1-wenst@chromium.org/
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
Louis-Alexis Eyraud (3):
regulator: dt-bindings: mt6360: add buck regulator supplies
arm64: dts: mediatek: mt8395-genio-common: add MT6315 PMIC supplies
arm64: dts: mediatek: mt8395-genio-common: add MT6360 PMIC supplies
.../bindings/regulator/mt6360-regulator.yaml | 4 +++
.../boot/dts/mediatek/mt8395-genio-common.dtsi | 32 +++++++++++++++++++++-
2 files changed, 35 insertions(+), 1 deletion(-)
---
base-commit: f244905cd8cff7a7249cd3dac8a366e02d61ad4f
change-id: 20260413-mtk-g1200-pmic-cleanup-666643b85b52
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply
* Re: [PATCH v1 4/4] ASoC: qcom: sc8280xp: don't force S16_LE in hw_params fixup
From: Mark Brown @ 2026-04-14 11:40 UTC (permalink / raw)
To: Kumar Anurag
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Srinivas Kandagatla, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, linux-arm-msm, devicetree, linux-kernel,
linux-sound
In-Reply-To: <20260413091937.134469-5-kumar.singh@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 872 bytes --]
On Mon, Apr 13, 2026 at 02:19:37AM -0700, Kumar Anurag wrote:
> The machine driver was unconditionally forcing S16_LE in
> sc8280xp_be_hw_params_fixup(), which prevents links (e.g. HDMI bridges)
> that require 32-bit formats from working. Drop the format override and
> keep only the fixed rate/channels constraints.
> struct snd_interval *channels = hw_param_interval(params,
> SNDRV_PCM_HW_PARAM_CHANNELS);
> - struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
>
> rate->min = rate->max = 48000;
> - snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
This breaks compressed playback, for compressed streams we need to
override the format since the DSP will be converting an input compressed
stream to a PCM one. See 9565c9d53c5b (ASoC: qcom: sc8280xp: explicitly
set S16LE format in sc8280xp_be_hw_params_fixup()).
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v1 3/4] ASoC: qcom: q6dsp: Update bit format support for secondary i2s
From: Mark Brown @ 2026-04-14 11:38 UTC (permalink / raw)
To: Kumar Anurag
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Srinivas Kandagatla, Liam Girdwood, Jaroslav Kysela,
Takashi Iwai, linux-arm-msm, devicetree, linux-kernel,
linux-sound
In-Reply-To: <20260413091937.134469-4-kumar.singh@oss.qualcomm.com>
[-- Attachment #1: Type: text/plain, Size: 342 bytes --]
On Mon, Apr 13, 2026 at 02:19:36AM -0700, Kumar Anurag wrote:
> Add 32bit for playback and capture over secondary mi2s.
> - .formats = SNDRV_PCM_FMTBIT_S16_LE,
> + .formats = SNDRV_PCM_FMTBIT_S16_LE |
> + SNDRV_PCM_FMTBIT_S24_LE |
> + SNDRV_PCM_FMTBIT_S32_LE,
The commit message said 32 bit but this is both 24 and 32 bit.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* [PATCH v2 7/7] arm64: dts: qcom: hamoa: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the hamoa device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index 051dee076416..f10af9db8bd4 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -6882,6 +6882,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -6939,6 +6940,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -7077,6 +7079,7 @@ tpdm@10800000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rpdm_mxa";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7096,6 +7099,7 @@ tpdm@1082c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7115,6 +7119,7 @@ tpdm@10841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -7134,6 +7139,7 @@ tpdm@10844000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_lpass";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7177,6 +7183,7 @@ cti@1098b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_cscti";
};
tpdm@109d0000 {
@@ -7185,6 +7192,7 @@ tpdm@109d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7205,6 +7213,7 @@ tpdm@10ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7225,6 +7234,7 @@ tpdm@10ac1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7459,6 +7469,7 @@ tpdm@10b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7478,6 +7489,7 @@ tpdm@10b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7497,6 +7509,7 @@ tpdm@10b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7516,6 +7529,7 @@ tpdm@10b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7535,6 +7549,7 @@ tpdm@10b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7554,6 +7569,7 @@ tpdm@10b20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_lpi";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7624,6 +7640,7 @@ tpdm@10c08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7672,6 +7689,7 @@ tpdm@10c28000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -7691,6 +7709,7 @@ tpdm@10c29000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7824,6 +7843,7 @@ tpdm@10c38000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7843,6 +7863,7 @@ tpdm@10c39000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mx";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -7939,6 +7960,7 @@ tpdm@10cc1000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_tmess_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -8043,6 +8065,7 @@ tpdm@10d08000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_0";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8062,6 +8085,7 @@ tpdm@10d09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_1";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8081,6 +8105,7 @@ tpdm@10d0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_2";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8100,6 +8125,7 @@ tpdm@10d0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_3";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8119,6 +8145,7 @@ tpdm@10d0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_4";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8138,6 +8165,7 @@ tpdm@10d0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_5";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8157,6 +8185,7 @@ tpdm@10d0e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_6";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -8176,6 +8205,7 @@ tpdm@10d0f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llcc_7";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 6/7] arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the sm8750 device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd..fee7f28e44e4 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -4112,6 +4112,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4176,6 +4177,7 @@ tpdm@10800000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_modem_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4256,6 +4258,7 @@ cti@1080b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_mss_qdsp6";
};
tpdm@1082c000 {
@@ -4264,6 +4267,7 @@ tpdm@1082c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@@ -4282,6 +4286,7 @@ tpdm@10841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-msrs-num = <32>;
@@ -4300,6 +4305,7 @@ tpdm@1084e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_bcv";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4319,6 +4325,7 @@ tpdm@1084f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_lmh";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4338,6 +4345,7 @@ tpdm@10850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mm_dpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4402,6 +4410,7 @@ tpdm@10980000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4490,6 +4499,7 @@ cti@1098b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_qdsp";
};
tpdm@109a3000 {
@@ -4498,6 +4508,7 @@ tpdm@109a3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pmu";
qcom,cmb-msrs-num = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4517,6 +4528,7 @@ tpdm@109a4000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc";
qcom,cmb-msrs-num = <32>;
@@ -4535,6 +4547,7 @@ tpdm@109a5000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-msrs-num = <32>;
@@ -4553,6 +4566,7 @@ tpdm@109a6000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_north_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4571,6 +4585,7 @@ tpdm@109a7000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4589,6 +4604,7 @@ tpdm@109a8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb0";
qcom,cmb-msrs-num = <32>;
@@ -4607,6 +4623,7 @@ tpdm@109a9000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb1";
qcom,cmb-msrs-num = <32>;
@@ -4625,6 +4642,7 @@ tpdm@109aa000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cmb2";
qcom,cmb-msrs-num = <32>;
@@ -4776,6 +4794,7 @@ tpdm@109d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-msrs-num = <32>;
@@ -4909,6 +4928,7 @@ tpdm@10b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4928,6 +4948,7 @@ tpdm@10b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4947,6 +4968,7 @@ tpdm@10b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4966,6 +4988,7 @@ tpdm@10b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4985,6 +5008,7 @@ tpdm@10b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -6801,6 +6825,7 @@ timer {
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6814,6 +6839,7 @@ tpdm_cdsp_llm_out: endpoint {
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm2";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6827,6 +6853,7 @@ tpdm_cdsp_llm2_out: endpoint {
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_1";
qcom,dsb-element-bits = <32>;
out-ports {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 5/7] arm64: dts: qcom: kaanapali: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM nodes in the kaanapali device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1a..0d5714ddef9d 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -4201,6 +4201,7 @@ tpdm@10003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
@@ -4256,6 +4257,7 @@ tpdm@1000f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
@@ -4319,6 +4321,7 @@ tpdm@11000000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_modem_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4407,6 +4410,7 @@ tpdm@1102c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gcc";
qcom,dsb-msrs-num = <32>;
@@ -4425,6 +4429,7 @@ tpdm@11180000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4444,6 +4449,7 @@ tpdm@11183000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_cmsr1";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@@ -4463,6 +4469,7 @@ tpdm@11184000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_cmsr2";
qcom,dsb-element-bits = <32>;
qcom,cmb-element-bits = <32>;
@@ -4482,6 +4489,7 @@ tpdm@11185000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm1";
qcom,cmb-element-bits = <64>;
@@ -4500,6 +4508,7 @@ tpdm@11186000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_dpm2";
qcom,cmb-element-bits = <64>;
@@ -4619,6 +4628,7 @@ tpdm@111a3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pmu";
qcom,dsb-msrs-num = <32>;
@@ -4637,6 +4647,7 @@ tpdm@111a4000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qrng";
out-ports {
port {
@@ -4653,6 +4664,7 @@ tpdm@111a5000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlmm";
qcom,dsb-msrs-num = <32>;
@@ -4671,6 +4683,7 @@ tpdm@111a6000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_north_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4689,6 +4702,7 @@ tpdm@111a7000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_south_dsb";
qcom,dsb-msrs-num = <32>;
@@ -4707,6 +4721,7 @@ tpdm@111a8000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_cx";
out-ports {
port {
@@ -4723,6 +4738,7 @@ tpdm@111a9000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxa";
out-ports {
port {
@@ -4739,6 +4755,7 @@ tpdm@111aa000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_rdpm_mxc";
out-ports {
port {
@@ -4755,6 +4772,7 @@ tpdm@111ab000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb0";
out-ports {
port {
@@ -4771,6 +4789,7 @@ tpdm@111ac000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb1";
out-ports {
port {
@@ -4787,6 +4806,7 @@ tpdm@111ad000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb2";
out-ports {
port {
@@ -4803,6 +4823,7 @@ tpdm@111ae000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb3";
out-ports {
port {
@@ -4819,6 +4840,7 @@ tpdm@111af000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipcc_cmb4";
out-ports {
port {
@@ -4835,6 +4857,7 @@ tpdm@111b3000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pcie_rscc";
out-ports {
port {
@@ -5024,6 +5047,7 @@ tpdm@111d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
out-ports {
port {
@@ -5040,6 +5064,7 @@ tpdm@11303000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_4";
qcom,cmb-element-bits = <64>;
@@ -5181,6 +5206,7 @@ tpdm@11309000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
@@ -5199,6 +5225,7 @@ tpdm@1130a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
@@ -5217,6 +5244,7 @@ tpdm@1130b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
@@ -5235,6 +5263,7 @@ tpdm@1130c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
@@ -5253,6 +5282,7 @@ tpdm@1130d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -5272,6 +5302,7 @@ tpdm@11422000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ipa";
qcom,dsb-msrs-num = <32>;
@@ -6958,6 +6989,7 @@ timer {
tpdm-cdsp-llm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6971,6 +7003,7 @@ tpdm_cdsp_llm_out: endpoint {
tpdm-cdsp-llm2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm2";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6984,6 +7017,7 @@ tpdm_cdsp_llm2_out: endpoint {
tpdm-modem1 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_1";
qcom,cmb-element-bits = <32>;
out-ports {
@@ -6997,6 +7031,7 @@ tpdm_modem1_out: endpoint {
tpdm-modem2 {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_modem_2";
qcom,cmb-element-bits = <64>;
out-ports {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 4/7] arm64: dts: qcom: kodiak: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the kodiak device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/kodiak.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..3a2c28752e31 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -3513,6 +3513,7 @@ tpdm@600f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3532,6 +3533,7 @@ cti@6010000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss";
};
funnel@6041000 {
@@ -3681,6 +3683,7 @@ cti@6b00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao";
};
cti@6b01000 {
@@ -3689,6 +3692,7 @@ cti@6b01000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_1";
};
cti@6b02000 {
@@ -3697,6 +3701,7 @@ cti@6b02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_2";
};
cti@6b03000 {
@@ -3705,6 +3710,7 @@ cti@6b03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_3";
};
funnel@6b04000 {
@@ -3859,6 +3865,7 @@ tpdm@6b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3878,6 +3885,7 @@ tpdm@6b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3897,6 +3905,7 @@ tpdm@6b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3916,6 +3925,7 @@ tpdm@6b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3935,6 +3945,7 @@ tpdm@6b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3954,6 +3965,7 @@ cti@6b11000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
etm@7040000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 2/7] arm64: dts: qcom: talos: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to CTI and TPDM nodes in the talos device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/talos.dtsi | 59 +++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi
index ff5afbfce2a4..019911f3f923 100644
--- a/arch/arm64/boot/dts/qcom/talos.dtsi
+++ b/arch/arm64/boot/dts/qcom/talos.dtsi
@@ -2180,6 +2180,7 @@ cti@6010000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss";
};
cti@6011000 {
@@ -2188,6 +2189,7 @@ cti@6011000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_1";
};
cti@6012000 {
@@ -2196,6 +2198,7 @@ cti@6012000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_2";
};
cti@6013000 {
@@ -2204,6 +2207,7 @@ cti@6013000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_3";
};
cti@6014000 {
@@ -2212,6 +2216,7 @@ cti@6014000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_4";
};
cti@6015000 {
@@ -2220,6 +2225,7 @@ cti@6015000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_5";
};
cti@6016000 {
@@ -2228,6 +2234,7 @@ cti@6016000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_6";
};
cti@6017000 {
@@ -2236,6 +2243,7 @@ cti@6017000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_7";
};
cti@6018000 {
@@ -2244,6 +2252,7 @@ cti@6018000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_8";
};
cti@6019000 {
@@ -2252,6 +2261,7 @@ cti@6019000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_9";
};
cti@601a000 {
@@ -2260,6 +2270,7 @@ cti@601a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_10";
};
cti@601b000 {
@@ -2268,6 +2279,7 @@ cti@601b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_11";
};
cti@601c000 {
@@ -2276,6 +2288,7 @@ cti@601c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_12";
};
cti@601d000 {
@@ -2284,6 +2297,7 @@ cti@601d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_13";
};
cti@601e000 {
@@ -2292,6 +2306,7 @@ cti@601e000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_14";
};
cti@601f000 {
@@ -2300,6 +2315,7 @@ cti@601f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdss_15";
};
funnel@6041000 {
@@ -2532,6 +2548,7 @@ cti@683b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_qdsp6";
};
tpdm@6840000 {
@@ -2540,6 +2557,7 @@ tpdm@6840000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_vsense";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2560,6 +2578,7 @@ tpdm@684c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2579,6 +2598,7 @@ tpdm@6850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pimem";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2600,6 +2620,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2643,6 +2664,7 @@ cti@6867000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp";
};
tpdm@6870000 {
@@ -2651,6 +2673,7 @@ tpdm@6870000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2671,6 +2694,7 @@ tpdm@699c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_wcss";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2693,6 +2717,7 @@ tpdm@69c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_monaq";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2736,6 +2761,7 @@ tpdm@69d0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_qm";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2756,6 +2782,7 @@ tpdm@6a00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2776,6 +2803,7 @@ cti@6a02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl0";
};
cti@6a03000 {
@@ -2784,6 +2812,7 @@ cti@6a03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl0_1";
};
cti@6a10000 {
@@ -2792,6 +2821,7 @@ cti@6a10000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl1";
};
cti@6a11000 {
@@ -2800,6 +2830,7 @@ cti@6a11000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ddr_dl1_1";
};
funnel@6a05000 {
@@ -2870,6 +2901,7 @@ tpdm@6b02000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -2890,6 +2922,7 @@ tpdm@6b03000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -2910,6 +2943,7 @@ cti@6b04000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao";
};
cti@6b05000 {
@@ -2918,6 +2952,7 @@ cti@6b05000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_1";
};
cti@6b06000 {
@@ -2926,6 +2961,7 @@ cti@6b06000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_2";
};
cti@6b07000 {
@@ -2934,6 +2970,7 @@ cti@6b07000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_swao_3";
};
funnel@6b08000 {
@@ -3040,6 +3077,7 @@ cti@6b21000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aop_m3";
};
tpdm@6b48000 {
@@ -3048,6 +3086,7 @@ tpdm@6b48000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_west";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3067,6 +3106,7 @@ cti@6c13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_titan";
/* Not all required clocks can be enabled from the OS */
status = "fail";
@@ -3078,6 +3118,7 @@ cti@6c20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_venus";
status = "disabled";
};
@@ -3087,6 +3128,7 @@ tpdm@6c28000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_center";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3106,6 +3148,7 @@ cti@6c29000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_dlct";
};
cti@6c2a000 {
@@ -3114,6 +3157,7 @@ cti@6c2a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_dlct_1";
};
cti@7020000 {
@@ -3122,6 +3166,7 @@ cti@7020000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_2";
};
etm@7040000 {
@@ -3150,6 +3195,7 @@ cti@7120000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_3";
};
etm@7140000 {
@@ -3178,6 +3224,7 @@ cti@7220000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_4";
};
etm@7240000 {
@@ -3206,6 +3253,7 @@ cti@7320000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_5";
};
etm@7340000 {
@@ -3234,6 +3282,7 @@ cti@7420000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_6";
};
etm@7440000 {
@@ -3262,6 +3311,7 @@ cti@7520000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_7";
};
etm@7540000 {
@@ -3290,6 +3340,7 @@ cti@7620000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_8";
};
etm@7640000 {
@@ -3318,6 +3369,7 @@ cti@7720000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_apb_9";
};
etm@7740000 {
@@ -3492,6 +3544,7 @@ tpdm@7830000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_olc";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3535,6 +3588,7 @@ tpdm@7860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3578,6 +3632,7 @@ tpdm@78a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3597,6 +3652,7 @@ tpdm@78b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3664,6 +3720,7 @@ cti@78e0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss";
};
cti@78f0000 {
@@ -3672,6 +3729,7 @@ cti@78f0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_1";
};
cti@7900000 {
@@ -3680,6 +3738,7 @@ cti@7900000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss_2";
};
remoteproc_cdsp: remoteproc@8300000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 3/7] arm64: dts: qcom: monaco: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:36 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the monaco device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/monaco.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi
index 7b1d57460f1e..3e076a1df1b9 100644
--- a/arch/arm64/boot/dts/qcom/monaco.dtsi
+++ b/arch/arm64/boot/dts/qcom/monaco.dtsi
@@ -3045,6 +3045,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3307,6 +3308,7 @@ tpdm@4841000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_prng";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3326,6 +3328,7 @@ tpdm@4850000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_pimem";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3347,6 +3350,7 @@ tpdm@4860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_ch_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3440,6 +3444,7 @@ tpdm@4980000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3483,6 +3488,7 @@ tpdm@4ac0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_mmnoc_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3555,6 +3561,7 @@ tpdm@4ad0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dlct";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3807,6 +3814,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3826,6 +3834,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3845,6 +3854,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3864,6 +3874,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3883,6 +3894,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3902,6 +3914,7 @@ cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
tpdm@4b80000 {
@@ -3910,6 +3923,7 @@ tpdm@4b80000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_cdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3977,6 +3991,7 @@ cti@4b8b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_cdsp_1";
};
tpdm@4c40000 {
@@ -3985,6 +4000,7 @@ tpdm@4c40000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_gpdsp_0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4078,6 +4094,7 @@ tpdm@4c50000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dl_south";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4150,6 +4167,7 @@ tpdm@4e00000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4240,6 +4258,7 @@ tpdm@4e10000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_ch0";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4283,6 +4302,7 @@ tpdm@4e20000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ddr_ch1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4608,6 +4628,7 @@ cti@682b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_apss";
};
tpdm@6860000 {
@@ -4616,6 +4637,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -4635,6 +4657,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4715,6 +4738,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4734,6 +4758,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -4753,6 +4778,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_ext_dsb";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -4772,6 +4798,7 @@ cti@68e0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_llm_gold";
};
cti@68f0000 {
@@ -4780,6 +4807,7 @@ cti@68f0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_llm_silver";
};
cti@6900000 {
@@ -4788,6 +4816,7 @@ cti@6900000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_ext_dsb";
};
sdhc_1: mmc@87c4000 {
--
2.34.1
^ permalink raw reply related
* [PATCH v2 1/7] arm64: dts: qcom: lemans: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
In-Reply-To: <20260414-add-label-to-coresight-device-v2-0-5017d07358f2@oss.qualcomm.com>
Add label properties to TPDM and CTI nodes in the lemans device tree to
provide human-readable identifiers for each CoreSight device. These
labels allow userspace tools and the CoreSight framework to identify
devices by name rather than by base address.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
index fe6e76351823..7cdca20708cc 100644
--- a/arch/arm64/boot/dts/qcom/lemans.dtsi
+++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
@@ -2847,6 +2847,7 @@ tpdm@4003000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_dcc";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -2906,6 +2907,7 @@ tpdm@400f000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_spdm";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3374,6 +3376,7 @@ tpdm@4b09000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_0";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3394,6 +3397,7 @@ tpdm@4b0a000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_1";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3414,6 +3418,7 @@ tpdm@4b0b000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_2";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3434,6 +3439,7 @@ tpdm@4b0c000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_prio_3";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3454,6 +3460,7 @@ tpdm@4b0d000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_swao_1";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3474,6 +3481,7 @@ aoss_cti: cti@4b13000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "cti_aoss";
};
funnel@4b83000 {
@@ -3795,6 +3803,7 @@ tpdm@6860000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_actpm";
qcom,cmb-element-bits = <64>;
qcom,cmb-msrs-num = <32>;
@@ -3815,6 +3824,7 @@ tpdm@6861000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_apss";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -3897,6 +3907,7 @@ tpdm@68a0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_silver";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3917,6 +3928,7 @@ tpdm@68b0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_gold";
qcom,cmb-element-bits = <32>;
qcom,cmb-msrs-num = <32>;
@@ -3937,6 +3949,7 @@ tpdm@68c0000 {
clocks = <&aoss_qmp>;
clock-names = "apb_pclk";
+ label = "tpdm_llm_ext";
qcom,dsb-element-bits = <32>;
qcom,dsb-msrs-num = <32>;
@@ -8590,6 +8603,7 @@ arch_timer: timer {
turing-llm-tpdm {
compatible = "qcom,coresight-static-tpdm";
+ label = "tpdm_cdsp_llm_0";
qcom,cmb-element-bits = <32>;
--
2.34.1
^ permalink raw reply related
* [PATCH v2 0/7] arm64: dts: qcom: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:35 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan, Konrad Dybcio
The CoreSight framework and userspace tools identify trace devices by
their base address, which is not human-readable. The label property
provides a stable, descriptive name for each TPDM and CTI device,
allowing tools to refer to devices by name rather than address.
This series adds label properties to TPDM and CTI nodes across seven
Qualcomm platforms:
lemans
talos
monaco
kodiak
kaanapali
sm8750
hamoa
With the change, we will have a sysfs node for each Coresight device:
root@qemuarm64:/sys/bus/coresight/devices/tpdm0# cat label
tpdm_spdm
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Changes in v2:
- fix the extra tab format issue in patch 6 (sm8750).
- Link to v1: https://lore.kernel.org/r/20260410-add-label-to-coresight-device-v1-0-d71a6759dbc2@oss.qualcomm.com
---
Jie Gan (7):
arm64: dts: qcom: lemans: Add label properties to CoreSight devices
arm64: dts: qcom: talos: Add label properties to CoreSight devices
arm64: dts: qcom: monaco: Add label properties to CoreSight devices
arm64: dts: qcom: kodiak: Add label properties to CoreSight devices
arm64: dts: qcom: kaanapali: Add label properties to CoreSight devices
arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
arm64: dts: qcom: hamoa: Add label properties to CoreSight devices
arch/arm64/boot/dts/qcom/hamoa.dtsi | 30 +++++++++++++++++
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 35 +++++++++++++++++++
arch/arm64/boot/dts/qcom/kodiak.dtsi | 12 +++++++
arch/arm64/boot/dts/qcom/lemans.dtsi | 14 ++++++++
arch/arm64/boot/dts/qcom/monaco.dtsi | 29 ++++++++++++++++
arch/arm64/boot/dts/qcom/sm8750.dtsi | 27 +++++++++++++++
arch/arm64/boot/dts/qcom/talos.dtsi | 59 +++++++++++++++++++++++++++++++++
7 files changed, 206 insertions(+)
---
base-commit: f3e6330d7fe42b204af05a2dbc68b379e0ad179e
change-id: 20260409-add-label-to-coresight-device-b17a2ba6030e
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH 6/7] arm64: dts: qcom: sm8750: Add label properties to CoreSight devices
From: Jie Gan @ 2026-04-14 11:29 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <6187fa72-d14c-40a1-bc03-ba43860d0e27@oss.qualcomm.com>
On 4/14/2026 6:19 PM, Konrad Dybcio wrote:
> On 4/10/26 5:08 AM, Jie Gan wrote:
>> Add label properties to TPDM and CTI nodes in the sm8750 device tree to
>> provide human-readable identifiers for each CoreSight device. These
>> labels allow userspace tools and the CoreSight framework to identify
>> devices by name rather than by base address.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>
> [...]
>
>> tpdm-cdsp-llm {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_cdsp_llm";
>> qcom,cmb-element-bits = <32>;
>>
>> out-ports {
>> @@ -6814,6 +6839,7 @@ tpdm_cdsp_llm_out: endpoint {
>>
>> tpdm-cdsp-llm2 {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_cdsp_llm2";
>> qcom,cmb-element-bits = <32>;
>>
>> out-ports {
>> @@ -6827,6 +6853,7 @@ tpdm_cdsp_llm2_out: endpoint {
>>
>> tpdm-modem1 {
>> compatible = "qcom,coresight-static-tpdm";
>> + label = "tpdm_modem_1";
>
> Please fix the extra \t
noted.
Thanks,
Jie
>
> Konrad
^ permalink raw reply
* Re: [PATCH v11 2/4] crypto: spacc - Add SPAcc ahash support
From: Herbert Xu @ 2026-04-14 11:16 UTC (permalink / raw)
To: Pavitrakumar Managutte
Cc: linux-crypto, linux-kernel, devicetree, robh, conor+dt,
Ruud.Derwig, manjunath.hadli, adityak, navami.telsang, bhoomikak
In-Reply-To: <CALxtO0kj4JfL94qY-radGcLwMeTnq4NQF7vPqs6giuhBinvALw@mail.gmail.com>
On Tue, Apr 14, 2026 at 03:58:16PM +0530, Pavitrakumar Managutte wrote:
> Hi Herbert,
> If the above snip looks good, I can push that and some more code
> clean-ups/improvements as part of V12 patchset. Do let me know.
>
> Below are the code fixes and improvements
> 1. Multi-device safety handling - All packed up inside priv
> 2. Minor code polishes
> 3. memzero_explicit inside setkey, spacc_compute_xcbc_key etc.
> 4. Algo registration clean-ups
I would prefer if you left out sm3 for now. If it really mattered
someone would move it to lib/crypto.
Thanks,
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* Re: [PATCH 31/35] arm64: dts: qcom: milos: Drop unused second PDC reg entry
From: Krzysztof Kozlowski @ 2026-04-14 10:57 UTC (permalink / raw)
To: Mukesh Ojha, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio
Cc: cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260410184124.1068210-32-mukesh.ojha@oss.qualcomm.com>
On 10/04/2026 20:41, Mukesh Ojha wrote:
> The PDC driver only maps the first register region (APSS DRV) via
> of_address_to_resource(node, 0, ...). The second reg entry was never
> accessed by the driver and can be removed.
>
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/milos.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 71941e6f49bf..a3c2ac8ca675 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -1564,8 +1564,7 @@ dispcc: clock-controller@af00000 {
>
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,milos-pdc", "qcom,pdc";
> - reg = <0x0 0x0b220000 0x0 0x10000>,
You already changed this line in previous patch. Fixing one property in
DTS to match hardware is one commit.
Best regards,
Krzysztof
^ permalink raw reply
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