* RE: [PATCH v3 6/8] iio: core: Add IIO_COVERAGE channel type
From: Stan, Liviu @ 2026-05-22 9:57 UTC (permalink / raw)
To: Stan, Liviu, Jonathan Cameron, David Lechner, Sa, Nuno,
Andy Shevchenko, Hennerich, Michael, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Miclaus, Antoniu,
Francesco Lavra, linux-iio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux, devicetree@vger.kernel.org
In-Reply-To: <20260521164323.770626-7-liviu.stan@analog.com>
Hello everyone, I'll reply to sashiko's review here:
On Thu, 21 May 2026 18:10:28 +0000 sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The sysfs ABI documentation for IIO_COVERAGE incorrectly uses 'X' instead of 'Y' as the channel index wildcard.
> --
>
> commit 6217a0a065fdaa7ef3fffa525f2928d59a323a05
> Author: Liviu Stan <liviu.stan@analog.com>
> iio: core: Add IIO_COVERAGE channel type
>
> This commit introduces a new channel type for sensors that report fractional
> coverage as a percentage. It updates the core IIO structures and provides
> the necessary sysfs ABI documentation for the new attributes.
>
> > diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
> > index 4fc9f6bd42812..90fb8ef26de0e 100644
> > --- a/Documentation/ABI/testing/sysfs-bus-iio
> > +++ b/Documentation/ABI/testing/sysfs-bus-iio
> > @@ -1959,6 +1959,23 @@ Description:
> > Raw (unscaled no offset etc.) resistance reading.
> > Units after application of scale and offset are ohms.
> >
> > +What: /sys/bus/iio/devices/iio:deviceX/in_coverageX_raw
>
> [Severity: Low]
> Should this use Y for the channel index wildcard instead of X? The IIO sysfs
> ABI documentation typically uses X strictly for the device index and Y for the
> channel index, which would make this in_coverageY_raw.
>
> > +KernelVersion: 7.2
> > +Contact: linux-iio@vger.kernel.org
> > +Description:
> > + Raw (unscaled no offset etc.) coverage reading. Used for sensors
> > + that report fractional coverage as a percentage, such as leak
> > + detectors where the value represents what portion of the sensing
> > + element is wetted. Units after application of scale and offset are
> > + percent.
> > +
> > +What: /sys/bus/iio/devices/iio:deviceX/in_coverageX_scale
>
> [Severity: Low]
> Does this attribute have the same naming consistency issue? Following the
> standard convention, this would be in_coverageY_scale.
>
> --
> Sashiko AI review * https://sashiko.dev/#/patchset/20260521164323.770626-1-liviu.stan@analog.com?part=6
>
I see now that other attributes have Y as the channel index wildcard.
Will change
Thanks,
Liviu
^ permalink raw reply
* Re: [PATCH] arm64: dts: glymur-crd: Add reset GPIO to touchscreen node
From: Konrad Dybcio @ 2026-05-22 10:00 UTC (permalink / raw)
To: Pradyot Kumar Nayak, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Abel Vesa, Dmitry Baryshkov
Cc: linux-arm-msm, devicetree, linux-kernel,
20260519-glymur-mahua-common-nodes-v2-1-9f1b89a3f398
In-Reply-To: <20260522-arm64-dts-glymur-crd-add-reset-gpio-to-touchscreen-v1-1-c7653924acdc@oss.qualcomm.com>
On 5/22/26 11:56 AM, Pradyot Kumar Nayak wrote:
> The touchscreen module on Glymur/Mahua CRDs is different from the one
> used on Hamoa CRDs and requires the reset-gpios to be wired to the device.
> Without this in place the reset line will remain permanently asserted
> during resume leaving the device offline and causing all I2C transactions
> to fail with -ENXIO.
>
> Error Logs:
> i2c_hid_of 3-0038: failed to change power setting.
> i2c_hid_of 3-0038: PM: dpm_run_callback(): i2c_hid_core_pm_resume [i2c_hid] returns -6
> i2c_hid_of 3-0038: PM: failed to resume async: error -6
>
> Add the reset GPIO so the driver can deassert the line on resume,
> restoring I2C communication with the device.
>
> Fixes: e6bf559f7eb9 ("arm64: dts: qcom: glymur-crd: Enable keyboard, trackpad and touchscreen")
> Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* [PATCH] arm64: dts: qcom: Add Display Port audio on Arduino Monza
From: Srinivas Kandagatla @ 2026-05-22 10:00 UTC (permalink / raw)
To: andersson
Cc: konradybcio, robh, krzk+dt, conor+dt, linux-arm-msm, devicetree,
linux-kernel, Srinivas Kandagatla, Loic Poulain
Add support for Display port Audio on Arduino VENTUNO-Q board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
CC: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
alsa tplg changes are:
https://github.com/linux-msm/audioreach-topology/pull/63
Ucm changes are:
https://github.com/Srinivas-Kandagatla/alsa-ucm-conf/tree/ventuno-q
.../arm64/boot/dts/qcom/monaco-arduino-monza.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
index ca14f0ea4dae..01acc8363cbb 100644
--- a/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-arduino-monza.dts
@@ -117,6 +117,22 @@ platform {
sound-dai = <&q6apm>;
};
};
+
+ displayport-0-dai-link {
+ link-name = "DisplayPort0 Playback";
+
+ codec {
+ sound-dai = <&mdss_dp0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
};
vdc_3v3: regulator-3v3 {
--
2.47.3
^ permalink raw reply related
* [PATCH 0/3] spacemit: k1: Add support for Banana Pi BPI-CM6 IO board
From: Junhui Liu @ 2026-05-22 10:01 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Vivian Wang, Paolo Abeni, Guodong Xu, Yangyu Chen
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Junhui Liu
This adds initial support for the Banana Pi BPI-CM6 IO board. The
BPI-CM6 is an industrial-grade RISC-V compute module powered by the
SpacemiT K1 SoC, featuring board-to-board connectors similar to the
Raspberry Pi CM4 form factor. For evaluation and development, the module
is paired with a companion IO carrier board.
During the board bring-up, GPIO45 and GPIO46 were found to be used by
the BPI-CM6 hardware as Ethernet PHY reset GPIOs, while the common K1
GMAC pinctrl groups currently mux them as optional GMAC reference clock
pins. Since the reference clock pins are not required on all K1 boards,
the first patch separates them into independent pinctrl groups so board
DTS files can select them only when the signal is actually wired.
This is based on the "dt-for-next" branch of the spacemit-com/linux.
Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Junhui Liu (3):
dt-bindings: riscv: spacemit: Add Banana Pi BPI-CM6 compatible
riscv: dts: spacemit: k1: Split gmac_clk_ref into independent pinctrl groups
riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board
.../devicetree/bindings/riscv/spacemit.yaml | 5 +
arch/riscv/boot/dts/spacemit/Makefile | 1 +
.../riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts | 215 +++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 227 +++++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 24 ++-
5 files changed, 468 insertions(+), 4 deletions(-)
---
base-commit: 6edd9a0d32e1ef81133b8cb5b3bb3157a44da4d1
change-id: 20260522-bpi-cm6-dc38f91e3fec
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply
* [PATCH 1/3] dt-bindings: riscv: spacemit: Add Banana Pi BPI-CM6 compatible
From: Junhui Liu @ 2026-05-22 10:01 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Vivian Wang, Paolo Abeni, Guodong Xu, Yangyu Chen
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Junhui Liu
In-Reply-To: <20260522-bpi-cm6-v1-0-707ef1917a30@pigmoral.tech>
The Banana Pi BPI-CM6 IO board consists of the BPI-CM6 compute module
plugged into an IO carrier board, which is used for evaluation and
development.
The core CM6 module is based on the SpacemiT K1 SoC and provides PMIC,
DDR, the eth0 PHY and wireless connectivity. The carrier board extends
this by adding the eth1 PHY and external interfaces including Ethernet,
PCIe M.2, USB, MicroSD, QSPI, and serial console connectivity.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
Documentation/devicetree/bindings/riscv/spacemit.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml
index af8030242bdc..3e868383eb4a 100644
--- a/Documentation/devicetree/bindings/riscv/spacemit.yaml
+++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml
@@ -19,6 +19,11 @@ properties:
const: '/'
compatible:
oneOf:
+ - items:
+ - enum:
+ - bananapi,bpi-cm6-io
+ - const: bananapi,bpi-cm6
+ - const: spacemit,k1
- items:
- enum:
- bananapi,bpi-f3
--
2.54.0
^ permalink raw reply related
* [PATCH 2/3] riscv: dts: spacemit: k1: Split gmac_clk_ref into independent pinctrl groups
From: Junhui Liu @ 2026-05-22 10:01 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Vivian Wang, Paolo Abeni, Guodong Xu, Yangyu Chen
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Junhui Liu
In-Reply-To: <20260522-bpi-cm6-v1-0-707ef1917a30@pigmoral.tech>
The gmac_clk_ref signal is optional for the GMAC controller and is not
strictly required for all hardware designs. In several already
upstreamed K1 boards, this signal remains unconnected or the
corresponding resistor is marked as NC.
Furthermore, the pins for gmac0_clk_ref (GPIO 45) and gmac1_clk_ref
(GPIO 46) may be used as GPIOs for other functions even when the
Ethernet controller is active. Splitting these into independent groups
avoids pinmux conflicts and allows boards to use the reference clock
signal only when it is actually needed.
Fixes: 60775f28cfb7 ("riscv: dts: spacemit: Add Ethernet support for K1")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index 4e9a62d0e85b..8c57ca05dabd 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -27,8 +27,16 @@ gmac0-pins {
<K1_PADCONF(11, 1)>, /* gmac0_tx_en */
<K1_PADCONF(12, 1)>, /* gmac0_mdc */
<K1_PADCONF(13, 1)>, /* gmac0_mdio */
- <K1_PADCONF(14, 1)>, /* gmac0_int_n */
- <K1_PADCONF(45, 1)>; /* gmac0_clk_ref */
+ <K1_PADCONF(14, 1)>; /* gmac0_int_n */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ gmac0_clk_ref_cfg: gmac0-clk-ref-cfg {
+ gmac0-clk-ref-pins {
+ pinmux = <K1_PADCONF(45, 1)>; /* gmac0_clk_ref */
bias-pull-up = <0>;
drive-strength = <21>;
@@ -51,8 +59,16 @@ gmac1-pins {
<K1_PADCONF(40, 1)>, /* gmac1_tx_en */
<K1_PADCONF(41, 1)>, /* gmac1_mdc */
<K1_PADCONF(42, 1)>, /* gmac1_mdio */
- <K1_PADCONF(43, 1)>, /* gmac1_int_n */
- <K1_PADCONF(46, 1)>; /* gmac1_clk_ref */
+ <K1_PADCONF(43, 1)>; /* gmac1_int_n */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ gmac1_clk_ref_cfg: gmac1-clk-ref-cfg {
+ gmac1-clk-ref-pins {
+ pinmux = <K1_PADCONF(46, 1)>; /* gmac1_clk_ref */
bias-pull-up = <0>;
drive-strength = <21>;
--
2.54.0
^ permalink raw reply related
* [PATCH 0/3] ASoC: rockchip: Reorder clock enable sequence
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail.com>
Hi all,
This series reorders the runtime resume clock enable
sequence in the Rockchip SPDIF and PDM drivers to enable
the bus clock before the functional controller clock.
It also updates the SPDIF DT binding clock descriptions to
match the actual clock usage in the driver.
Best Regards,
Phuc
bui duc phuc (3):
ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
ASoC: rockchip: spdif: Reorder clock enable sequence
ASoC: rockchip: rockchip_pdm: Reorder clock enable sequence
.../devicetree/bindings/sound/rockchip-spdif.yaml | 2 +-
sound/soc/rockchip/rockchip_pdm.c | 10 +++++-----
sound/soc/rockchip/rockchip_spdif.c | 10 +++++-----
3 files changed, 11 insertions(+), 11 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH 1/3] ASoC: dt-bindings: rockchip-spdif: Correct SPDIF clock descriptions
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
In-Reply-To: <20260522100318.73474-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
The clock descriptions are currently swapped relative to the
clock names used by the driver.
Update the binding descriptions to match the actual clock
usage, where 'mclk' is the controller clock and 'hclk' is
the bus clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
Documentation/devicetree/bindings/sound/rockchip-spdif.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
index 502907dd28b3..b174d7498029 100644
--- a/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
+++ b/Documentation/devicetree/bindings/sound/rockchip-spdif.yaml
@@ -45,8 +45,8 @@ properties:
clocks:
items:
- - description: clock for SPDIF bus
- description: clock for SPDIF controller
+ - description: clock for SPDIF bus
clock-names:
items:
--
2.43.0
^ permalink raw reply related
* [PATCH 2/3] ASoC: rockchip: spdif: Reorder clock enable sequence
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
In-Reply-To: <20260522100318.73474-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Enable the 'hclk' bus clock before the 'mclk' controller
clock during runtime resume.
The bus clock provides the register access interface and
should be enabled before the controller clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/rockchip/rockchip_spdif.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_spdif.c b/sound/soc/rockchip/rockchip_spdif.c
index 581624f2682e..8de5b76cfe79 100644
--- a/sound/soc/rockchip/rockchip_spdif.c
+++ b/sound/soc/rockchip/rockchip_spdif.c
@@ -76,16 +76,16 @@ static int rk_spdif_runtime_resume(struct device *dev)
struct rk_spdif_dev *spdif = dev_get_drvdata(dev);
int ret;
- ret = clk_prepare_enable(spdif->mclk);
+ ret = clk_prepare_enable(spdif->hclk);
if (ret) {
- dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
+ dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(spdif->hclk);
+ ret = clk_prepare_enable(spdif->mclk);
if (ret) {
- clk_disable_unprepare(spdif->mclk);
- dev_err(spdif->dev, "hclk clock enable failed %d\n", ret);
+ clk_disable_unprepare(spdif->hclk);
+ dev_err(spdif->dev, "mclk clock enable failed %d\n", ret);
return ret;
}
--
2.43.0
^ permalink raw reply related
* [PATCH 3/3] riscv: dts: spacemit: k1: Add Banana Pi BPI-CM6 IO board
From: Junhui Liu @ 2026-05-22 10:01 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Yixun Lan,
Vivian Wang, Paolo Abeni, Guodong Xu, Yangyu Chen
Cc: devicetree, linux-riscv, spacemit, linux-kernel, Junhui Liu
In-Reply-To: <20260522-bpi-cm6-v1-0-707ef1917a30@pigmoral.tech>
The Banana Pi BPI-CM6 IO board combines the BPI-CM6 compute module with
an IO carrier board. The core module integrates the SpacemiT K1 SoC,
PMIC, DDR, eMMC, the eth0 PHY, and wireless connectivity. The companion
IO carrier board extends it by providing the eth1 PHY and exposing
standard interfaces, including dual Gigabit Ethernet, MicroSD, two USB-A
ports, a USB Type-C port, two PCIe M.2 slots, and a serial console.
The board also has two I2C EEPROMs. One is on the core module, which
stores factory manufacturing data and is marked read-only. The other is
on the carrier board, which is shipped unprogrammed and left writable
for evaluation purposes.
Add initial support for UART console, eMMC, SD card, I2C, EEPROMs,
PCIe, USB, and dual Ethernet interfaces.
Link: https://docs.banana-pi.org/en/BPI-CM6/BananaPi_BPI-CM6
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
arch/riscv/boot/dts/spacemit/Makefile | 1 +
.../riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts | 215 +++++++++++++++++++
arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi | 227 +++++++++++++++++++++
3 files changed, 443 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/Makefile b/arch/riscv/boot/dts/spacemit/Makefile
index acb993c452ba..dd6125dc2012 100644
--- a/arch/riscv/boot/dts/spacemit/Makefile
+++ b/arch/riscv/boot/dts/spacemit/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-cm6-io.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-bananapi-f3.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts
new file mode 100644
index 000000000000..b2767f44e8d6
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6-io.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "k1-bananapi-cm6.dtsi"
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Banana Pi BPI-CM6 IO Board";
+ compatible = "bananapi,bpi-cm6-io", "bananapi,bpi-cm6", "spacemit,k1";
+
+ aliases {
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led0 {
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_LOW>;
+ };
+
+ led1 {
+ color = <LED_COLOR_ID_BLUE>;
+ gpios = <&gpio K1_GPIO(97) GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ vdd_sys_12v: regulator-vdd-sys-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SYS";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vdd_5v0: regulator-vdd-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_5V0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vdd_sys_12v>;
+ };
+
+ pcie_vcc_3v3: regulator-pcie-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "NGFF_KEYM_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vdd_sys_12v>;
+ };
+
+ usb_vbus_5v: regulator-usb-vbus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VBUS_A_B";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio K1_GPIO(124) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_vdd_5v0>;
+ };
+
+ reg_vdd_3v3: regulator-vdd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vdd_sys_12v>;
+ };
+
+ sd_vcc_3v3: regulator-sd-vcc-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3VS_CARD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio K1_GPIO(127) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_vdd_3v3>;
+ };
+};
+
+&combo_phy {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+};
+
+ð1 {
+ nvmem-cells = <&mac_address 1>;
+ nvmem-cell-names = "mac-address";
+ phy-handle = <&rgmii1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_cfg>;
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <250>;
+ status = "okay";
+
+ mdio-bus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ reset-gpios = <&gpio K1_GPIO(46) GPIO_ACTIVE_LOW>;
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <100000>;
+
+ rgmii1: phy@1 {
+ reg = <0x1>;
+ };
+ };
+};
+
+&i2c2 {
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ vcc-supply = <&buck3_1v8>;
+ pagesize = <16>;
+ size = <1024>;
+ };
+};
+
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_port {
+ phys = <&pcie1_phy>;
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie1 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie2_port {
+ phys = <&pcie2_phy>;
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+};
+
+&pcie2 {
+ vpcie3v3-supply = <&pcie_vcc_3v3>;
+ status = "okay";
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_cfg>;
+ status = "okay";
+};
+
+&sdhci0 {
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&mmc1_cfg>;
+ pinctrl-1 = <&mmc1_uhs_cfg>;
+ bus-width = <4>;
+ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ no-mmc;
+ no-sdio;
+ disable-wp;
+ cap-sd-highspeed;
+ vmmc-supply = <&sd_vcc_3v3>;
+ vqmmc-supply = <&aldo1>;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_2_cfg>;
+ status = "okay";
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+&usb_dwc3 {
+ dr_mode = "host";
+ vbus-supply = <&usb_vbus_5v>;
+ status = "okay";
+};
+
+&vddin_sys_5v {
+ vin-supply = <®_vdd_5v0>;
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
new file mode 100644
index 000000000000..9b91128edb34
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-cm6.dtsi
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2026 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include "k1.dtsi"
+#include "k1-pinctrl.dtsi"
+
+/ {
+ model = "Banana Pi BPI-CM6 Module";
+ compatible = "bananapi,bpi-cm6", "spacemit,k1";
+
+ aliases {
+ i2c2 = &i2c2;
+ i2c8 = &i2c8;
+ };
+
+ vddin_sys_5v: regulator-vddin-sys-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIN_SYS";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_vcc_4v: regulator-vcc-4v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC4V0_SYS";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ vin-supply = <&vddin_sys_5v>;
+ };
+};
+
+&emmc {
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+ð0 {
+ nvmem-cells = <&mac_address 0>;
+ nvmem-cell-names = "mac-address";
+ phy-handle = <&rgmii0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_cfg>;
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+
+ mdio-bus {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ reset-gpios = <&gpio K1_GPIO(45) GPIO_ACTIVE_LOW>;
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <100000>;
+
+ rgmii0: phy@1 {
+ reg = <0x1>;
+ };
+ };
+};
+
+&pdma {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_0_cfg>;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ vcc-supply = <&buck3_1v8>;
+ pagesize = <16>;
+ read-only;
+ size = <256>;
+
+ nvmem-layout {
+ compatible = "onie,tlv-layout";
+
+ mac_address: mac-address {
+ #nvmem-cell-cells = <1>;
+ };
+
+ num-macs {
+ };
+
+ serial-number {
+ };
+ };
+ };
+};
+
+&i2c8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8_cfg>;
+ status = "okay";
+
+ pmic@41 {
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ vin1-supply = <®_vcc_4v>;
+ vin2-supply = <®_vcc_4v>;
+ vin3-supply = <®_vcc_4v>;
+ vin4-supply = <®_vcc_4v>;
+ vin5-supply = <®_vcc_4v>;
+ vin6-supply = <®_vcc_4v>;
+ aldoin-supply = <®_vcc_4v>;
+ dldoin1-supply = <&buck5>;
+ dldoin2-supply = <&buck5>;
+
+ regulators {
+ buck1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5: buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1: aldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+};
--
2.54.0
^ permalink raw reply related
* [PATCH 3/3] ASoC: rockchip: rockchip_pdm: Reorder clock enable sequence
From: phucduc.bui @ 2026-05-22 10:03 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, perex, tiwai, heiko, linux-arm-kernel, linux-kernel,
linux-sound, linux-rockchip, robh, krzk+dt, conor+dt, devicetree,
bui duc phuc
In-Reply-To: <20260522100318.73474-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Enable the 'hclk' bus clock before the 'clk' controller
clock during runtime resume.
The bus clock provides the register access interface and
should be enabled before the controller clock.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/rockchip/rockchip_pdm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c
index c69cdd6f2499..8f78f7bc1806 100644
--- a/sound/soc/rockchip/rockchip_pdm.c
+++ b/sound/soc/rockchip/rockchip_pdm.c
@@ -422,16 +422,16 @@ static int rockchip_pdm_runtime_resume(struct device *dev)
struct rk_pdm_dev *pdm = dev_get_drvdata(dev);
int ret;
- ret = clk_prepare_enable(pdm->clk);
+ ret = clk_prepare_enable(pdm->hclk);
if (ret) {
- dev_err(pdm->dev, "clock enable failed %d\n", ret);
+ dev_err(pdm->dev, "hclock enable failed %d\n", ret);
return ret;
}
- ret = clk_prepare_enable(pdm->hclk);
+ ret = clk_prepare_enable(pdm->clk);
if (ret) {
- clk_disable_unprepare(pdm->clk);
- dev_err(pdm->dev, "hclock enable failed %d\n", ret);
+ clk_disable_unprepare(pdm->hclk);
+ dev_err(pdm->dev, "clock enable failed %d\n", ret);
return ret;
}
--
2.43.0
^ permalink raw reply related
* [PATCH] ARM: dts: aspeed: clemente: Remove IOB NIC TMP421 nodes
From: Mike Hsieh @ 2026-05-22 10:07 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Cosmo Chou, Potin Lai, Mike Hsieh, Mike Hsieh
Remove the TMP421 sensor entry from the DTS, as it is no longer the
primary telemetry source.
Accessing the CX8 NIC via I2C while it is powered off causes voltage
leakage on the bus, leading to EEPROM corruption on shared I2C devices.
Removing this node prevents the BMC from initiating traffic to the NIC
during initialization, protecting the integrity of the shared bus.
Signed-off-by: Mike Hsieh <mike.quanta.115@gmail.com>
---
Remove the TMP421 sensor entry from the DTS, as it is no longer the
primary telemetry source.
Accessing the CX8 NIC via I2C while it is powered off causes voltage
leakage on the bus, leading to EEPROM corruption on shared I2C devices.
Removing this node prevents the BMC from initiating traffic to the NIC
during initialization, protecting the integrity of the shared bus.
---
.../boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
index 2aff21442f11..820d39a92974 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
@@ -443,11 +443,6 @@ i2c0mux2ch0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- // IOB0 NIC0 TEMP
- temperature-sensor@1f {
- compatible = "ti,tmp421";
- reg = <0x1f>;
- };
};
i2c0mux2ch1: i2c@1 {
@@ -466,11 +461,6 @@ i2c0mux2ch3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- // IOB0 NIC1 TEMP
- temperature-sensor@1f {
- compatible = "ti,tmp421";
- reg = <0x1f>;
- };
};
};
@@ -637,11 +627,6 @@ i2c0mux5ch0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- // IOB1 NIC0 TEMP
- temperature-sensor@1f {
- compatible = "ti,tmp421";
- reg = <0x1f>;
- };
};
i2c0mux5ch1: i2c@1 {
@@ -666,11 +651,6 @@ i2c0mux5ch3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- // IOB1 NIC1 TEMP
- temperature-sensor@1f {
- compatible = "ti,tmp421";
- reg = <0x1f>;
- };
};
};
};
---
base-commit: 6779b50faa562e6cca1aa6a4649a4d764c6c7e28
change-id: 20260522-clemente-dts-remove-iob-nic-tmp421-89221ba96dd7
Best regards,
--
Mike Hsieh <mike.quanta.115@gmail.com>
^ permalink raw reply related
* Re: [PATCH RESEND] ARM: dts: qcom: msm8960: expressatt: Add coreriver,tc360-touchkey
From: Konrad Dybcio @ 2026-05-22 10:08 UTC (permalink / raw)
To: guptarud, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260503-expressatt-touchkey-v1-1-f7dd5db64e0d@gmail.com>
On 5/3/26 11:24 PM, Rudraksha Gupta via B4 Relay wrote:
> From: Rudraksha Gupta <guptarud@gmail.com>
>
> Add the tc360 touchkey. It's unknown if this is the actual model of the
> touchkey, as downstream doesn't mention a variant, but this works.
>
> Link:
> https://github.com/LineageOS/android_kernel_samsung_d2/blob/stable/cm-12.0-YNG4N/drivers/input/keyboard/cypress_touchkey_236/Makefile#L5
>
> Signed-off-by: Rudraksha Gupta <guptarud@gmail.com>
> ---
[...]
> + i2c-gpio-touchkey {
> + compatible = "i2c-gpio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + sda-gpios = <&tlmm 71 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&tlmm 72 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&touchkey_i2c_pins>;
property-n
property-names
in this order, please, everywhere
> + status = "okay";
Drop this line, it's "okay" by default if nothing else explicitly disables
the node
Konrad
^ permalink raw reply
* Re: [PATCH v6 01/10] dt-bindings: dma: nvidia,tegra186-gpc-dma: Make reset optional
From: Thierry Reding @ 2026-05-22 10:09 UTC (permalink / raw)
To: Akhil R
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Hunter, Laxman Dewangan, Philipp Zabel,
dmaengine, devicetree, linux-tegra, linux-kernel
In-Reply-To: <20260331102303.33181-2-akhilrajeev@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1081 bytes --]
On Tue, Mar 31, 2026 at 03:52:54PM +0530, Akhil R wrote:
> On Tegra264, GPCDMA reset control is not exposed to Linux and is handled
> by the boot firmware.
>
> Although reset was not exposed in Tegra234 as well, the firmware supported
> a dummy reset which just returns success on reset without doing an actual
> reset. This is also not supported in Tegra264 BPMP. Therefore mark 'reset'
> and 'reset-names' properties as required only for devices prior to
> Tegra264.
>
> This also necessitates that the Tegra264 compatible be standalone and
> cannot have the fallback compatible of Tegra186. Since there is no
> functional impact, we keep reset as required for Tegra234 to avoid
> breaking the ABI.
>
> Fixes: bb8c97571db5 ("dt-bindings: dma: Add Tegra264 compatible string")
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
> .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 23 +++++++++++++------
> 1 file changed, 16 insertions(+), 7 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply
* Re: [PATCH 01/35] dt-bindings: qcom,pdc: Tighten reg to single APSS DRV region
From: Konrad Dybcio @ 2026-05-22 10:09 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Mukesh Ojha, Thomas Gleixner, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson, Konrad Dybcio,
cros-qcom-dts-watchers, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <5z7zoybn2gqsyn3zqvjo7saq2zjpoimkp67ubqenlntzcweyz3@rkm36ya6j44f>
On 4/14/26 6:23 PM, Dmitry Baryshkov wrote:
> On Mon, Apr 13, 2026 at 10:23:59AM +0200, Konrad Dybcio wrote:
>> On 4/11/26 4:32 PM, Dmitry Baryshkov wrote:
>>> On Sat, Apr 11, 2026 at 12:10:38AM +0530, Mukesh Ojha wrote:
>>>> The PDC has multiple DRV regions, each sized 0x10000, where each region
>>>> serves a specific client in the system. Linux only needs access to the
>>>
>>> Nit: there are other OS than Linux. Would you rather point out that
>>> other DRV regions are to be used by ... what?
>>
>> TZ, HYP, HLOS, CPUCP..
>
> => commit message
>
>>
>> I'm wondering if we can make use of the HYP one on e.g. Glymur, to
>> parallelize accesses (and whether that would bring any practical
>> benefit).
>>
>> In the RPMH architecture, each "client" has their own (GPU, AOP, DISP,
>> etc.). Then, each one of those clients may have an associates RSC
>> (Resource State Coordinator) and/or anyOf BCM ("interconnect"), VRM
>> ("regulator"), ARC ("RPMHPD") voting interfaces
>
> At least the RSC should be visible to the OS. We don't use it (now), but
> we probably will at some point (at least the DISP_RSC) if I understand
> it correctly.
The display RSC is a separate instance, living at a far different
register base. Same with the PCIe RSC etc.
Konrad
^ permalink raw reply
* Re: [PATCH v6 03/10] dt-bindings: dma: nvidia,tegra186-gpc-dma: Add iommu-map property
From: Thierry Reding @ 2026-05-22 10:10 UTC (permalink / raw)
To: Akhil R
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Hunter, Laxman Dewangan, Philipp Zabel,
dmaengine, devicetree, linux-tegra, linux-kernel
In-Reply-To: <20260331102303.33181-4-akhilrajeev@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 762 bytes --]
On Tue, Mar 31, 2026 at 03:52:56PM +0530, Akhil R wrote:
> Add iommu-map property to specify separate stream IDs for each DMA
> channel. This enables each channel to be in its own IOMMU domain,
> keeping memory isolated from other devices sharing the same DMA
> controller.
>
> Define the constraints such that if the channel and stream IDs are
> contiguous, a single entry can map all the channels, but if the
> channels or stream IDs are non-contiguous support multiple entries.
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Acked-by: Rob Herring (Arm) <robh@kernel.org>
> ---
> .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
Acked-by: Thierry Reding <treding@nvidia.com>
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^ permalink raw reply
* Re: [PATCH v6 04/10] dmaengine: tegra: Make reset control optional
From: Thierry Reding @ 2026-05-22 10:11 UTC (permalink / raw)
To: Akhil R
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Hunter, Laxman Dewangan, Philipp Zabel,
dmaengine, devicetree, linux-tegra, linux-kernel, Frank Li
In-Reply-To: <20260331102303.33181-5-akhilrajeev@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1317 bytes --]
On Tue, Mar 31, 2026 at 03:52:57PM +0530, Akhil R wrote:
> On Tegra264, reset is not available for the driver to control as
> this is handled by the boot firmware. Hence make the reset control
> optional and update the error message to reflect the correct error.
>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
> drivers/dma/tegra186-gpc-dma.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
> index 5948fbf32c21..a0522a992ebc 100644
> --- a/drivers/dma/tegra186-gpc-dma.c
> +++ b/drivers/dma/tegra186-gpc-dma.c
> @@ -1381,10 +1381,10 @@ static int tegra_dma_probe(struct platform_device *pdev)
> if (IS_ERR(tdma->base_addr))
> return PTR_ERR(tdma->base_addr);
>
> - tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
> + tdma->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, "gpcdma");
> if (IS_ERR(tdma->rst)) {
> return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
> - "Missing controller reset\n");
> + "Failed to get controller reset\n");
This change is a bit pointless, but I suppose it's a little more
accurate this way, so:
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH v5 0/5] Devicetree support for Glymur GPU
From: Akhil P Oommen @ 2026-05-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen, Rajendra Nayak,
Konrad Dybcio, Dmitry Baryshkov, Manaf Meethalavalappu Pallikunhi
This series adds the necessary Device Tree bits to enable GPU support
on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
chipsets is based on the new Adreno A8x family of GPUs. It features a new
slice architecture with 4 slices, significantly higher bandwidth
throughput compared to mobile counterparts, raytracing support, and the
highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
improvements.
This series includes patches that updates DT schema, add GPU SMMU &
GPU/GMU support. Keen-eyed readers may notice that the zap shader node
is missing. This is intentional: The Glymur-based laptop platforms
generally allow booting Linux at EL2 (yay!), which means the zap firmware
is not required here.
There is an update to the gxclkctl/drm drivers to properly support the IFPC
feature across all A8x GPUs. That series [1] is necessary to properly
support Glymur GPU:
[1] https://lore.kernel.org/lkml/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com/
Just FYI, on top of the linux-next, I had to pick below series [2] to boot
the device properly. But it is unrelated to GPU or this series:
[2] https://lore.kernel.org/all/20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com/
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v5:
- Relax contraints for reg-names property (Krzysztof)
- Drop the smmu binding doc patch as it got picked up
- Link to v4: https://lore.kernel.org/r/20260513-glymur-gpu-dt-v4-0-f83832c3bc9a@oss.qualcomm.com
Changes in v4:
- Add a new patch for passive cooling support
- Link to v3: https://lore.kernel.org/r/20260512-glymur-gpu-dt-v3-0-84232dc21c03@oss.qualcomm.com
Changes in v3:
- Add a new patch to fix RSCC base vaddr in drm-msm
- Remove interconnect property from adreno smmu dt and the binding doc
- Add a contrait in GPU binding doc to limit the reg entries for Glymur
(Krzysztof)
- Link to v2: https://lore.kernel.org/r/20260501-glymur-gpu-dt-v2-0-2f128b5596bb@oss.qualcomm.com
Changes in v2:
- Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)
- Drop zap shader node from DT
- A new patch to update GPU SMMU dt schema.
- Adjust reg range in dt nodes to avoid overlap.
- Removed cx_dbgc range as it is already stable across chipsets. This
region is now part of kgsl_3d0_reg_memory range.
- Link to v1: https://lore.kernel.org/r/20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com
---
Akhil P Oommen (3):
drm/msm/a8xx: Fix RSCC offset
dt-bindings: display/msm: gpu: Document Adreno X2-185
arm64: dts: qcom: Add GPU support for Glymur
Manaf Meethalavalappu Pallikunhi (1):
arm64: dts: qcom: glymur: Add GPU cooling
Rajendra Nayak (1):
arm64: dts: qcom: glymur: Add GPU smmu node
.../devicetree/bindings/display/msm/gpu.yaml | 16 +
arch/arm64/boot/dts/qcom/glymur.dtsi | 461 ++++++++++++++++++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +-
3 files changed, 427 insertions(+), 57 deletions(-)
---
base-commit: c9bd03db3e792a99e9789fde20e91898e3a29e8a
change-id: 20260226-glymur-gpu-dt-339e5092606b
prerequisite-message-id: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com>
prerequisite-patch-id: f7ab29f2f0241b6536d3b0c0593f0baa0e435221
prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079
Best regards,
--
Akhil P Oommen <akhilpo@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v5 1/5] drm/msm/a8xx: Fix RSCC offset
From: Akhil P Oommen @ 2026-05-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen
In-Reply-To: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com>
In A8xx, the RSCC block is part of GPU's register space. Update the
virtual base address of rscc to point to the correct address.
Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 1b44b9e21ad8..cab4c46c6cf2 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
goto err_mmio;
}
} else if (adreno_is_a8xx(adreno_gpu)) {
- gmu->rscc = gmu->mmio + 0x19000;
+ /*
+ * On a8xx , RSCC lives at GPU base + 0x50000, which falls
+ * inside the GPU's kgsl_3d0_reg_memory range rather than the
+ * GMU's.
+ */
+ gmu->rscc = gpu->mmio + 0x50000;
} else {
gmu->rscc = gmu->mmio + 0x23000;
}
--
2.51.0
^ permalink raw reply related
* [PATCH v5 2/5] dt-bindings: display/msm: gpu: Document Adreno X2-185
From: Akhil P Oommen @ 2026-05-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen
In-Reply-To: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com>
Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
It features a new slice architecture with 4 slices, significantly higher
bandwidth throughput compared to mobile counterparts, raytracing support,
and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
other improvements. Update the dt bindings documentation to describe this
GPU.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 04b2328903ca..77caacd0fb3f 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -411,6 +411,21 @@ allOf:
- clocks
- clock-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,adreno-44070001
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+
- if:
properties:
compatible:
@@ -434,6 +449,7 @@ allOf:
- qcom,adreno-43050a01
- qcom,adreno-43050c01
- qcom,adreno-43051401
+ - qcom,adreno-44070001
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
--
2.51.0
^ permalink raw reply related
* [PATCH v5 3/5] arm64: dts: qcom: glymur: Add GPU smmu node
From: Akhil P Oommen @ 2026-05-22 10:11 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen, Rajendra Nayak,
Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com>
From: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Add the nodes to describe the GPU SMMU node.
Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 38 ++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index ed9aac42fcbf..5e76a0d53f01 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3729,6 +3729,44 @@ gpucc: clock-controller@3d90000 {
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x03da0000 0x0 0x40000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
+ clock-names = "hlos";
+ power-domains = <&gpucc GPU_CC_CX_GDSC>;
+ dma-coherent;
+ };
+
ipcc: mailbox@3e04000 {
compatible = "qcom,glymur-ipcc", "qcom,ipcc";
reg = <0x0 0x03e04000 0x0 0x1000>;
--
2.51.0
^ permalink raw reply related
* [PATCH v5 4/5] arm64: dts: qcom: Add GPU support for Glymur
From: Akhil P Oommen @ 2026-05-22 10:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen, Konrad Dybcio
In-Reply-To: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com>
The Adreno X2 series GPU present in Glymur SoC belongs to the A8x
family. It is a new HW IP with architectural improvements as well
as different set of hw configs like GMEM, num SPs, Caches sizes etc.
Add the GPU and GMU nodes to describe this hardware.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 183 +++++++++++++++++++++++++++++++++++
1 file changed, 183 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 5e76a0d53f01..01a2e32e503b 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3701,6 +3701,129 @@ hsc_noc: interconnect@2000000 {
#interconnect-cells = <2>;
};
+ gpu: gpu@3d00000 {
+ compatible = "qcom,adreno-44070001", "qcom,adreno";
+ reg = <0x0 0x03d00000 0x0 0x6c000>,
+ <0x0 0x03d9e000 0x0 0x2000>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 0x0>,
+ <&adreno_smmu 1 0x0>;
+
+ operating-points-v2 = <&gpu_opp_table>;
+
+ qcom,gmu = <&gmu>;
+ #cooling-cells = <2>;
+
+ interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2-adreno",
+ "operating-points-v2";
+
+ opp-310000000 {
+ opp-hz = /bits/ 64 <310000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+ opp-peak-kBps = <2136719>;
+ opp-supported-hw = <0xf>;
+ /* ACD is disabled */
+ };
+
+ opp-410000000 {
+ opp-hz = /bits/ 64 <410000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <6074219>;
+ opp-supported-hw = <0xf>;
+ /* ACD is disabled */
+ };
+
+ opp-572000000 {
+ opp-hz = /bits/ 64 <572000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <12449219>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xe02d5ffd>;
+ };
+
+ opp-760000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <12449219>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xc0285ffd>;
+ };
+
+ opp-820000000 {
+ opp-hz = /bits/ 64 <820000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0xa82e5ffd>;
+ };
+
+ opp-915000000 {
+ opp-hz = /bits/ 64 <915000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882d5ffd>;
+ };
+
+ opp-1070000000 {
+ opp-hz = /bits/ 64 <1070000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882b5ffd>;
+ };
+
+ opp-1185000000 {
+ opp-hz = /bits/ 64 <1185000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ opp-peak-kBps = <16500000>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-1350000000 {
+ opp-hz = /bits/ 64 <1350000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0xf>;
+ qcom,opp-acd-level = <0x882a5ffd>;
+ };
+
+ opp-1550000000 {
+ opp-hz = /bits/ 64 <1550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x7>;
+ qcom,opp-acd-level = <0xa8295ffd>;
+ };
+
+ opp-1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x7>;
+ qcom,opp-acd-level = <0x88295ffd>;
+ };
+
+ opp-1850000000 {
+ opp-hz = /bits/ 64 <1850000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ opp-peak-kBps = <18597657>;
+ opp-supported-hw = <0x3>;
+ qcom,opp-acd-level = <0x88285ffd>;
+ };
+ };
+ };
+
gxclkctl: clock-controller@3d64000 {
compatible = "qcom,glymur-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
@@ -3712,6 +3835,66 @@ gxclkctl: clock-controller@3d64000 {
#power-domain-cells = <1>;
};
+ gmu: gmu@3d6c000 {
+ compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
+
+ reg = <0x0 0x03d6c000 0x0 0x32000>;
+ reg-names = "gmu";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi",
+ "gmu";
+
+ clocks = <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+ <&gpucc GPU_CC_RSCC_HUB_AON_CLK>;
+ clock-names = "ahb",
+ "gmu",
+ "cxo",
+ "memnoc",
+ "hub",
+ "rscc";
+
+ power-domains = <&gpucc GPU_CC_CX_GDSC>,
+ <&gxclkctl GX_CLKCTL_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+
+ iommus = <&adreno_smmu 5 0x0>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-725000000 {
+ opp-hz = /bits/ 64 <725000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,glymur-gpucc";
reg = <0x0 0x03d90000 0x0 0x9800>;
--
2.51.0
^ permalink raw reply related
* [PATCH v5 5/5] arm64: dts: qcom: glymur: Add GPU cooling
From: Akhil P Oommen @ 2026-05-22 10:12 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Clark, Sean Paul, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Will Deacon, Robin Murphy, Joerg Roedel
Cc: linux-arm-msm, devicetree, linux-kernel, dri-devel, freedreno,
linux-arm-kernel, iommu, Akhil P Oommen,
Manaf Meethalavalappu Pallikunhi
In-Reply-To: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com>
From: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
The GPU does not throttle its speed automatically when it
reaches high temperatures. Set up GPU cooling by throttling
the GPU speed when it reaches 95°C.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 240 +++++++++++++++++++++++++++--------
1 file changed, 184 insertions(+), 56 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 01a2e32e503b..e109fb5b35a4 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -22,6 +22,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/thermal/thermal.h>
#include "glymur-ipcc.h"
@@ -7149,13 +7150,22 @@ aoss-7-critical {
};
thermal_gpu_0_0: gpu-0-0-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 1>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu00_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu00_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-0-0-critical {
@@ -7164,16 +7174,26 @@ gpu-0-0-critical {
type = "critical";
};
};
+
};
thermal_gpu_0_1: gpu-0-1-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 2>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu01_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu01_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-0-1-critical {
@@ -7185,13 +7205,22 @@ gpu-0-1-critical {
};
thermal_gpu_0_2: gpu-0-2-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 3>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu02_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu02_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-0-2-critical {
@@ -7203,13 +7232,22 @@ gpu-0-2-critical {
};
thermal_gpu_1_0: gpu-1-0-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 4>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu10_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu10_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-1-0-critical {
@@ -7221,13 +7259,22 @@ gpu-1-0-critical {
};
thermal_gpu_1_1: gpu-1-1-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 5>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu11_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu11_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-1-1-critical {
@@ -7239,13 +7286,22 @@ gpu-1-1-critical {
};
thermal_gpu_1_2: gpu-1-2-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 6>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu12_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu12_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-1-2-critical {
@@ -7257,13 +7313,22 @@ gpu-1-2-critical {
};
thermal_gpu_2_0: gpu-2-0-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 7>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu20_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu20_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-2-0-critical {
@@ -7275,13 +7340,22 @@ gpu-2-0-critical {
};
thermal_gpu_2_1: gpu-2-1-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 8>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu21_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu21_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-2-1-critical {
@@ -7293,13 +7367,22 @@ gpu-2-1-critical {
};
thermal_gpu_2_2: gpu-2-2-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 9>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu22_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu22_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-2-2-critical {
@@ -7311,13 +7394,22 @@ gpu-2-2-critical {
};
thermal_gpu_3_0: gpu-3-0-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 10>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu30_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu30_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-3-0-critical {
@@ -7329,13 +7421,22 @@ gpu-3-0-critical {
};
thermal_gpu_3_1: gpu-3-1-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 11>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu31_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu31_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-3-1-critical {
@@ -7347,13 +7448,22 @@ gpu-3-1-critical {
};
thermal_gpu_3_2: gpu-3-2-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 12>;
+ cooling-maps {
+ map0 {
+ trip = <&gpu32_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpu32_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpu-3-2-critical {
@@ -7365,13 +7475,22 @@ gpu-3-2-critical {
};
thermal_gpuss_0: gpuss-0-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 13>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpuss0_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpuss-0-critical {
@@ -7383,13 +7502,22 @@ gpuss-0-critical {
};
thermal_gpuss_1: gpuss-1-thermal {
+ polling-delay-passive = <100>;
+
thermal-sensors = <&tsens7 14>;
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+
trips {
- trip-point0 {
- temperature = <90000>;
- hysteresis = <5000>;
- type = "hot";
+ gpuss1_alert0: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "passive";
};
gpuss-1-critical {
--
2.51.0
^ permalink raw reply related
* Re: [PATCH 0/6] arm64: qcom: Enable additional hardware on Radxa Dragon Q6A
From: Graham O'Connor @ 2026-05-22 10:13 UTC (permalink / raw)
To: linux-arm-msm
Cc: andersson, konradybcio, robin.clark, lumag, abhinav.kumar, robh,
krzk+dt, conor+dt, dri-devel, devicetree, linux-kernel,
neil.armstrong
In-Reply-To: <20260522060645.4399-1-graham.oconnor@gmail.com>
Thank you to Konrad, Neil, and others for the very prompt and helpful reviews.
Based on the feedback received, I think it best to withdraw this series to
address the issues raised, most notobly:
1. The DP_TRAIN_LEVEL_MAX change (patch 3) is too broad - it affects all
devices using the Qualcomm MSM DP driver rather than being specific to
the RA620 bridge. A proper fix should be implemented at the bridge
level. This is going to take more investigation.
2. The display DT nodes (patch 5) should use the radxa,ra620 compatible
string per the existing Radxa upstream series from Xilin Wu, and the
lane ordering needs correcting.
3. The rpmh-rsc early return (patch 1) needs further review regarding
the implications of returning before full driver initialization.
4. DTS patch label dependency issue (sorry)
I'll integrate with the Radxa upstream effort, re-evaluate the other areas
and resubmit corrected patches addressing these concerns at a later date.
Thanks for the feedback.
Cheers
Graham
^ permalink raw reply
* Re: [PATCH v6 05/10] dmaengine: tegra: Use struct for register offsets
From: Thierry Reding @ 2026-05-22 10:15 UTC (permalink / raw)
To: Akhil R
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Jonathan Hunter, Laxman Dewangan, Philipp Zabel,
dmaengine, devicetree, linux-tegra, linux-kernel, Frank Li
In-Reply-To: <20260331102303.33181-6-akhilrajeev@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 525 bytes --]
On Tue, Mar 31, 2026 at 03:52:58PM +0530, Akhil R wrote:
[...]
> diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
[...]
> @@ -181,18 +149,24 @@ struct tegra_dma_chip_data {
> unsigned int nr_channels;
> unsigned int channel_reg_size;
> unsigned int max_dma_count;
> + const struct tegra_dma_channel_regs *channel_regs;
Odd. I would've thought you'd have to predeclare the structure, but if
this builds fine, I suppose it's okay this way, too:
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
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