* Re: [PATCH 1/4] ASoC: qcom: audioreach: compute active channel maps from channel_map
From: Srinivas Kandagatla @ 2026-06-16 18:52 UTC (permalink / raw)
To: Neil Armstrong, Srinivas Kandagatla, Liam Girdwood, Mark Brown,
Jaroslav Kysela, Takashi Iwai, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: kancy2333, linux-sound, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <a35d7f95-c158-46d1-b136-b901dcfbf101@linaro.org>
On 6/16/26 4:12 PM, Neil Armstrong wrote:
> On 6/16/26 16:59, Srinivas Kandagatla wrote:
>>
>>
>> On 6/15/26 2:54 PM, Neil Armstrong wrote:
>>> On 6/15/26 11:36, Srinivas Kandagatla wrote:
>>>> On 6/15/26 10:31 AM, Neil Armstrong wrote:
>>>>> On 6/15/26 10:38, Srinivas Kandagatla wrote:
>>>>>>
>>>>>>
>>>>>> On 6/10/26 8:41 AM, Neil Armstrong wrote:
>>>>>>> The Qualcom SM8650 based Ayaneo Pocket S2 gaming device has a set
>>>>>>> of 2 WSA speakers connected on the WSA2 lines.
>>>>>>>
>>>>>>> But the Audioreach DSP only handles WSA2 in pair with the WSA
>>>>>>> interface by using the upper bits of the active_channels_mask
>>>>>>> for WSA2 and the lower bits for WSA:
>>>>>>>
>>>>>>> /-------------------------------------------------\
>>>>>>> | Bits | 3 | 2 | 1 | 0 |
>>>>>>> |-------------------------------------------------|
>>>>>>> | Line | WSA2 Ch2 | WSA2 Ch1 | WSA Ch2 | WSA Ch1 |
>>>>>>> \-------------------------------------------------/
>>>>>>>
>>>>>> No, this is not totally correct, if the setup only has WSA2, then
>>>>>> channel 0 and 1 should be WSA2 channels.
>>>>>>
>>>>>> What is the backend dai id that is in DT, it should be
>>>>>>
>>>>>> sound-dai = <&q6apmbedai WSA2_CODEC_DMA_RX_0>;
>>>>>>
>
> Yeah 0xC0 for active_channels_mask and channel_mapping =
> { PCM_CHANNEL_FL, PCM_CHANNEL_FR };
>
> I tried to keep the leading 0, but since the channel_mapping table is
> allocated with
> the size of the num_channels parameter, you can ony have 2 entries.
>
>>
>> From DSP docs:
>> https://github.com/AudioReach/audioreach-engine/blob/master/fwk/api/
>> modules/media_fmt_api_basic.h#L780
>>
>> Channel[i] mapping describes channel i. Each element i of the array
>> describes channel i inside the buffer where i is less than num_channels.
>> An unused channel is set to 0.
>>
>>
>> So unused channels should be set to zero, but the patch padding the
>> channels starting form zero.
>
> My understanding in my trial and error is that the DSP will map each
> entry of the channel_mapping to the active_channels_mask bits in order
> so you can have a non linear active_channels_mask like b10101010 which
> has 4 channels active and pass a channel_mapping table with 4 entries.
>
You are correct, I was mis-interpreting some of the comments from
modules/media_fmt_api_basic.h specially the channel map comment.
Also confirmed this internally so we are good,
I tested this on T14s,
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
--srini
> The is what I implemented here, and it gives a lot of flexibility on how
> to connect speakers to the interface.
>
> Neil
^ permalink raw reply
* Re: [PATCH 2/4] ASoC: qcom: sc8280xp: add Ayaneo Pocket S2 card with special WSA channel mapping
From: Srinivas Kandagatla @ 2026-06-16 18:54 UTC (permalink / raw)
To: Neil Armstrong, Srinivas Kandagatla, Liam Girdwood, Mark Brown,
Jaroslav Kysela, Takashi Iwai, Bjorn Andersson, Konrad Dybcio,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: kancy2333, linux-sound, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20260610-topic-sm8650-ayaneo-pocket-s2-wsa2-fix-v1-2-18bb19c5ca22@linaro.org>
On 6/10/26 8:41 AM, Neil Armstrong wrote:
> The WSA Speakers are connected on the WSA2 interface, but the
> WSA and WSA2 links are handled as a single dai and DSP interface, so
> we need to specify the channel mapping of the Ayaneo Pocket S2 for the
> WSA dai in order to have functional playback and avoid DSP errors.
>
> Let's add a special entry for the Ayaneo Pocket S2 adding a prepare
> callback in order to set the proper channel mapping.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
lgtm,
Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
--srini
> sound/soc/qcom/sc8280xp.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c
> index 1f3afc6d015c..2f1688c9f317 100644
> --- a/sound/soc/qcom/sc8280xp.c
> +++ b/sound/soc/qcom/sc8280xp.c
> @@ -14,6 +14,7 @@
> #include "qdsp6/q6afe.h"
> #include "qdsp6/q6apm.h"
> #include "qdsp6/q6prm.h"
> +#include "qdsp6/q6dsp-common.h"
> #include "common.h"
> #include "sdw.h"
>
> @@ -49,6 +50,7 @@ struct snd_soc_common {
> bool codec_sysclk_set;
> bool mi2s_mclk_enable;
> bool mi2s_bclk_enable;
> + int (*snd_prepare)(struct snd_pcm_substream *substream);
> };
>
> struct sc8280xp_snd_data {
> @@ -193,12 +195,58 @@ static int sc8280xp_snd_hw_params(struct snd_pcm_substream *substream,
> return 0;
> }
>
> +/*
> + * WSA and WSA2 are handled as a single interface with the
> + * following channels mask:
> + * __________________________________________________
> + * | Bits | 3 | 2 | 1 | 0 |
> + * ---------------------------------------------------
> + * | Line | WSA2 Ch2 | WSA2 Ch1 | WSA Ch2 | WSA Ch1 |
> + * ---------------------------------------------------
> + *
> + * The Ayaneo Pocket S2 speakers are connected only to
> + * the WSA2 interface and the WSA interface is not enabled.
> + *
> + * Set the channel mapping on the WSA2 channels only.
> + */
> +static const unsigned int ayaneo_ps2_channels_mapping[] = {
> + 0, /* WSA Ch1 */
> + 0, /* WSA Ch2 */
> + PCM_CHANNEL_FL, /* WSA2 Ch1 */
> + PCM_CHANNEL_FR /* WSA2 Ch2 */
> +};
> +
> +static int ayaneo_ps2_snd_prepare(struct snd_pcm_substream *substream)
> +{
> + struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
> + struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
> + unsigned int channels = substream->runtime->channels;
> +
> + if (cpu_dai->id != WSA_CODEC_DMA_RX_0)
> + return 0;
> +
> + if (channels != 2)
> + return -EINVAL;
> +
> + return snd_soc_dai_set_channel_map(cpu_dai, 0, NULL,
> + ARRAY_SIZE(ayaneo_ps2_channels_mapping),
> + ayaneo_ps2_channels_mapping);
> +}
> +
> static int sc8280xp_snd_prepare(struct snd_pcm_substream *substream)
> {
> struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
> struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
> struct sc8280xp_snd_data *data = snd_soc_card_get_drvdata(rtd->card);
>
> + if (data->snd_soc_common_priv->snd_prepare) {
> + int ret;
> +
> + ret = data->snd_soc_common_priv->snd_prepare(substream);
> + if (ret)
> + return ret;
> + }
> +
> return qcom_snd_sdw_prepare(substream, &data->stream_prepared[cpu_dai->id]);
> }
>
> @@ -273,6 +321,13 @@ static int sc8280xp_platform_probe(struct platform_device *pdev)
> return devm_snd_soc_register_card(dev, card);
> }
>
> +static struct snd_soc_common ayaneo_ps2_priv_data = {
> + .driver_name = "ayaneo-ps2",
> + .dapm_widgets = sc8280xp_dapm_widgets,
> + .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets),
> + .snd_prepare = ayaneo_ps2_snd_prepare,
> +};
> +
> static struct snd_soc_common kaanapali_priv_data = {
> .driver_name = "kaanapali",
> .dapm_widgets = sc8280xp_dapm_widgets,
> @@ -341,6 +396,7 @@ static struct snd_soc_common sm8750_priv_data = {
> };
>
> static const struct of_device_id snd_sc8280xp_dt_match[] = {
> + {.compatible = "ayaneo,pocket-s2-sndcard", .data = &ayaneo_ps2_priv_data},
> {.compatible = "qcom,kaanapali-sndcard", .data = &kaanapali_priv_data},
> {.compatible = "qcom,qcm6490-idp-sndcard", .data = &qcm6490_priv_data},
> {.compatible = "qcom,qcs615-sndcard", .data = &qcs615_priv_data},
>
^ permalink raw reply
* [PATCH] dt-bindings: sound: add toshiba,apb-dummy-codec binding
From: Pablo D. Bergamasco @ 2026-06-16 18:56 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Vaibhav Agarwal, Mark Greer, Liam Girdwood, Mark Brown,
linux-sound, devicetree, linux-kernel, Pablo D. Bergamasco
Add device tree binding documentation for the Toshiba APBridge
dummy ALSA SoC codec used in the Greybus audio framework.
Fixes the following checkpatch warning:
WARNING: DT compatible string appears un-documented
Signed-off-by: Pablo D. Bergamasco <danpablo@gmail.com>
---
.../sound/toshiba,apb-dummy-codec.yaml | 33 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/toshiba,apb-dummy-codec.yaml
diff --git a/Documentation/devicetree/bindings/sound/toshiba,apb-dummy-codec.yaml b/Documentation/devicetree/bindings/sound/toshiba,apb-dummy-codec.yaml
new file mode 100644
index 000000000000..e0542feeb980
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/toshiba,apb-dummy-codec.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/toshiba,apb-dummy-codec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba APBridge Dummy ALSA SoC Codec
+
+maintainers:
+ - Vaibhav Agarwal <vaibhav.agarwal@linaro.org>
+
+description:
+ The APBridge dummy codec is part of the Greybus audio framework,
+ used in Project Ara modular phone hardware. It provides a dummy
+ ALSA SoC codec driver for the APBridge audio interface, enabling
+ audio streaming between Greybus modules and the host processor
+ via the APBridge protocol.
+
+properties:
+ compatible:
+ const: toshiba,apb-dummy-codec
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ codec {
+ compatible = "toshiba,apb-dummy-codec";
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index b2040011a386..b6b4b488c0f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11077,6 +11077,7 @@ GREYBUS AUDIO PROTOCOLS DRIVERS
M: Vaibhav Agarwal <vaibhav.sr@gmail.com>
M: Mark Greer <mgreer@animalcreek.com>
S: Maintained
+F: Documentation/devicetree/bindings/sound/toshiba,apb-dummy-codec.yaml
F: drivers/staging/greybus/audio_apbridgea.c
F: drivers/staging/greybus/audio_apbridgea.h
F: drivers/staging/greybus/audio_codec.c
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v7 9/9] arm64: dts: mediatek: Add MediaTek MT6392 PMIC dtsi
From: Rob Herring @ 2026-06-16 18:57 UTC (permalink / raw)
To: Luca Leonardo Scorcia
Cc: linux-mediatek, Val Packett, Dmitry Torokhov, Krzysztof Kozlowski,
Conor Dooley, Sen Chu, Sean Wang, Macpaul Lin, Lee Jones,
Matthias Brugger, AngeloGioacchino Del Regno, Liam Girdwood,
Mark Brown, Linus Walleij, Louis-Alexis Eyraud, Julien Massot,
Fabien Parent, Akari Tsuyukusa, Chen Zhong, linux-input,
devicetree, linux-kernel, linux-pm, linux-arm-kernel, linux-gpio
In-Reply-To: <CAORyz2LiMHnaTK6QnsLxJDtw0fZ_N9LELw0iCorOZwHuWXus0g@mail.gmail.com>
On Tue, Jun 16, 2026 at 10:32 AM Luca Leonardo Scorcia
<l.scorcia@gmail.com> wrote:
>
> > > arch/arm64/boot/dts/mediatek/mt6392.dtsi | 75 ++++++++++++++++++++++++
> >
> > Nothing is using this so it is a dead file that doesn't get tested.
>
> Hi, it's not referenced as the dtsi inclusion was removed in the
> original patch from 2019 for an easier merging of support for mt8516
> pumpkin boards [1][2].
> If you prefer in the next revision I can add another patch to readd it
> to the existing pumpkin board.
That or move this patch to the series for the board(s). If the board
is already upstream, then add the include in *this* patch.
Rob
^ permalink raw reply
* Re: [PATCH 3/4] input: misc: Add Qualcomm SPMI PMIC haptics driver
From: Dmitry Torokhov @ 2026-06-16 19:22 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Fenglin Wu, linux-arm-msm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Lee Jones, Stephen Boyd, Bjorn Andersson,
Konrad Dybcio, David Collins, Subbaraman Narayanamurthy,
Kamal Wadhwa, kernel, linux-input, devicetree, linux-kernel
In-Reply-To: <eb693705-c0c3-427b-a924-5aa907fd65bb@oss.qualcomm.com>
On Tue, Jun 16, 2026 at 12:25:55PM +0200, Konrad Dybcio wrote:
> On 6/16/26 12:08 PM, Fenglin Wu wrote:
> > Add an initial driver for the Qualcomm PMIH010x PMIC haptics module,
> > named as HAP530_HV. This module supports several play modes, including
> > DIRECT_PLAY, FIFO, PAT_MEM, and SWR, each with distinct data sourcing
> > and hardware data handling logic. Currently, the driver provides support
> > for two play modes using the input force-feedback framework: FF_CONSTANT
> > effect for DIRECT_PLAY mode and FF_PERIODIC effect with FF_CUSTOM
> > waveform for FIFO mode.
> >
> > Assisted-by: Claude:claude-4-6-sonnet
> > Signed-off-by: Fenglin Wu <fenglin.wu@oss.qualcomm.com>
> > ---
>
> [...]
>
> > +static int cfg_write(struct qcom_haptics *h, u32 off, u32 val)
>
> static inline
No, let compiler do its job and decide whether it should be inlined or
not.
Thanks.
--
Dmitry
^ permalink raw reply
* Re: [PATCH 3/5] ASoC: qcom: qdsp6: q6prm: add the missing MCLK clock IDs
From: Srinivas Kandagatla @ 2026-06-16 19:41 UTC (permalink / raw)
To: Hongyang Zhao, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Daniel Drake, Katsuhiro Suzuki,
Matteo Martelli, Binbin Zhou, Srinivas Kandagatla,
Jaroslav Kysela, Takashi Iwai, Bjorn Andersson, Konrad Dybcio
Cc: linux-sound, devicetree, linux-kernel, linux-arm-msm,
mohammad.rafi.shaik, rosh, Neil Armstrong, Srinivas Kandagatla
In-Reply-To: <20260607-rubikpi-next-20260605-v1-3-7f334e16fea6@thundersoft.com>
On 6/6/26 7:58 PM, Hongyang Zhao wrote:
> From: Neil Armstrong <neil.armstrong@linaro.org>
>
> Add the missing MCLK ids for the q6prm DSP interface.
>
> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
please add your signed-off here
for more info take a look at
Documentation/process/submitting-patches.rst
> ---
> sound/soc/qcom/qdsp6/q6prm-clocks.c | 5 +++++
> sound/soc/qcom/qdsp6/q6prm.h | 11 +++++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c
> index 4c574b48ab00..51b131fa9531 100644
> --- a/sound/soc/qcom/qdsp6/q6prm-clocks.c
> +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c
> @@ -42,6 +42,11 @@ static const struct q6dsp_clk_init q6prm_clks[] = {
> Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
> Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
> Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_1),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_2),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_3),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_4),
> + Q6PRM_CLK(LPASS_CLK_ID_MCLK_5),
> Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
> Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
> Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
> diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h
> index a988a32086fe..6917e70bcb8a 100644
> --- a/sound/soc/qcom/qdsp6/q6prm.h
> +++ b/sound/soc/qcom/qdsp6/q6prm.h
> @@ -52,6 +52,17 @@
> /* Clock ID for QUINARY MI2S OSR CLK */
> #define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116
>
> +/* Clock ID for MCLK1 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_1 0x300
> +/* Clock ID for MCLK2 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_2 0x301
> +/* Clock ID for MCLK3 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_3 0x302
> +/* Clock ID for MCLK4 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_4 0x303
> +/* Clock ID for MCLK5 */
> +#define Q6PRM_LPASS_CLK_ID_MCLK_5 0x304
> +
> #define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305
> #define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306
>
>
^ permalink raw reply
* Re: [PATCH 1/4] dt-bindings: iio: adc: add ti,ads122c14
From: David Lechner @ 2026-06-16 19:54 UTC (permalink / raw)
To: Conor Dooley
Cc: Jonathan Cameron, Nuno Sá, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kurt Borja, Nguyen Minh Tien,
linux-iio, devicetree, linux-kernel
In-Reply-To: <20260616-spoon-ducky-b05e9bf7e999@spud>
On 6/16/26 11:07 AM, Conor Dooley wrote:
> On Mon, Jun 15, 2026 at 04:59:59PM -0500, David Lechner (TI) wrote:
>> Add new bindings for ti,ads122c14 and similar devices.
>>
>> This is an ADC that is primarily intended for use with temperature
>> sensors. There are a few unusual properties because of this. In
>> particular, the reference voltage source and current output requirements
>> can be different for each measurement, so these are included in the
>> channel bindings.
>>
>> The REFP/REFN reference voltage is usually just connected to a resistor
>> that is being driven by the ADC's current outputs, so there is special
>> property for this case rather than requiring a regulator to be defined
>> to represent that.
>>
>> ti,vref-source is reused from ti,tlv320adcx140.yaml (otherwise might
>> have preferred an enum of strings).
>>
>> Signed-off-by: David Lechner (TI) <dlechner@baylibre.com>
>> ---
>> .../devicetree/bindings/iio/adc/ti,ads112c14.yaml | 224 +++++++++++++++++++++
>> MAINTAINERS | 7 +
>> include/dt-bindings/iio/adc/ti,ads112c14.h | 11 +
>> 3 files changed, 242 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml b/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml
>> new file mode 100644
>> index 000000000000..dc7f37cad772
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/ti,ads112c14.yaml
>> @@ -0,0 +1,224 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/iio/adc/ti,ads112c14.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Texas Instruments' ADS112C14 and similar ADC chips
>> +
>> +description: |
>> + Supports the following Texas Instruments' ADC chips:
>> + - ADS112C14 (16-bit)
>> + - ADS122C14 (24-bit)
>> +
>> + https://www.ti.com/lit/ds/symlink/ads122c14.pdf
>> +
>> + These chips are primarily designed for use with temperature sensors such as
>> + RTDs and thermocouples. The channel bindings reflect this in that each channel
>> + represents the conditions required to make a measurement rather than strictly
>> + just the physical input channels.
>> +
>> +maintainers:
>> + - David Lechner <dlechner@baylibre.com>
>> +
>> +unevaluatedProperties: false
>
> Weird positioning of this.
IIRC, Rob asked that I do it in this order on another binding a while
ago (the reasoning being that it was too far away from properties:
otherwise), so I've done it like this on a few bindings now. It doesn't
make much difference to me though.
>
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - ti,ads112c14
>> + - ti,ads122c14
>> +
>> + reg:
>> + items:
>> + - minimum: 0x40
>> + maximum: 0x47
>> +
>> + clocks:
>> + maxItems: 1
>> + description: Optional external clock connected to GPIO3 pin.
>> +
>> + avdd-supply: true
>> + dvdd-supply: true
>> +
>> + refp-supply: true
>> + refn-supply: true
>> +
>> + refp-refn-resistor-ohms:
>
> Missing prefix here and elsewhere.
I thought we didn't need a prefix when using standard units.
>> + ti,vref-source:
>> + description: |
>> + Indicates the source for the reference voltage for this channel.
>> + 0 - Internal 2.5V reference
>> + 1 - Internal 1.25V reference
>> + 2 - External reference (REFP-REFN)
>> + 3 - AVDD as reference
>
> My usual complaint here about things you have to make macros for, could
> these just be strings from the get-go?
As in the commit message, this is an existing property name, so I didn't want
to change the type. But I agree that strings are better for this kind of thing
so perhaps I should just use a different property name instead so we can do
it better.
^ permalink raw reply
* Re: [PATCH 2/13] dt-bindings: sound: Add Qualcomm QAIF binding
From: Srinivas Kandagatla @ 2026-06-16 19:59 UTC (permalink / raw)
To: Harendra Gautam, Srinivas Kandagatla
Cc: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-sound, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20260605103739.3557573-3-harendra.gautam@oss.qualcomm.com>
On 6/5/26 11:37 AM, Harendra Gautam wrote:
> Add a Devicetree binding for the Qualcomm Audio Interface (QAIF) CPU DAI
> controller used on the Shikra audio platform.
>
> QAIF moves PCM data between system memory and external serial audio
> interfaces through the AIF path, and between memory and the internal Bolero
> digital codec through the CIF path. The controller needs a binding so
> platform Devicetree files can describe its MMIO region, DMA IOMMU stream,
> clocks, interrupt, DAI cells and per-interface AIF configuration.
>
> Describe the single register region, one EE interrupt, the required GCC
> LPASS and audio core clocks, the DMA IOMMU mapping, and 'aif-interface@N'
> child nodes used for static PCM, TDM or MI2S configuration.
>
> Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
> ---
> .../devicetree/bindings/sound/qcom,qaif.yaml | 353 ++++++++++++++++++
> 1 file changed, 353 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/qcom,qaif.yaml
>
> diff --git a/Documentation/devicetree/bindings/sound/qcom,qaif.yaml b/Documentation/devicetree/bindings/sound/qcom,qaif.yaml
Pl run dt-bindings checks before posting.
> new file mode 100644
> index 000000000000..5b385e05a650
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/qcom,qaif.yaml
> @@ -0,0 +1,361 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/qcom,qaif.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Audio Interface (QAIF) CPU DAI Controller
> +
> +maintainers:
> + - Harendra Gautam <harendra.gautam@oss.qualcomm.com>
> +
> +description:
> + |
> + The Qualcomm Audio Interface (QAIF) is a fully configurable DMA-based
> + audio subsystem controller. It serialises and deserialises PCM audio
> + between system memory and external serial audio peripherals (PCM, TDM,
> + I2S, MI2S) through the AIF path, and transfers parallel audio between
> + memory and an internal WCD codec through the CIF path.
> +
> + AIF (Audio Interface): up to 13 multi-lane Unified Audio Interfaces,
> + each supporting up to 8 independent data lanes. Each lane is individually
> + configurable as TX (output/speaker) or RX (input/mic). All lanes of an
> + interface share a single bit clock and frame sync. Supported modes are
> + PCM (short/long sync), TDM, and MI2S (stereo/mono). Per-interface
> + configuration includes sync source (master/slave), sync mode, sync delay,
> + sync inversion, slot width (8/16/24/32-bit), sample width, active slot
> + masks (up to 32 slots), bits-per-lane frame size, lane enable/direction
> + masks, loopback, output-enable control, and full-cycle path support for
> + long chip-to-chip connections.
> +
> + CIF (Codec Interface): up to 32 RDDMA (playback) and 32 WRDMA (capture)
> + channels connecting to an internal codec over a parallel bus. Each channel
> + supports active-channel enable mask (up to 16 channels), frame-sync
> + selection, frame-sync delay, frame-sync output gating, dynamic clock
> + gating, and 16-bit packing/unpacking.
> +
> + Note on RX/TX naming convention: in QAIF, RX refers to the capture path
> + (audio received from the interface into memory) and TX refers to the
> + playback path (audio transmitted from memory to the interface). This
> + applies to both AIF lane directions and CIF slot/mask properties.
> +
> + DMA engine: RDDMA fetches audio from DDR/TCM/LPM into a shared SRAM
> + latency buffer (SHRAM) and drains it to the interface. WRDMA collects
> + data from the interface into SHRAM and writes it to memory. Each DMA
> + owns a private SHRAM region defined by start address and length registers.
> + Burst sizes of 1/2/4/8/16 beats (64-bit) are supported with up to 4
> + outstanding transactions per DMA. Two QSB master ports (QXM0 for TCM,
> + QXM1 for DDR/LPM) provide the memory interface.
> +
> + Resources are partitioned among up to 5 Execution Engines (EEs) via
> + EE map registers. Each EE owns a set of DMAs, audio interfaces, and
> + interface groups, and receives its own independent interrupt output.
> + The interrupt hierarchy has a two-level structure: a summary register
> + identifies the event class (DMA period, underflow/overflow, error
> + response, audio interface underflow/overflow, group done, rate detector,
> + VFR), and per-resource status registers identify the specific channel.
> +
> + Interface grouping (bonding) allows up to 6 groups of audio and codec
> + interfaces to start synchronously and align their DMA period interrupts
> + within half a frame duration using the RDDMA padding feature.
> +
> + Two rate detector blocks measure the frequency of incoming frame sync or
> + word select signals and generate interrupts on rate change, undetected
> + rate, or sync timeout.
> +
> + Block diagram::
> +
> + System Memory (DDR / LPM / TCM)
> + +---------------------------------+
> + | Circular Buffers (ping-pong) |
> + +----------+----------+-----------+
> + | ^
> + 64-bit AXI 64-bit AXI
> + | |
> + +----------v----------+-----------+
> + | QSB Master Ports |
> + | +----------+ +----------+ |
> + | | QXM0 | | QXM1 | |
> + | +----+-----+ +-----+----+ |
> + +-------|--------------|----------+
> + | |
> + +-------v--------------v----------+
> + | Shared RAM (SHRAM) |
> + | +------------+ +------------+ |
> + | | QXM0 Read | | QXM0 Write | |
> + | | SHRAM | | SHRAM | |
> + | +------------+ +------------+ |
> + | +------------+ +------------+ |
> + | | QXM1 Read | | QXM1 Write | |
> + | | SHRAM | | SHRAM | |
> + | +------------+ +------------+ |
> + +---+--------+--------+-------+---+
> + | | | |
> + +---v--+ +--v---+ +--v---+ +-v----+
> + |RDDMA | |RDDMA | |WRDMA | |WRDMA |
> + | AIF | | CIF | | AIF | | CIF |
> + |[0..n]| |[0..n]| |[0..n]| |[0..n]|
> + +--+---+ +--+---+ +--+---+ +-+----+
> + | | ^ ^
> + | TX | TX | RX | RX
> + v v | |
> + +--+--------------------+ +----+----------+
> + | Unified Audio Intf | | Codec DMA |
> + | (AIF 0..12) | | Interface |
> + | | | (CIF) |
> + | AUD_INTFa block: | | |
> + | - Serializer (TX) | | RDDMA: DDR -> |
> + | - De-serializer (RX) | | internal |
> + | - Sync gen/detect | | codec |
> + | - Up to 8 data lanes | | WRDMA: codec |
> + | - PCM / TDM / MI2S | | -> DDR |
> + | - Near Pad Logic | | Up to 16 ch |
> + +--+--------------------+ +----+----------+
> + | Lane 0..7 (TX/RX) | Parallel bus
> + | Bit clk + Frame sync | + Frame sync
> + v v
> + +--+--------+ +------+------+
> + | External | | Internal |
> + | Serial | | Digital |
> + | Peripherals| | Codec |
> + | (PCM/TDM/ | | (Bolero/ |
> + | MI2S) | | WCD) |
> + +-----------+ +-------------+
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,shikra-qaif-cpu
> +
> + reg:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + clocks:
> + minItems: 15
> + maxItems: 15
> +
> + clock-names:
> + items:
> + - const: lpass_config_clk
> + - const: lpass_core_axim_clk
> + - const: aud_dma_clk
> + - const: aud_dma_mem_clk
> + - const: bus_clk
> + - const: aif_if0_ebit_clk
> + - const: aif_if0_ibit_clk
> + - const: aif_if1_ebit_clk
> + - const: aif_if1_ibit_clk
> + - const: aif_if2_ebit_clk
> + - const: aif_if2_ibit_clk
> + - const: aif_if3_ebit_clk
> + - const: aif_if3_ibit_clk
> + - const: ext_mclka_clk
> + - const: ext_mclkb_clk
Also do we really need to specify these 15 clocks even though I use only
one aif interface on my board.
should some of these clocks belong to each aif child node instead of
global qaif-cpu?
> +
> + interrupts:
> + maxItems: 1
> +
> + '#sound-dai-cells':
> + const: 1
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + status: true
> +
> +patternProperties:
> + "^aif-interface@[0-9a-f]+$":
> + type: object
> + description:
> + AIF interface configuration child node. The compatible string
> + identifies the serial protocol the interface is wired for on the
> + board. The unit address matches the hardware AIF interface index.
> + properties:
> + compatible:
> + enum:
> + - qcom,qaif-pcm-dai
> + - qcom,qaif-tdm-dai
> + - qcom,qaif-mi2s-dai
> + reg:
> + maxItems: 1
> + description: |
> + Hardware AIF interface index (AUD_INTFa block index). This value
> + also serves as the ALSA DAI ID; it corresponds directly to the
> + QAIF_MI2S_TDM_AIFn constants in <dt-bindings/sound/qcom,qaif.h>
> + (e.g. reg = <2> selects QAIF_MI2S_TDM_AIF2).
> + qcom,qaif-aif-sync-mode:
> + $ref: /schemas/types.yaml#/definitions/uint32
These should be enum instead of uint32, simillar comments apply to some
of the properties that have only few supported values.
> + description:
> + Sync mode. Use QAIF_AIF_SYNC_MODE_SHORT (0) for short (pulse)
> + sync or QAIF_AIF_SYNC_MODE_LONG (1) for long (level) sync.
> + qcom,qaif-aif-sync-src:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Sync source. Use QAIF_AIF_SYNC_SRC_SLAVE (0) for slave mode
> + or QAIF_AIF_SYNC_SRC_MASTER (1) for master mode.
> + qcom,qaif-aif-invert-sync:
> + type: boolean
> + description: Invert the frame sync polarity.
> + qcom,qaif-aif-sync-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: Number of bit-clock cycles to delay the data relative to sync.
This looks redundant to qcom,qaif-aif-sync-mode, which already indicates
the delay information?
> + qcom,qaif-aif-slot-width-rx:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + RX slot width in bits. This is a board-specific hardware constraint
> + determined by the wiring of the serial audio interface.
> + qcom,qaif-aif-slot-width-tx:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + TX slot width in bits. This is a board-specific hardware constraint
> + determined by the wiring of the serial audio interface.
> + qcom,qaif-aif-slot-en-rx-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Bitmask of active RX slots. Board-specific — determined by which
> + TDM slots the codec is wired to on this board.
> + qcom,qaif-aif-slot-en-tx-mask:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Bitmask of active TX slots. Board-specific — determined by which
> + TDM slots the codec is wired to on this board.
> + qcom,qaif-aif-loopback:
> + type: boolean
> + description: Enable loopback mode (presence enables loopback).
What is this mode used for, testing ?
> + qcom,qaif-aif-ctrl-data-oe:
> + type: boolean
> + description: Enable output drive on the control/data line.
will this be ever false?
> + qcom,qaif-aif-lane-config:
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + description:
> + Lane configuration matrix. Each row is a pair <enable direction>
> + for one lane starting from lane 0, up to 8 lanes. Use
> + QAIF_AIF_LANE_ENABLE (1) or QAIF_AIF_LANE_DISABLE (0) for enable.
> + Use QAIF_AIF_LANE_DIR_TX (0) for TX (speaker) or QAIF_AIF_LANE_DIR_RX
> + (1) for RX (mic). TX and RX lanes should each be grouped contiguously.
what do you mean ? can you elobrate how can you enforce this?
> + maxItems: 8
> + items:
> + items:
> + - description: Lane enable (0 = disabled, 1 = enabled)
> + enum: [0, 1]
> + - description: Lane direction (0 = TX/speaker, 1 = RX/mic)
> + enum: [0, 1]
> + qcom,qaif-aif-full-cycle-en:
> + type: boolean
> + description: Enable full-cycle sync (effective in sync master mode).
> + qcom,qaif-aif-bits-per-lane:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Number of slots per lane. The frame length is computed as
bits per lane?
> + slot-width multiplied by bits-per-lane.
> + if:
> + properties:
> + compatible:
> + const: qcom,qaif-mi2s-dai
> + then:
> + description:
> + MI2S interface. Sync mode and slot-enable masks are fixed by the
> + MI2S protocol and must not be set in DT. Mono/stereo mode is
> + determined at runtime from the stream channel count.
> + properties:
> + qcom,qaif-aif-sync-mode: false
> + qcom,qaif-aif-slot-en-rx-mask: false
> + qcom,qaif-aif-slot-en-tx-mask: false
> + else:
> + description:
> + PCM or TDM interface. Sync mode and slot-enable masks are
> + board-specific and must be provided. Mono mode does not apply.
> + required:
> + - qcom,qaif-aif-sync-mode
> + - qcom,qaif-aif-slot-en-rx-mask
> + - qcom,qaif-aif-slot-en-tx-mask
> +
> + required:
> + - compatible
> + - reg
> + additionalProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - iommus
do we
> + - clocks
> + - clock-names
> + - interrupts
> + - '#sound-dai-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + /* Shikra platform example */
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/sound/qcom,qaif.h>
> + #include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
> + #include <dt-bindings/clock/qcom,gcc-shikra.h>
> +
> + qaif_cpu: audio@a000000 {
> + compatible = "qcom,shikra-qaif-cpu";
> + reg = <0x0 0x0a000000 0x0 0x20000>;
> + iommus = <&apps_smmu 0x1c0 0x0>;
> + clocks = <&gcc GCC_LPASS_CONFIG_CLK>,
> + <&gcc GCC_LPASS_CORE_AXIM_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_BUS_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>,
> + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>;
> + clock-names = "lpass_config_clk",
> + "lpass_core_axim_clk",
> + "aud_dma_clk",
> + "aud_dma_mem_clk",
> + "bus_clk",
> + "aif_if0_ebit_clk",
> + "aif_if0_ibit_clk",
> + "aif_if1_ebit_clk",
> + "aif_if1_ibit_clk",
> + "aif_if2_ebit_clk",
> + "aif_if2_ibit_clk",
> + "aif_if3_ebit_clk",
> + "aif_if3_ibit_clk",
> + "ext_mclka_clk",
> + "ext_mclkb_clk";
> + #sound-dai-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> + status = "okay";
> +
> + qaif_aif_if2: aif-interface@2 {
> + compatible = "qcom,qaif-tdm-dai";
> + reg = <QAIF_MI2S_TDM_AIF2>;
> + qcom,qaif-aif-sync-mode = <QAIF_AIF_SYNC_MODE_LONG>;
> + qcom,qaif-aif-sync-src = <QAIF_AIF_SYNC_SRC_MASTER>;
> + qcom,qaif-aif-sync-delay = <1>;
> + qcom,qaif-aif-slot-width-rx = <32>;
> + qcom,qaif-aif-slot-width-tx = <32>;
> + qcom,qaif-aif-slot-en-rx-mask = <0x3>;
> + qcom,qaif-aif-slot-en-tx-mask = <0x3>;
> + qcom,qaif-aif-ctrl-data-oe;
> + /* Lane 0: RX (mic); Lane 1: TX (speaker) */
> + qcom,qaif-aif-lane-config = <QAIF_AIF_LANE_ENABLE QAIF_AIF_LANE_DIR_RX>,
> + <QAIF_AIF_LANE_ENABLE QAIF_AIF_LANE_DIR_TX>;
> + /* frame length = slot-width (32) * bits-per-lane (2) = 64 bits */
> + qcom,qaif-aif-bits-per-lane = <2>;
> + };
> + };
^ permalink raw reply
* Re: [PATCH 3/9] firmware: imx: ele: Add API functions for OCOTP fuse access
From: Frank Li @ 2026-06-16 20:05 UTC (permalink / raw)
To: Frieder Schrempf
Cc: Frieder Schrempf, Pankaj Gupta, Srinivas Kandagatla, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, devicetree,
imx, linux-arm-kernel, linux-kernel
In-Reply-To: <cea74ed4-1003-419e-8da3-1c62b1ace726@kontron.de>
On Tue, Jun 16, 2026 at 07:59:54PM +0200, Frieder Schrempf wrote:
> On 16.06.26 17:36, Frank Li wrote:
> > On Tue, Jun 16, 2026 at 01:52:18PM +0200, Frieder Schrempf wrote:
> >> From: Frieder Schrempf <frieder.schrempf@kontron.de>
> >>
> >> The ELE S400 API provides read and write access to the OCOTP fuse
> >> registers. This adds the necessary API functions imx_se_read_fuse()
> >> and imx_se_write_fuse() to be used by other drivers such as the
> >> OCOTP S400 NVMEM driver.
> >>
> >> This is ported from the downstream vendor kernel.
> >>
> >> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> >> ---
> >> drivers/firmware/imx/ele_base_msg.c | 122 ++++++++++++++++++++++++++++++++++++
> >> drivers/firmware/imx/ele_base_msg.h | 6 ++
> >> include/linux/firmware/imx/se_api.h | 3 +
> >> 3 files changed, 131 insertions(+)
> >>
> > ...
> >> +++ b/include/linux/firmware/imx/se_api.h
> >> @@ -11,4 +11,7 @@
> >> #define SOC_ID_OF_IMX8ULP 0x084d
> >> #define SOC_ID_OF_IMX93 0x9300
> >>
> >> +int imx_se_read_fuse(void *se_if_data, uint16_t fuse_id, u32 *value);
> >> +int imx_se_write_fuse(void *se_if_data, uint16_t fuse_id, u32 value);
> >> +
> >
> > This API should implement in fuse drivers. Other consume should use standard
> > fuse API to get value. If put here, it may bypass fuse driver.
>
> The reason this is here, is the downstream implementation in linux-imx
> and the current code organization.
Downstream may not good enough, sometime, it is quick solution.
> I thought there is some good reason
> to have shared functions and it looks like Pankaj structured it like
> this so all API functions live in ele_base_msg.c and the internal
> structs and defines in ele_base_msg.h and se_ctrl.h are not exposed to
> other drivers.
>
> If I would move this into imx-ocotp-ele.c, then I would also need to
> change how the code is organized and make the internal se_api functions
> exposed to other drivers. I don't know if that is really a good idea.
>
> I get your point but it looks like this contradicts the intention of
> having a clean API in the firmware driver.
You can refer imx-ocotp-scu.c, structure should be similar, only difference
is that lower transfer APIs.
Frank
^ permalink raw reply
* [PATCH v1 0/8] arm64: dts: qcom: shikra: Enable audio on EVK boards
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel
This series enables the Shikra audio path on EVK targets by adding the QAIF
CPU endpoint, GPR/APM/PRM services, SoundWire and LPASS macro nodes, and
board-level sound card wiring for CQM, CQS and IQS variants.
The series is based on linux-next plus the posted Shikra dependency stack
(clock/controller, bindings and ASoC dependencies listed in prerequisite
patches below).
Patch split:
- 1-4: SoC-level audio nodes in shikra.dtsi (kept disabled)
- 5-7: board-level enablement for CQM/CQS/IQS EVKs
- 8: arm64 defconfig updates for QAIF and WSA885X-I2C
Mohammad Rafi Shaik (8):
ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
arm64: dts: qcom: shikra: Add QAIF CPU node for audio
arm64: dts: qcom: shikra: Add gpr node
arm64: dts: qcom: shikra: Add soundwire and macro nodes
arm64: dts: qcom: shikra-cqm-evk: Enable sound card support
arm64: dts: qcom: shikra-cqs-evk: Enable sound card support
arm64: dts: qcom: shikra-iqs-evk: Enable sound card support
arm64: defconfig: Enable Qualcomm QAIF and WSA885X-I2C drivers
.../bindings/soc/qcom/qcom,apr.yaml | 4 +-
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 222 +++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 5 +
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 149 ++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 143 ++++++++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 256 ++++++++++++++++++
arch/arm64/configs/defconfig | 2 +
7 files changed, 780 insertions(+), 1 deletion(-)
base-commit: abe651837cb394f76d738a7a747322fca3bf17ba
prerequisite-patch-id: 59bb0a7828e41f546f734f127d81da83c0adcda9
prerequisite-patch-id: 197da6bcb15cadc47869dba88c8020987b25c335
prerequisite-patch-id: 8ec9c1eb03f052ae232ed54117abed38672c23f6
prerequisite-patch-id: 350db4f4bcdfc0fad9ed57cd5b1723f85ad44f5d
prerequisite-patch-id: e80ea7940b9817449cec21afa6e9e443e007166f
prerequisite-patch-id: 80d8ab865b7b0663c5b2878b45b55e2e4fde9c19
prerequisite-patch-id: 8e645e1c6ad6182de4813a726c293654324de1df
prerequisite-patch-id: f6781d2cf0829ccb32f1400623c95739972f2ee2
prerequisite-patch-id: 2acc300a68ed8c5364fb5f2f7d28fc0d56ab07bf
prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405
prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc
prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8
prerequisite-patch-id: 39475cddaf673b2cbbae703165a782916f199885
prerequisite-patch-id: 6f7f265abfbdffdc0a1fdc5a7e08929e4eec5b7a
prerequisite-patch-id: b5d7f75df02fde56181f576a936baf09d0a72276
prerequisite-patch-id: 3ce52e07ae57139c2e2b71a29ed7d7250f6fcc87
prerequisite-patch-id: 7d92e5a301d09616840e54dc9e4a81f30a64383c
prerequisite-patch-id: 003035cc99f02794043818256ba0ef657872d511
prerequisite-patch-id: 5d23c938843176de2a02987d2832f31fe5df7fcf
prerequisite-patch-id: 430488f50f36039338965ab1fc28d83f02dbc9fd
prerequisite-patch-id: 359ddad8a3fb36f171c96da5ce5ffacd7dd63e8f
prerequisite-patch-id: a98885b9d0e0655bb3161dc2c31fd92a844a5e4e
prerequisite-patch-id: 80aead6484e36f52cb6cc7fd7d9e0326d8296860
prerequisite-patch-id: 2f1bd3efac328030dd8efe28fb95f84603868043
prerequisite-patch-id: 047b4fb1894b92109aa7afcebd7d5c7988ec5379
prerequisite-patch-id: 99977ae9253a961b85331b9808c1feff0c2cc38e
prerequisite-patch-id: 9e3edab83e9fc008b2dc254fb3b548ddd8f8b5f8
prerequisite-patch-id: a7706e25f5951ec41e6b662c1704df8d20662d77
prerequisite-patch-id: d13035abab3ff342753f5bf87b53bbf06a02c6a1
prerequisite-patch-id: 4d40e704139dc4b0ec2529c49f096d86a4e4dc5f
--
2.34.1
^ permalink raw reply
* [PATCH v1 1/8] ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Add support for the modem_apps GLINK channel on Shikra, as audio
processing is handled through the modem DSP.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml
index e51acdcaafaf..01250b556985 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml
@@ -120,7 +120,9 @@ allOf:
properties:
qcom,glink-channels:
items:
- - const: adsp_apps
+ - enum:
+ - adsp_apps
+ - modem_apps
power-domains: false
else:
properties:
--
2.34.1
^ permalink raw reply related
* [PATCH v1 2/8] arm64: dts: qcom: shikra: Add QAIF CPU node for audio
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
Harendra Gautam
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Add the QAIF CPU endpoint in shikra.dtsi so board files can connect LPASS
front-end links to backend codecs.
Describe the MMIO region, interrupt, IOMMU mapping and required clocks for
the QAIF block. Keep the node disabled at SoC level; board dts files enable
and consume it in subsequent patches.
Co-developed-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
Signed-off-by: Harendra Gautam <harendra.gautam@oss.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 46 ++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index bc4ad2bcbbec..e58c87fc8cb0 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2017,6 +2017,52 @@ dispcc: clock-controller@5f00000 {
#power-domain-cells = <1>;
};
+ qaif_cpu: audio@a000000 {
+ compatible = "qcom,shikra-qaif-cpu";
+ reg = <0x0 0x0a000000 0x0 0x20000>;
+
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_LPASS_CONFIG_CLK>,
+ <&gcc GCC_LPASS_CORE_AXIM_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_BUS_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>;
+ clock-names = "lpass_config_clk",
+ "lpass_core_axim_clk",
+ "aud_dma_clk",
+ "aud_dma_mem_clk",
+ "bus_clk",
+ "aif_if0_ebit_clk",
+ "aif_if0_ibit_clk",
+ "aif_if1_ebit_clk",
+ "aif_if1_ibit_clk",
+ "aif_if2_ebit_clk",
+ "aif_if2_ibit_clk",
+ "aif_if3_ebit_clk",
+ "aif_if3_ibit_clk",
+ "ext_mclka_clk",
+ "ext_mclkb_clk";
+
+ iommus = <&apps_smmu 0x1c0 0x0>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
audiocorecc: clock-controller@a0a0000 {
compatible = "qcom,shikra-cqm-audiocorecc";
reg = <0x0 0x0a0a0000 0x0 0x10000>,
--
2.34.1
^ permalink raw reply related
* [PATCH v1 3/8] arm64: dts: qcom: shikra: Add gpr node
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
Pratyush Meduri
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Add GPR(Generic Pack router) node along with
APM(Audio Process Manager) and PRM(Proxy resource
Manager) audio services.
Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 39 ++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e58c87fc8cb0..3df09cfd17a4 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-audiocorecc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
+#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -15,6 +16,8 @@
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/soc/qcom,gpr.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -1851,6 +1854,42 @@ glink-edge {
mboxes = <&apcs_glb 12>;
qcom,remote-pid = <1>;
label = "mpss";
+
+ gpr: gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "modem_apps";
+ qcom,domain = <GPR_DOMAIN_ID_MODEM>;
+ qcom,intents = <200 20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ q6apm: service@1 {
+ compatible = "qcom,q6apm";
+ reg = <GPR_APM_MODULE_IID>;
+ #sound-dai-cells = <0>;
+
+ q6apmbedai: bedais {
+ compatible = "qcom,q6apm-lpass-dais";
+ #sound-dai-cells = <1>;
+ };
+
+ q6apmdai: dais {
+ compatible = "qcom,q6apm-dais";
+ qcom,vmid = <QCOM_SCM_VMID_LPASS
+ QCOM_SCM_VMID_MSS_MSA>;
+ };
+ };
+
+ q6prm: service@2 {
+ compatible = "qcom,q6prm";
+ reg = <GPR_PRM_MODULE_IID>;
+
+ q6prmcc: clock-controller {
+ compatible = "qcom,q6prm-lpass-clocks";
+ #clock-cells = <2>;
+ };
+ };
+ };
};
};
--
2.34.1
^ permalink raw reply related
* [PATCH v1 4/8] arm64: dts: qcom: shikra: Add soundwire and macro nodes
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Add SoC-level SoundWire masters and LPASS RX/VA macro nodes, along with
DMIC and SWR pinctrl states required by the audio data path.
Keep these nodes disabled in shikra.dtsi so board dts files can selectively
enable and configure them.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 171 +++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 3df09cfd17a4..0ed73b948588 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -833,6 +833,70 @@ rclk-pins {
bias-bus-hold;
};
};
+
+ dmic01_default: dmic01-default-state {
+ clk-pins {
+ pins = "gpio96";
+ function = "dmic";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio97";
+ function = "dmic";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ dmic23_default: dmic23-default-state {
+ clk-pins {
+ pins = "gpio98";
+ function = "dmic";
+ drive-strength = <8>;
+ output-high;
+ };
+
+ data-pins {
+ pins = "gpio99";
+ function = "dmic";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_active: tx-swr-active-state {
+ clk-pins {
+ pins = "gpio105";
+ function = "swr0_tx";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio106";
+ function = "swr0_tx";
+ drive-strength = <8>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_active: rx-swr-active-state {
+ clk-pins {
+ pins = "gpio107";
+ function = "swr0_rx";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ data-pins {
+ pins = "gpio108", "gpio109";
+ function = "swr0_rx";
+ drive-strength = <8>;
+ bias-bus-hold;
+ };
+ };
};
pmu@c91000 {
@@ -2114,6 +2178,113 @@ audiocorecc: clock-controller@a0a0000 {
status = "disabled";
};
+ rxmacro: codec@a040000 {
+ compatible = "qcom,shikra-lpass-rx-macro";
+ reg = <0x0 0x0a040000 0x0 0x1000>;
+
+ pinctrl-0 = <&rx_swr_active>;
+ pinctrl-names = "default";
+
+ clocks = <&audiocorecc AUDIO_CORE_CC_RX_MCLK_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_RX_MCLK_2X_CLK>,
+ <&vamacro>;
+ clock-names = "mclk",
+ "npl",
+ "fsgen";
+
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+ #sound-dai-cells = <1>;
+ status = "disabled";
+ };
+
+ swr0: soundwire@a060000 {
+ compatible = "qcom,soundwire-v3.1.0";
+ reg = <0x0 0x0a060000 0x0 0x10000>;
+ qcom,swr-master-ee-val = <0>;
+
+ interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&rxmacro>;
+ clock-names = "iface";
+
+ label = "RX";
+ qcom,din-ports = <0>;
+ qcom,dout-ports = <5>;
+
+ resets = <&audiocorecc AUDIO_CORE_CSR_RX_SWR_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ vamacro: codec@a078000 {
+ compatible = "qcom,shikra-lpass-va-macro";
+ reg = <0x0 0x0a078000 0x0 0x2000>;
+
+ pinctrl-0 = <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ clocks = <&audiocorecc AUDIO_CORE_CC_TX_MCLK_CLK>,
+ <&audiocorecc AUDIO_CORE_CC_TX_MCLK_2X_CLK>;
+ clock-names = "mclk",
+ "npl";
+
+ #clock-cells = <0>;
+ #sound-dai-cells = <1>;
+ clock-output-names = "fsgen";
+ status = "disabled";
+ };
+
+ swr1: soundwire@a080000 {
+ compatible = "qcom,soundwire-v3.1.0";
+ reg = <0x0 0x0a080000 0x0 0x10000>;
+ qcom,swr-master-ee-val = <0>;
+
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "core", "wakeup";
+
+ clocks = <&vamacro>;
+ clock-names = "iface";
+
+ label = "VA_TX";
+
+ qcom,din-ports = <4>;
+ qcom,dout-ports = <0>;
+
+ resets = <&audiocorecc AUDIO_CORE_CSR_TX_SWR_CGCR>;
+ reset-names = "swr_audio_cgcr";
+
+ qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
+ qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
+ qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
+ qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
+
+ #sound-dai-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 5/8] arm64: dts: qcom: shikra-cqm-evk: Enable sound card support
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Enable the sound card on the shikra-cqm-evk platform, including
the PM4125 (Rouleur) headset codec, WSA885x external speaker path,
and QAIF backend links.
Also enable the required LPASS macro and SoundWire nodes, along with
the necessary pinctrl configurations for DMIC and I2S interfaces.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 222 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 5 +
2 files changed, 227 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index b88652703fb8..b68d196b9d04 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/sound/qcom,qaif.h>
#include "shikra-cqm-som.dtsi"
#include "shikra-evk.dtsi"
@@ -23,6 +24,74 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ sound: sound {
+ compatible = "qcom,shikra-cqm-sndcard";
+ model = "shikra-cqm-evk";
+
+ audio-routing = "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "AMIC2", "MIC BIAS2",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb";
+
+ pinctrl-0 = <&i2s2_default>, <&dmic_eldo_en_default>;
+ pinctrl-names = "default";
+
+ headset-capture-dai-link {
+ link-name = "Headphones Capture";
+
+ codec {
+ sound-dai = <&pmic4125_codec 1>,
+ <&swr1 0>,
+ <&vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&qaif_cpu QAIF_CDC_DMA_VA_TX0>;
+ };
+ };
+
+ headset-playback-dai-link {
+ link-name = "Headphones Playback";
+
+ codec {
+ sound-dai = <&pmic4125_codec 0>,
+ <&swr0 0>,
+ <&rxmacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&qaif_cpu QAIF_CDC_DMA_RX0>;
+ };
+ };
+
+ wsa-speaker-dai-link {
+ link-name = "WSA Speaker Playback";
+
+ codec {
+ sound-dai = <&wsa885x_i2c>;
+ };
+
+ cpu {
+ sound-dai = <&qaif_cpu QAIF_MI2S_TDM_AIF2>;
+ };
+ };
+
+ va-dmic-dai-link {
+ link-name = "VA DMIC Capture";
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&qaif_cpu QAIF_CDC_DMA_VA_TX0>;
+ };
+ };
+ };
+
wcn3988-pmu {
compatible = "qcom,wcn3988-pmu";
@@ -60,6 +129,79 @@ vreg_pmu_ch1: ldo4 {
};
};
+&gpr {
+ status = "disabled";
+};
+
+&i2c3 {
+ status = "okay";
+
+ wsa885x_i2c: speaker@c {
+ compatible = "qcom,wsa885x-i2c";
+ reg = <0x0c>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa885x_i2c_spkr_sd_n>;
+
+ interrupt-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ vdd-1p8-supply = <&pm4125_l15>;
+ vdd-io-supply = <&pm4125_l15>;
+ qcom,battery-config = <2>;
+
+ qcom,wsa885x-init-table =
+ <0x8470 0x2
+ 0x8470 0x0
+ 0x8470 0x1
+ 0x0004 0x1
+ 0x8602 0x60
+ 0x8622 0x60
+ 0x8458 0x79
+ 0x810B 0xD9
+ 0x8111 0xD9
+ 0x813C 0x08
+ 0x8102 0x04
+ 0x811C 0x29
+ 0x811D 0x40
+ 0x8129 0x40
+ 0x811A 0x80
+ 0x8126 0x80
+ 0x8103 0x6
+ 0x80CA 0x85
+ 0x80CB 0xE
+ 0x80CC 0xC
+ 0x80D0 0x80
+ 0x80BA 0xC0
+ 0x841C 0x4E
+ 0x8435 0x47
+ 0x86CE 0x09
+ 0x8667 0x34
+ 0x800D 0x08>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&qaif_cpu {
+ status = "okay";
+ qaif_aif_if2: aif-interface@2 {
+ compatible = "qcom,qaif-tdm-dai";
+ reg = <QAIF_MI2S_TDM_AIF2>;
+ qcom,qaif-aif-sync-mode = <QAIF_AIF_SYNC_MODE_LONG>;
+ qcom,qaif-aif-sync-src = <QAIF_AIF_SYNC_SRC_MASTER>;
+ qcom,qaif-aif-sync-delay = <1>;
+ qcom,qaif-aif-slot-width-rx = <32>;
+ qcom,qaif-aif-slot-width-tx = <32>;
+ qcom,qaif-aif-slot-en-rx-mask = <0x3>;
+ qcom,qaif-aif-slot-en-tx-mask = <0x3>;
+ qcom,qaif-aif-ctrl-data-oe;
+ /* Lane 0: RX (mic); Lane 1: TX (speaker) */
+ qcom,qaif-aif-lane-config = <QAIF_AIF_LANE_ENABLE QAIF_AIF_LANE_DIR_RX>,
+ <QAIF_AIF_LANE_ENABLE QAIF_AIF_LANE_DIR_TX>;
+ /* frame length = slot-width (32) * bits-per-lane (2) = 64 bits */
+ qcom,qaif-aif-bits-per-lane = <2>;
+ };
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
@@ -79,6 +221,10 @@ &remoteproc_mpss {
status = "okay";
};
+&rxmacro {
+ status = "okay";
+};
+
&audiocorecc {
status = "okay";
};
@@ -99,6 +245,74 @@ &sdhc_1 {
status = "okay";
};
+&spmi_bus {
+ pmic@0 {
+ pmic4125_codec: audio-codec@f000 {
+ compatible = "qcom,pm4125-codec";
+ reg = <0xf000>;
+ vdd-io-supply = <&pm4125_l15>;
+ vdd-cp-supply = <&pm4125_s1>;
+ vdd-pa-vpos-supply = <&pm4125_s1>;
+
+ vdd-mic-bias-supply = <&pm4125_l22>;
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+
+ qcom,rx-device = <&pm4125_rx>;
+ qcom,tx-device = <&pm4125_tx>;
+ #sound-dai-cells = <1>;
+
+ status = "okay";
+ };
+ };
+};
+
+&swr0 {
+ status = "okay";
+
+ pm4125_rx: codec@0,4 {
+ compatible = "sdw20217010c00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+};
+
+&swr1 {
+ status = "okay";
+
+ pm4125_tx: codec@0,3 {
+ compatible = "sdw20217010c00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 2 3 4>;
+ };
+};
+
+&tlmm {
+ dmic_eldo_en_default: dmic-eldo-default-active-state {
+ pins = "gpio71";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ i2s2_default: i2s2-default-active-state {
+ pins = "gpio100", "gpio101", "gpio102", "gpio103";
+ function = "i2s2";
+ drive-strength = <8>;
+ output-high;
+ bias-disable;
+ };
+
+ wsa885x_i2c_spkr_sd_n: wsa885x-i2c-spkr-sd-n-active-state {
+ pins = "gpio2";
+ function = "gpio";
+ input-disable;
+ output-enable;
+ };
+};
+
&uart8 {
status = "okay";
@@ -110,6 +324,14 @@ bluetooth {
};
};
+&vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ qcom,dmic-sample-rate = <4800000>;
+ status = "okay";
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&vreg_pmu_xo>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
index dc3861489f64..86b323f2fa58 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
@@ -53,6 +53,11 @@ &rpm_requests {
regulators {
compatible = "qcom,rpm-pm2250-regulators";
+ pm4125_s1: s1 {
+ regulator-min-microvolt = <1396000>;
+ regulator-max-microvolt = <1396000>;
+ };
+
pm4125_s2: s2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1200000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 6/8] arm64: dts: qcom: shikra-cqs-evk: Enable sound card support
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
Pratyush Meduri
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Enable the sound card on the shikra-cqs-evk platform, including
WSA885x external speaker path and DMIC via VA macro
Also enable the required LPASS macro along with the necessary
pinctrl configurations for DMIC and I2S interfaces.
Co-developed-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
Signed-off-by: Pratyush Meduri <mpratyus@qti.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 149 ++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index 6498ef47bf3a..76d41b645741 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,57 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ sound {
+ compatible = "qcom,shikra-cqs-sndcard";
+ model = "shikra-cqs-evk";
+
+ pinctrl-0 = <&i2s2_default>, <&dmic_eldo_en_default>;
+ pinctrl-names = "default";
+
+ audio-routing = "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb";
+
+ va-dmic-dai-link {
+ link-name = "VA DMIC Capture";
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ wsa-playback-dai-link {
+ link-name = "WSA Playback";
+
+ codec {
+ sound-dai = <&wsa885x_i2c>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai SECONDARY_TDM_RX_0>;
+ dai-tdm-slot-num = <2>;
+ dai-tdm-slot-width = <32>;
+ dai-tdm-slot-rx-mask = <1 1>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
wcn3988-pmu {
compatible = "qcom,wcn3988-pmu";
@@ -60,6 +111,66 @@ vreg_pmu_ch1: ldo4 {
};
};
+&i2c3 {
+ status = "okay";
+
+ wsa885x_i2c: speaker@c {
+ compatible = "qcom,wsa885x-i2c";
+ reg = <0x0c>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wsa885x_i2c_spkr_sd_n>;
+
+ interrupt-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+ vdd-1p8-supply = <&pm4125_l15>;
+ vdd-io-supply = <&pm4125_l15>;
+ qcom,battery-config = <2>;
+
+ qcom,wsa885x-init-table =
+ <0x8470 0x2
+ 0x8470 0x0
+ 0x8470 0x1
+ 0x0004 0x1
+ 0x8602 0x60
+ 0x8622 0x60
+ 0x8458 0x79
+ 0x810B 0xD9
+ 0x8111 0xD9
+ 0x813C 0x08
+ 0x8102 0x04
+ 0x811C 0x29
+ 0x811D 0x40
+ 0x8129 0x40
+ 0x811A 0x80
+ 0x8126 0x80
+ 0x8103 0x6
+ 0x80CA 0x85
+ 0x80CB 0xE
+ 0x80CC 0xC
+ 0x80D0 0x80
+ 0x80BA 0xC0
+ 0x841C 0x4E
+ 0x8435 0x47
+ 0x86CE 0x09
+ 0x8667 0x34
+ 0x800D 0x08>;
+
+ #sound-dai-cells = <0>;
+ };
+};
+
+&q6apmbedai {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dai@40 {
+ reg = <SECONDARY_TDM_RX_0>;
+ clocks = <&q6prmcc LPASS_CLK_ID_AUD_INTF2_IBIT
+ LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "bclk";
+ };
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
@@ -100,6 +211,31 @@ &sdhc_1 {
status = "okay";
};
+&tlmm {
+ dmic_eldo_en_default: dmic-eldo-default-active-state {
+ pins = "gpio71";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ i2s2_default: i2s2-default-active-state {
+ pins = "gpio100", "gpio101", "gpio102", "gpio103";
+ function = "i2s2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ wsa885x_i2c_spkr_sd_n: wsa885x-i2c-spkr-sd-n-active-state {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <8>;
+ input-disable;
+ output-enable;
+ };
+};
+
&uart8 {
status = "okay";
@@ -111,6 +247,19 @@ bluetooth {
};
};
+&vamacro {
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&tx_swr_active>;
+ pinctrl-names = "default";
+
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk",
+ "npl";
+
+ qcom,dmic-sample-rate = <4800000>;
+ status = "okay";
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&vreg_pmu_xo>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 7/8] arm64: dts: qcom: shikra-iqs-evk: Enable sound card support
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel,
Ajay Kumar Nandam
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Enable the IQS EVK audio card using MAX98091 on I2S0 for primary
playback/capture and VA DMIC capture through q6apm backend links.
Add board clock and pinctrl states required for codec IRQ, external
mclk and digital mic routing.
Co-developed-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 143 ++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index fd691d53a0fa..62f405578172 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,75 @@ chosen {
stdout-path = "serial0:115200n8";
};
+ sound {
+ compatible = "qcom,shikra-iqs-sndcard";
+ model = "shikra-iqs-evk";
+
+ pinctrl-0 = <&i2s0_default>, <&ext_mclk2_active>;
+ pinctrl-names = "default";
+
+ audio-routing = "IN34", "Headset Mic",
+ "Headset Mic", "MICBIAS",
+ "DMICL", "Int Mic",
+ "Int Mic", "MICBIAS",
+ "Headphone", "HPL",
+ "Headphone", "HPR",
+ "Speaker", "SPKL",
+ "Speaker", "SPKR",
+ "VA DMIC0", "vdd-micb",
+ "VA DMIC1", "vdd-micb",
+ "VA DMIC2", "vdd-micb",
+ "VA DMIC3", "vdd-micb";
+
+ pri-i2s-playback-dai-link {
+ link-name = "Analog Playback";
+
+ codec {
+ sound-dai = <&max98091>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ pri-i2s-capture-dai-link {
+ link-name = "Analog Capture";
+
+ codec {
+ sound-dai = <&max98091>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai PRIMARY_MI2S_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+
+ va-dmic-dai-link {
+ link-name = "VA DMIC Capture";
+
+ codec {
+ sound-dai = <&vamacro 0>;
+ };
+
+ cpu {
+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
+ };
+
+ platform {
+ sound-dai = <&q6apm>;
+ };
+ };
+ };
+
vreg_wcn_3p3: regulator-wcn-3p3 {
compatible = "regulator-fixed";
regulator-name = "wcn_3p3";
@@ -68,6 +137,36 @@ vreg_pmu_ch1: ldo4 {
};
};
+&i2c3 {
+ status = "okay";
+
+ max98091: audio-codec@10 {
+ compatible = "maxim,max98091";
+ reg = <0x10>;
+
+ pinctrl-0 = <&max98091_default>;
+ pinctrl-names = "default";
+
+ interrupts-extended = <&tlmm 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk";
+ assigned-clocks = <&q6prmcc LPASS_CLK_ID_MCLK_2 LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ assigned-clock-rates = <12288000>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&q6apmbedai {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dai@16 {
+ reg = <PRIMARY_MI2S_RX>;
+ clocks = <&q6prmcc LPASS_CLK_ID_AUD_INTF0_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "bclk";
+ };
+};
+
&remoteproc_cdsp {
firmware-name = "qcom/shikra/cdsp.mbn";
@@ -103,6 +202,36 @@ &sdhc_1 {
status = "okay";
};
+&tlmm {
+ dmic_eldo_en_default: dmic-eldo-default-active-state {
+ pins = "gpio71";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ output-high;
+ };
+
+ ext_mclk2_active: ext-mclk2-state {
+ pins = "gpio110";
+ function = "ext_mclk";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ i2s0_default: i2s0-default-active-state {
+ pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109";
+ function = "i2s0";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ max98091_default: max98091-default-state {
+ pins = "gpio28";
+ function = "gpio";
+ bias-pull-up;
+ };
+};
+
&uart8 {
status = "okay";
@@ -114,6 +243,20 @@ bluetooth {
};
};
+&vamacro {
+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+ <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+ clock-names = "mclk",
+ "npl";
+
+ pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&dmic_eldo_en_default>;
+ pinctrl-names = "default";
+
+ qcom,dmic-sample-rate = <4800000>;
+
+ status = "okay";
+};
+
&wifi {
vdd-0.8-cx-mx-supply = <&pm8150_s4>;
vdd-1.8-xo-supply = <&vreg_pmu_xo>;
--
2.34.1
^ permalink raw reply related
* [PATCH v1 8/8] arm64: defconfig: Enable Qualcomm QAIF and WSA885X-I2C drivers
From: Mohammad Rafi Shaik @ 2026-06-16 20:13 UTC (permalink / raw)
To: Srinivas Kandagatla, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-sound, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com>
Enable the QAIF CPU DAI and WSA885X I2C codec as modules in
arm64 defconfig.
These options are required to exercise the Shikra EVK
audio paths enabled by the preceding DTS changes.
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 271589322efd..067f4ecc05bf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1099,6 +1099,7 @@ CONFIG_SND_SOC_QCOM=m
CONFIG_SND_SOC_APQ8016_SBC=m
CONFIG_SND_SOC_QDSP6_USB=m
CONFIG_SND_SOC_MSM8996=m
+CONFIG_SND_SOC_QCOM_QAIF=m
CONFIG_SND_SOC_SDM845=m
CONFIG_SND_SOC_SM8250=m
CONFIG_SND_SOC_SC8280XP=m
@@ -1175,6 +1176,7 @@ CONFIG_SND_SOC_WM8978=m
CONFIG_SND_SOC_WSA881X=m
CONFIG_SND_SOC_WSA883X=m
CONFIG_SND_SOC_WSA884X=m
+CONFIG_SND_SOC_WSA885X_I2C=m
CONFIG_SND_SOC_NAU8822=m
CONFIG_SND_SOC_LPASS_WSA_MACRO=m
CONFIG_SND_SOC_LPASS_VA_MACRO=m
--
2.34.1
^ permalink raw reply related
* Re: [PATCH] dt-bindings: sound: add toshiba,apb-dummy-codec binding
From: Mark Brown @ 2026-06-16 20:23 UTC (permalink / raw)
To: Pablo D. Bergamasco
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vaibhav Agarwal,
Mark Greer, Liam Girdwood, linux-sound, devicetree, linux-kernel
In-Reply-To: <20260616185619.1581174-1-danpablo@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 525 bytes --]
On Tue, Jun 16, 2026 at 03:56:19PM -0300, Pablo D. Bergamasco wrote:
> Add device tree binding documentation for the Toshiba APBridge
> dummy ALSA SoC codec used in the Greybus audio framework.
Please submit patches using subject lines reflecting the style for the
subsystem, this makes it easier for people to identify relevant patches.
Look at what existing commits in the area you're changing are doing and
make sure your subject lines visually resemble what they're doing.
There's no need to resubmit to fix this alone.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH RFC v4 00/12] ZTE zx297520v3 clock bindings and driver
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
Hi,
I am sending version 4 of my zx297520v3 clock patch. The major change is
using regmaps rather than raw mmio to access the clocks and moving reset
handling into its own aux bus driver.
I think the list of clocks in my driver is fairly complete; It is
certainly a lot better than what the downstream ZTE drivers have. I
deduced a lot of it by trial and error. I am sure there are some clocks
missing that will need to be added to the binding later. Afaiu adding
clocks is not an issue, but removing or reordering them is an ABI break.
I expect Sashiko to find a lot of slopiness mistakes, so I kept the
[RFC] tag for this submission.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Changes in v4:
*) Use syscon and regmap instead of raw IO
*) Move reset to its own driver on the aux bus, but keep reset and clk
in the same binding as it matches the way the hardware works
*) Go back to having matrixclk in its own device because syscon deals
poorly with multi io reg devices. List all PLL outputs from topclk as
inputs to matrixclk
*) Some more hardware research: Figure out the parents of the 4 possible
GPIO clock outputs and declare them in the driver. They are unused on
the hardware I have, but they show that all PLLs can be used.
- Link to v3: https://lore.kernel.org/r/20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com
Changes in v3:
Model top and matrix clocks as one device
Add PLL driver
Fixed a few issues found by Sashiko: register lock, some missing devm_,
error handling
v2: Fix build issues introduced by checkpatch.pl fixes that I didn't
spot earlier.
---
Stefan Dösinger (12):
dt-bindings: clk: zte: Add zx297520v3 top clock and reset bindings
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset bindings
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings
clk: zte: Add Clock registration infrastructure.
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap based clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 LSP clocks
reset: zte: Add a zx297520v3 reset driver
ARM: dts: zte: Declare zx297520v3 clock device nodes
ARM: dts: zte: Add a syscon-reboot for zx297520v3 boards
.../bindings/clock/zte,zx297520v3-lspclk.yaml | 130 ++++
.../bindings/clock/zte,zx297520v3-matrixclk.yaml | 180 +++++
.../bindings/clock/zte,zx297520v3-topclk.yaml | 70 ++
MAINTAINERS | 4 +
arch/arm/boot/dts/zte/zx297520v3.dtsi | 97 ++-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/zte/Kconfig | 28 +
drivers/clk/zte/Makefile | 6 +
drivers/clk/zte/clk-regmap.c | 247 +++++++
drivers/clk/zte/clk-zx.c | 157 ++++
drivers/clk/zte/clk-zx.h | 79 ++
drivers/clk/zte/clk-zx297520v3.c | 795 +++++++++++++++++++++
drivers/clk/zte/pll-zx.c | 477 +++++++++++++
drivers/reset/Kconfig | 11 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-zte-zx297520v3.c | 224 ++++++
include/dt-bindings/clock/zte,zx297520v3-clk.h | 219 ++++++
18 files changed, 2718 insertions(+), 9 deletions(-)
---
base-commit: c1ecb239fa3456529a32255359fc78b69eb9d847
change-id: 20260510-zx29clk-2e4d39e3128c
Best regards,
--
Stefan Dösinger <stefandoesinger@gmail.com>
^ permalink raw reply
* [PATCH RFC v4 01/12] dt-bindings: clk: zte: Add zx297520v3 top clock and reset bindings
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com>
These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. The
separation of concerns between Top and Matrix and the interface between
them is poorly defined in the hardware, so the bindings list all
potential PLL clocks that might be passed between them.
Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.
The top clock controller is fed by a 26mhz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-Related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.
Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.
The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
.../bindings/clock/zte,zx297520v3-topclk.yaml | 70 ++++++++++++
MAINTAINERS | 2 +
include/dt-bindings/clock/zte,zx297520v3-clk.h | 118 +++++++++++++++++++++
3 files changed, 190 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-topclk.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topclk.yaml
new file mode 100644
index 000000000000..374f63891288
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-topclk.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zte,zx297520v3-topclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC top clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ The zx297520v3's top clock controller generates clocks for core devices on the
+ board like the main bus, USB and timers. In addition to clocks it has reset
+ controls for peripherals, a global board reset and watchdog reset controls.
+
+ The controller has two clock inputs: a 26 MHz and a 32 KHz external
+ oscillator. They need to be provided as input clocks. The controller provides
+ clocks to the downstream Matrix clock controller.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header.
+
+properties:
+ compatible:
+ items:
+ - const: zte,zx297520v3-topclk
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 26 MHz external oscillator
+ - description: 32 KHz external oscillator
+
+ clock-names:
+ items:
+ - const: osc26m
+ - const: osc32k
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+
+ clock-controller@13b000 {
+ compatible = "zte,zx297520v3-topclk", "syscon";
+ reg = <0x0013b000 0x400>;
+ clocks = <&osc26m>, <&osc32k>;
+ clock-names = "osc26m", "osc32k";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 8629ed2aa82f..0cc1ede3c80c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3867,8 +3867,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
+F: Documentation/devicetree/zte,zx297520v3-*
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
+F: include/dt-bindings/clock/zte,zx297520v3-clk.h
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@amd.com>
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
new file mode 100644
index 000000000000..cf436ff20dfe
--- /dev/null
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H
+#define __DT_BINDINGS_CLOCK_ZX297520V3_H
+
+#define ZX297520V3_M0_WCLK 1
+#define ZX297520V3_SRAM1_PCLK 2
+#define ZX297520V3_SRAM2_PCLK 3
+#define ZX297520V3_UART0_WCLK 4
+#define ZX297520V3_UART0_PCLK 5
+#define ZX297520V3_I2C0_WCLK 6
+#define ZX297520V3_I2C0_PCLK 7
+#define ZX297520V3_RTC_WCLK 8
+#define ZX297520V3_RTC_PCLK 9
+#define ZX297520V3_LPM_GSM_WCLK 10
+#define ZX297520V3_LPM_GSM_PCLK 11
+#define ZX297520V3_LPM_LTE_WCLK 12
+#define ZX297520V3_LPM_LTE_PCLK 13
+#define ZX297520V3_LPM_TD_WCLK 14
+#define ZX297520V3_LPM_TD_PCLK 15
+#define ZX297520V3_LPM_W_WCLK 16
+#define ZX297520V3_LPM_W_PCLK 17
+#define ZX297520V3_TIMER_T08_WCLK 18
+#define ZX297520V3_TIMER_T08_PCLK 19
+#define ZX297520V3_TIMER_T09_WCLK 20
+#define ZX297520V3_TIMER_T09_PCLK 21
+#define ZX297520V3_MPLL 22
+#define ZX297520V3_MPLL_D2 23
+#define ZX297520V3_MPLL_D3 24
+#define ZX297520V3_MPLL_D4 25
+#define ZX297520V3_MPLL_D5 26
+#define ZX297520V3_MPLL_D6 27
+#define ZX297520V3_MPLL_D8 28
+#define ZX297520V3_MPLL_D12 29
+#define ZX297520V3_MPLL_D16 30
+#define ZX297520V3_MPLL_D26 31
+#define ZX297520V3_UPLL 32
+#define ZX297520V3_UPLL_D2 33
+#define ZX297520V3_UPLL_D3 34
+#define ZX297520V3_UPLL_D4 35
+#define ZX297520V3_UPLL_D5 36
+#define ZX297520V3_UPLL_D6 37
+#define ZX297520V3_UPLL_D8 38
+#define ZX297520V3_UPLL_D12 39
+#define ZX297520V3_UPLL_D16 40
+#define ZX297520V3_DPLL 41
+#define ZX297520V3_DPLL_D2 42
+#define ZX297520V3_DPLL_D3 43
+#define ZX297520V3_DPLL_D4 44
+#define ZX297520V3_DPLL_D5 45
+#define ZX297520V3_DPLL_D6 46
+#define ZX297520V3_DPLL_D8 47
+#define ZX297520V3_DPLL_D12 48
+#define ZX297520V3_DPLL_D16 49
+#define ZX297520V3_GPLL 50
+#define ZX297520V3_GPLL_D2 51
+#define ZX297520V3_GPLL_D3 52
+#define ZX297520V3_GPLL_D4 53
+#define ZX297520V3_GPLL_D5 54
+#define ZX297520V3_GPLL_D6 55
+#define ZX297520V3_GPLL_D8 56
+#define ZX297520V3_GPLL_D12 57
+#define ZX297520V3_GPLL_D16 58
+#define ZX297520V3_PMM_WCLK 59
+#define ZX297520V3_PMM_PCLK 60
+#define ZX297520V3_OUT0_WCLK 61
+#define ZX297520V3_OUT1_WCLK 62
+#define ZX297520V3_OUT2_WCLK 63
+#define ZX297520V3_OUT32K_WCLK 64
+#define ZX297520V3_RMIIPHY_WCLK 65
+#define ZX297520V3_TIMER_T12_WCLK 66
+#define ZX297520V3_TIMER_T12_PCLK 67
+#define ZX297520V3_TIMER_T13_WCLK 68
+#define ZX297520V3_TIMER_T13_PCLK 69
+#define ZX297520V3_TIMER_T14_WCLK 70
+#define ZX297520V3_TIMER_T14_PCLK 71
+#define ZX297520V3_TIMER_T15_WCLK 72
+#define ZX297520V3_TIMER_T15_PCLK 73
+#define ZX297520V3_TIMER_T16_WCLK 74
+#define ZX297520V3_TIMER_T16_PCLK 75
+#define ZX297520V3_TIMER_T17_WCLK 76
+#define ZX297520V3_TIMER_T17_PCLK 77
+#define ZX297520V3_WDT_T18_WCLK 78
+#define ZX297520V3_WDT_T18_PCLK 79
+#define ZX297520V3_USIM1_WCLK 80
+#define ZX297520V3_USIM1_PCLK 81
+#define ZX297520V3_AHB_WCLK 82
+#define ZX297520V3_AHB_PCLK 83
+#define ZX297520V3_USB_WCLK 84
+#define ZX297520V3_USB_PCLK 85
+#define ZX297520V3_HSIC_WCLK 86
+#define ZX297520V3_HSIC_PCLK 87
+
+#define ZX297520V3_ZSP_RESET 0
+#define ZX297520V3_UART0_RESET 1
+#define ZX297520V3_I2C0_RESET 2
+#define ZX297520V3_RTC_RESET 3
+#define ZX297520V3_TIMER_T08_RESET 4
+#define ZX297520V3_TIMER_T09_RESET 5
+#define ZX297520V3_PMM_RESET 6
+#define ZX297520V3_GPIO_RESET 7
+#define ZX297520V3_GPIO8_RESET 8
+#define ZX297520V3_TIMER_T12_RESET 9
+#define ZX297520V3_TIMER_T13_RESET 10
+#define ZX297520V3_TIMER_T14_RESET 11
+#define ZX297520V3_TIMER_T15_RESET 12
+#define ZX297520V3_TIMER_T16_RESET 13
+#define ZX297520V3_TIMER_T17_RESET 14
+#define ZX297520V3_WDT_T18_RESET 15
+#define ZX297520V3_USIM1_RESET 16
+#define ZX297520V3_AHB_RESET 17
+#define ZX297520V3_USB_RESET 18
+#define ZX297520V3_HSIC_RESET 19
+
+#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v4 02/12] dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset bindings
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com>
I split matrixclk into its own controller again because syscon/regmap
deals poorly with device nodes that have more than one memory region. As
a consequence I am passing all PLL outputs generated on Topclk down to
Matrixclk.
The syscon is used to generate the regmap shared between the clock and
auxiliary reset drivers. The register space also contains at least one
extra block of functionality, hardware spinlocks, that I expect will be
necessary to communicate correctly with the LTE DSP firmware blob.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
.../bindings/clock/zte,zx297520v3-matrixclk.yaml | 180 +++++++++++++++++++++
include/dt-bindings/clock/zte,zx297520v3-clk.h | 45 ++++++
2 files changed, 225 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixclk.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixclk.yaml
new file mode 100644
index 000000000000..4363ed9be76f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-matrixclk.yaml
@@ -0,0 +1,180 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zte,zx297520v3-matrixclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC matrix clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ This controller controls high speed devices on the zx297520v3 board: The CPU,
+ RAM, SDIO and Ethernet clocks and resets are found here. This controller
+ requires PLL-generated clocks from Topclk as well as the fixed 26 MHz and 32
+ KHz oscillators found on this board.
+
+ Other helper controls are found on this hardware too: It contains a mailbox
+ interface to read RAM properties and hardware spinlock registers.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header.
+
+properties:
+ compatible:
+ items:
+ - const: zte,zx297520v3-matrixclk
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 26 MHz external oscillator
+ - description: 32 KHz external oscillator
+ - description: Main PLL output from topclk (usually 624 MHz)
+ - description: Main PLL subdivision factor 2
+ - description: Main PLL subdivision factor 3
+ - description: Main PLL subdivision factor 4
+ - description: Main PLL subdivision factor 5
+ - description: Main PLL subdivision factor 6
+ - description: Main PLL subdivision factor 8
+ - description: Main PLL subdivision factor 12
+ - description: Main PLL subdivision factor 16
+ - description: Main PLL subdivision factor 26
+ - description: Upll output from topclk (Usually 480 MHz)
+ - description: Upll subdivision factor 2
+ - description: Upll subdivision factor 3
+ - description: Upll subdivision factor 4
+ - description: Upll subdivision factor 5
+ - description: Upll subdivision factor 6
+ - description: Upll subdivision factor 8
+ - description: Upll subdivision factor 12
+ - description: Upll subdivision factor 16
+ - description: Dpll output from topclk (usually 492.88 MHz)
+ - description: Dpll subdivision factor 2
+ - description: Dpll subdivision factor 3
+ - description: Dpll subdivision factor 4
+ - description: Dpll subdivision factor 5
+ - description: Dpll subdivision factor 6
+ - description: Dpll subdivision factor 8
+ - description: Dpll subdivision factor 12
+ - description: Dpll subdivision factor 16
+ - description: Gpll output from topclk (usually 200 MHz)
+ - description: Gpll subdivision factor 2
+ - description: Gpll subdivision factor 3
+ - description: Gpll subdivision factor 4
+ - description: Gpll subdivision factor 5
+ - description: Gpll subdivision factor 6
+ - description: Gpll subdivision factor 8
+ - description: Gpll subdivision factor 12
+ - description: Gpll subdivision factor 16
+
+ clock-names:
+ items:
+ - const: osc26m
+ - const: osc32k
+ - const: mpll
+ - const: mpll_d2
+ - const: mpll_d3
+ - const: mpll_d4
+ - const: mpll_d5
+ - const: mpll_d6
+ - const: mpll_d8
+ - const: mpll_d12
+ - const: mpll_d16
+ - const: mpll_d26
+ - const: upll
+ - const: upll_d2
+ - const: upll_d3
+ - const: upll_d4
+ - const: upll_d5
+ - const: upll_d6
+ - const: upll_d8
+ - const: upll_d12
+ - const: upll_d16
+ - const: dpll
+ - const: dpll_d2
+ - const: dpll_d3
+ - const: dpll_d4
+ - const: dpll_d5
+ - const: dpll_d6
+ - const: dpll_d8
+ - const: dpll_d12
+ - const: dpll_d16
+ - const: gpll
+ - const: gpll_d2
+ - const: gpll_d3
+ - const: gpll_d4
+ - const: gpll_d5
+ - const: gpll_d6
+ - const: gpll_d8
+ - const: gpll_d12
+ - const: gpll_d16
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+
+ topclk: clock-controller@13b000 {
+ compatible = "zte,zx297520v3-topclk", "syscon";
+ reg = <0x0013b000 0x400>;
+ clocks = <&osc26m>, <&osc32k>;
+ clock-names = "osc26m", "osc32k";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@1306000 {
+ compatible = "zte,zx297520v3-matrixclk", "syscon";
+ reg = <0x01306000 0x400>;
+ clocks = <&osc26m>, <&osc32k>,
+ <&topclk ZX297520V3_MPLL>, <&topclk ZX297520V3_MPLL_D2>,
+ <&topclk ZX297520V3_MPLL_D3>, <&topclk ZX297520V3_MPLL_D4>,
+ <&topclk ZX297520V3_MPLL_D5>, <&topclk ZX297520V3_MPLL_D6>,
+ <&topclk ZX297520V3_MPLL_D8>, <&topclk ZX297520V3_MPLL_D12>,
+ <&topclk ZX297520V3_MPLL_D16>, <&topclk ZX297520V3_MPLL_D26>,
+ <&topclk ZX297520V3_UPLL>, <&topclk ZX297520V3_UPLL_D2>,
+ <&topclk ZX297520V3_UPLL_D3>, <&topclk ZX297520V3_UPLL_D4>,
+ <&topclk ZX297520V3_UPLL_D5>, <&topclk ZX297520V3_UPLL_D6>,
+ <&topclk ZX297520V3_UPLL_D8>, <&topclk ZX297520V3_UPLL_D12>,
+ <&topclk ZX297520V3_UPLL_D16>,
+ <&topclk ZX297520V3_DPLL>, <&topclk ZX297520V3_DPLL_D2>,
+ <&topclk ZX297520V3_DPLL_D3>, <&topclk ZX297520V3_DPLL_D4>,
+ <&topclk ZX297520V3_DPLL_D5>, <&topclk ZX297520V3_DPLL_D6>,
+ <&topclk ZX297520V3_DPLL_D8>, <&topclk ZX297520V3_DPLL_D12>,
+ <&topclk ZX297520V3_DPLL_D16>,
+ <&topclk ZX297520V3_GPLL>, <&topclk ZX297520V3_GPLL_D2>,
+ <&topclk ZX297520V3_GPLL_D3>, <&topclk ZX297520V3_GPLL_D4>,
+ <&topclk ZX297520V3_GPLL_D5>, <&topclk ZX297520V3_GPLL_D6>,
+ <&topclk ZX297520V3_GPLL_D8>, <&topclk ZX297520V3_GPLL_D12>,
+ <&topclk ZX297520V3_GPLL_D16>;
+ clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3",
+ "mpll_d4", "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12",
+ "mpll_d16", "mpll_d26", "upll", "upll_d2", "upll_d3",
+ "upll_d4", "upll_d5", "upll_d6", "upll_d8", "upll_d12",
+ "upll_d16", "dpll", "dpll_d2", "dpll_d3", "dpll_d4",
+ "dpll_d5", "dpll_d6", "dpll_d8", "dpll_d12", "dpll_d16",
+ "gpll", "gpll_d2", "gpll_d3", "gpll_d4", "gpll_d5",
+ "gpll_d6", "gpll_d8", "gpll_d12", "gpll_d16";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
index cf436ff20dfe..815e8ceeb64e 100644
--- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -115,4 +115,49 @@
#define ZX297520V3_USB_RESET 18
#define ZX297520V3_HSIC_RESET 19
+#define ZX297520V3_CPU_WCLK 1
+#define ZX297520V3_CPU_PCLK 2
+#define ZX297520V3_ZSP_WCLK 3
+#define ZX297520V3_EDCP_WCLK 4
+#define ZX297520V3_EDCP_PCLK 5
+#define ZX297520V3_SD0_WCLK 6
+#define ZX297520V3_SD0_PCLK 7
+#define ZX297520V3_SD0_CDET 8
+#define ZX297520V3_SD1_WCLK 9
+#define ZX297520V3_SD1_PCLK 10
+#define ZX297520V3_SD1_CDET 11
+#define ZX297520V3_NAND_WCLK 12
+#define ZX297520V3_NAND_PCLK 13
+#define ZX297520V3_DMA_PCLK 14
+#define ZX297520V3_MBOX_PCLK 15
+#define ZX297520V3_PDCFG_WCLK 16
+#define ZX297520V3_PDCFG_PCLK 17
+#define ZX297520V3_SSC_WCLK 18
+#define ZX297520V3_SSC_PCLK 19
+#define ZX297520V3_GMAC_WCLK 20
+#define ZX297520V3_GMAC_PCLK 21
+#define ZX297520V3_GMAC_AHB 22
+#define ZX297520V3_VOU_WCLK 23
+#define ZX297520V3_VOU_PCLK 24
+#define ZX297520V3_LSP_MPLL_D5_WCLK 25
+#define ZX297520V3_LSP_MPLL_D4_WCLK 26
+#define ZX297520V3_LSP_MPLL_D6_WCLK 27
+#define ZX297520V3_LSP_MPLL_D8_WCLK 28
+#define ZX297520V3_LSP_MPLL_D12_WCLK 29
+#define ZX297520V3_LSP_OSC26M_WCLK 30
+#define ZX297520V3_LSP_OSC32K_WCLK 31
+#define ZX297520V3_LSP_PCLK 32
+#define ZX297520V3_LSP_TDM_WCLK 33
+#define ZX297520V3_LSP_DPLL_D4_WCLK 34
+
+#define ZX297520V3_CPU_RESET 0
+#define ZX297520V3_EDCP_RESET 1
+#define ZX297520V3_SD0_RESET 2
+#define ZX297520V3_SD1_RESET 3
+#define ZX297520V3_NAND_RESET 4
+#define ZX297520V3_PDCFG_RESET 5
+#define ZX297520V3_SSC_RESET 6
+#define ZX297520V3_GMAC_RESET 7
+#define ZX297520V3_VOU_RESET 8
+
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v4 03/12] dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com>
The clock controller of the Low Speed Peripherals is relatively clean.
One register per device with gates, muxes and resets and for some
devices a divider. There are even bits in the top controller to control
propagation of clock lines down to LSP.
The clocks are sorted by register address and I am convinced that the
device list is complete. There are however a few more registers that are
likely helper controls for the I2S and TDM devices.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Patch changelog:
v5: Order properties compatible->reg->clocks->clock->names->#cells
---
.../bindings/clock/zte,zx297520v3-lspclk.yaml | 130 +++++++++++++++++++++
include/dt-bindings/clock/zte,zx297520v3-clk.h | 56 +++++++++
2 files changed, 186 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml
new file mode 100644
index 000000000000..096295edb6e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspclk.yaml
@@ -0,0 +1,130 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspclk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC LSP clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ This clock and reset controller controls low speed peripherals on the board.
+ This is a relatively isolated subsystem containing UART, I2C, I2S and SPI
+ devices. The clock controller is responsible for bringing the devices out of
+ reset and enabling their clocks as needed.
+
+ The controller receives its clock signal from the matrix controller and need
+ to be declared as clock inputs.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header.
+
+properties:
+ compatible:
+ const: zte,zx297520v3-lspclk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main PLL divided by 5 output from matrixclk (124.8 MHz)
+ - description: Main PLL divided by 4 output from matrixclk (156 MHz)
+ - description: Main PLL divided by 6 output from matrixclk (104 MHz)
+ - description: Main PLL divided by 8 output from matrixclk (78 MHz)
+ - description: Main PLL divided by 12 output from matrixclk (52 MHz)
+ - description: Main oscillator output from matrixclk (26 MHz)
+ - description: Timer oscillator output from matrixclk (32 KHz)
+ - description: LSP pclk output from matrixclk (26 MHz)
+ - description: TDM wclk mux output from matrixclk
+ - description: DPLL divided by 4 output from matrixclk (122.88 MHz)
+
+ clock-names:
+ items:
+ - const: mpll_d5
+ - const: mpll_d4
+ - const: mpll_d6
+ - const: mpll_d8
+ - const: mpll_d12
+ - const: osc26m
+ - const: osc32k
+ - const: pclk
+ - const: tdm_wclk
+ - const: dpll_d4
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+
+ matrixclk: clock-controller@1306000 {
+ compatible = "zte,zx297520v3-matrixclk", "syscon";
+ reg = <0x01306000 0x400>;
+ clocks = <&osc26m>, <&osc32k>,
+ <&topclk ZX297520V3_MPLL>, <&topclk ZX297520V3_MPLL_D2>,
+ <&topclk ZX297520V3_MPLL_D3>, <&topclk ZX297520V3_MPLL_D4>,
+ <&topclk ZX297520V3_MPLL_D5>, <&topclk ZX297520V3_MPLL_D6>,
+ <&topclk ZX297520V3_MPLL_D8>, <&topclk ZX297520V3_MPLL_D12>,
+ <&topclk ZX297520V3_MPLL_D16>, <&topclk ZX297520V3_MPLL_D26>,
+ <&topclk ZX297520V3_UPLL>, <&topclk ZX297520V3_UPLL_D2>,
+ <&topclk ZX297520V3_UPLL_D3>, <&topclk ZX297520V3_UPLL_D4>,
+ <&topclk ZX297520V3_UPLL_D5>, <&topclk ZX297520V3_UPLL_D6>,
+ <&topclk ZX297520V3_UPLL_D8>, <&topclk ZX297520V3_UPLL_D12>,
+ <&topclk ZX297520V3_UPLL_D16>,
+ <&topclk ZX297520V3_DPLL>, <&topclk ZX297520V3_DPLL_D2>,
+ <&topclk ZX297520V3_DPLL_D3>, <&topclk ZX297520V3_DPLL_D4>,
+ <&topclk ZX297520V3_DPLL_D5>, <&topclk ZX297520V3_DPLL_D6>,
+ <&topclk ZX297520V3_DPLL_D8>, <&topclk ZX297520V3_DPLL_D12>,
+ <&topclk ZX297520V3_DPLL_D16>,
+ <&topclk ZX297520V3_GPLL>, <&topclk ZX297520V3_GPLL_D2>,
+ <&topclk ZX297520V3_GPLL_D3>, <&topclk ZX297520V3_GPLL_D4>,
+ <&topclk ZX297520V3_GPLL_D5>, <&topclk ZX297520V3_GPLL_D6>,
+ <&topclk ZX297520V3_GPLL_D8>, <&topclk ZX297520V3_GPLL_D12>,
+ <&topclk ZX297520V3_GPLL_D16>;
+ clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3",
+ "mpll_d4", "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12",
+ "mpll_d16", "mpll_d26", "upll", "upll_d2", "upll_d3",
+ "upll_d4", "upll_d5", "upll_d6", "upll_d8", "upll_d12",
+ "upll_d16", "dpll", "dpll_d2", "dpll_d3", "dpll_d4",
+ "dpll_d5", "dpll_d6", "dpll_d8", "dpll_d12", "dpll_d16",
+ "gpll", "gpll_d2", "gpll_d3", "gpll_d4", "gpll_d5",
+ "gpll_d6", "gpll_d8", "gpll_d12", "gpll_d16";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock-controller@1400000 {
+ compatible = "zte,zx297520v3-lspclk";
+ reg = <0x01400000 0x100>;
+ clocks = <&matrixclk ZX297520V3_LSP_MPLL_D5_WCLK>,
+ <&matrixclk ZX297520V3_LSP_MPLL_D4_WCLK>,
+ <&matrixclk ZX297520V3_LSP_MPLL_D6_WCLK>,
+ <&matrixclk ZX297520V3_LSP_MPLL_D8_WCLK>,
+ <&matrixclk ZX297520V3_LSP_MPLL_D12_WCLK>,
+ <&matrixclk ZX297520V3_LSP_OSC26M_WCLK>,
+ <&matrixclk ZX297520V3_LSP_OSC32K_WCLK>,
+ <&matrixclk ZX297520V3_LSP_PCLK>,
+ <&matrixclk ZX297520V3_LSP_TDM_WCLK>,
+ <&matrixclk ZX297520V3_LSP_DPLL_D4_WCLK>;
+ clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12",
+ "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
index 815e8ceeb64e..57387529a708 100644
--- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -160,4 +160,60 @@
#define ZX297520V3_GMAC_RESET 7
#define ZX297520V3_VOU_RESET 8
+#define ZX297520V3_TIMER_L1_WCLK 1
+#define ZX297520V3_TIMER_L1_PCLK 2
+#define ZX297520V3_WDT_L2_WCLK 3
+#define ZX297520V3_WDT_L2_PCLK 4
+#define ZX297520V3_WDT_L3_WCLK 5
+#define ZX297520V3_WDT_L3_PCLK 6
+#define ZX297520V3_PWM_WCLK 7
+#define ZX297520V3_PWM_PCLK 8
+#define ZX297520V3_I2S0_WCLK 9
+#define ZX297520V3_I2S0_PCLK 10
+#define ZX297520V3_I2S1_WCLK 11
+#define ZX297520V3_I2S1_PCLK 12
+#define ZX297520V3_QSPI_WCLK 13
+#define ZX297520V3_QSPI_PCLK 14
+#define ZX297520V3_UART1_WCLK 15
+#define ZX297520V3_UART1_PCLK 16
+#define ZX297520V3_I2C1_WCLK 17
+#define ZX297520V3_I2C1_PCLK 18
+#define ZX297520V3_SPI0_WCLK 19
+#define ZX297520V3_SPI0_PCLK 20
+#define ZX297520V3_TIMER_LB_WCLK 21
+#define ZX297520V3_TIMER_LB_PCLK 22
+#define ZX297520V3_TIMER_LC_WCLK 23
+#define ZX297520V3_TIMER_LC_PCLK 24
+#define ZX297520V3_UART2_WCLK 25
+#define ZX297520V3_UART2_PCLK 26
+#define ZX297520V3_WDT_LE_WCLK 27
+#define ZX297520V3_WDT_LE_PCLK 28
+#define ZX297520V3_TIMER_LF_WCLK 29
+#define ZX297520V3_TIMER_LF_PCLK 30
+#define ZX297520V3_SPI1_WCLK 31
+#define ZX297520V3_SPI1_PCLK 32
+#define ZX297520V3_TIMER_L11_WCLK 33
+#define ZX297520V3_TIMER_L11_PCLK 34
+#define ZX297520V3_TDM_WCLK 35
+#define ZX297520V3_TDM_PCLK 36
+
+#define ZX297520V3_TIMER_L1_RESET 0
+#define ZX297520V3_WDT_L2_RESET 1
+#define ZX297520V3_WDT_L3_RESET 2
+#define ZX297520V3_PWM_RESET 3
+#define ZX297520V3_I2S0_RESET 4
+#define ZX297520V3_I2S1_RESET 5
+#define ZX297520V3_QSPI_RESET 6
+#define ZX297520V3_UART1_RESET 7
+#define ZX297520V3_I2C1_RESET 8
+#define ZX297520V3_SPI0_RESET 9
+#define ZX297520V3_TIMER_LB_RESET 10
+#define ZX297520V3_TIMER_LC_RESET 11
+#define ZX297520V3_UART2_RESET 12
+#define ZX297520V3_WDT_LE_RESET 13
+#define ZX297520V3_TIMER_LF_RESET 14
+#define ZX297520V3_SPI1_RESET 15
+#define ZX297520V3_TIMER_L11_RESET 16
+#define ZX297520V3_TDM_RESET 17
+
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v4 04/12] clk: zte: Add Clock registration infrastructure.
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com>
The next patches will implement the regmap clocks and PLL driver. The
actual hardware specific clock listing will live in a separate module.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
MAINTAINERS | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/zte/Kconfig | 17 +++++
drivers/clk/zte/Makefile | 5 ++
drivers/clk/zte/clk-regmap.c | 30 +++++++++
drivers/clk/zte/clk-zx.c | 157 +++++++++++++++++++++++++++++++++++++++++++
drivers/clk/zte/clk-zx.h | 79 ++++++++++++++++++++++
drivers/clk/zte/pll-zx.c | 19 ++++++
9 files changed, 310 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0cc1ede3c80c..f1f0459b2c72 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3870,6 +3870,7 @@ F: Documentation/devicetree/bindings/arm/zte.yaml
F: Documentation/devicetree/zte,zx297520v3-*
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
+F: drivers/clk/zte/
F: include/dt-bindings/clock/zte,zx297520v3-clk.h
ARM/ZYNQ ARCHITECTURE
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1717ce75a907..6f0a863951ca 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -545,6 +545,7 @@ source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/visconti/Kconfig"
source "drivers/clk/x86/Kconfig"
source "drivers/clk/xilinx/Kconfig"
+source "drivers/clk/zte/Kconfig"
source "drivers/clk/zynqmp/Kconfig"
# Kunit test cases
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cc108a75a900..13a5478f1112 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -167,5 +167,6 @@ ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_X86) += x86/
endif
obj-y += xilinx/
+obj-$(CONFIG_COMMON_CLK_ZTE) += zte/
obj-$(CONFIG_ARCH_ZYNQ) += zynq/
obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/
diff --git a/drivers/clk/zte/Kconfig b/drivers/clk/zte/Kconfig
new file mode 100644
index 000000000000..b7b65a2172a9
--- /dev/null
+++ b/drivers/clk/zte/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# ZTE Clock Drivers
+#
+
+config COMMON_CLK_ZTE
+ tristate "Clock driver for ZTE SoCs"
+ depends on ARCH_ZTE || COMPILE_TEST
+ default ARCH_ZTE
+ select AUXILIARY_BUS
+ select MFD_SYSCON
+ help
+ This option selects common clock infrastructure for ZTE based SoCs.
+ You will need to enable one or more SoC specific drivers to make use
+ of this.
+
+ Enable this if you are building a kernel for a ZTE designed board.
diff --git a/drivers/clk/zte/Makefile b/drivers/clk/zte/Makefile
new file mode 100644
index 000000000000..27db07293165
--- /dev/null
+++ b/drivers/clk/zte/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_COMMON_CLK_ZTE) += clk-zte.o
+
+clk-zte-y += clk-zx.o pll-zx.o clk-regmap.o
diff --git a/drivers/clk/zte/clk-regmap.c b/drivers/clk/zte/clk-regmap.c
new file mode 100644
index 000000000000..7908f1562f63
--- /dev/null
+++ b/drivers/clk/zte/clk-regmap.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Copyright (c) 2018 BayLibre, SAS.
+ * Copyright (c) 2026 Stefan Dösinger.
+ * Author: Stefan Dösinger <stefandoesinger@gmail.com>
+ */
+
+#include "clk-zx.h"
+
+int zx_clk_register_gates(struct device *dev, struct regmap *regmap,
+ const struct zx_gate_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks)
+{
+ return -ENODEV;
+}
+
+int zx_clk_register_dividers(struct device *dev, struct regmap *regmap,
+ const struct zx_div_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks)
+{
+ return -ENODEV;
+}
+
+int zx_clk_register_muxes(struct device *dev, struct regmap *regmap,
+ const struct zx_mux_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks)
+{
+ return -ENODEV;
+}
diff --git a/drivers/clk/zte/clk-zx.c b/drivers/clk/zte/clk-zx.c
new file mode 100644
index 000000000000..6e21c4a82a46
--- /dev/null
+++ b/drivers/clk/zte/clk-zx.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Stefan Dösinger
+ */
+
+#include <linux/platform_device.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include "clk-zx.h"
+
+static void zx_adev_release(struct device *dev)
+{
+ dev_info(dev, "Aux device released.\n");
+}
+
+static void zx_adev_unregister(void *data)
+{
+ struct auxiliary_device *adev = data;
+
+ auxiliary_device_delete(adev);
+ auxiliary_device_uninit(adev);
+}
+
+int zx_clk_probe(struct platform_device *pdev)
+{
+ unsigned int public_clk_count = 1, highest_id = 0;
+ struct clk_hw_onecell_data *clocks;
+ struct device *dev = &pdev->dev;
+ const struct zx_clk_data *data;
+ struct auxiliary_device *adev;
+ struct regmap *map;
+ struct clk *clk;
+ unsigned int i;
+ int res;
+
+ data = device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ map = device_node_to_regmap(dev->of_node);
+ if (!map)
+ return -EINVAL;
+
+ for (i = 0; i < data->num_plls; ++i) {
+ if (data->plls[i].id) {
+ unsigned int last_idx = data->plls[i].id + data->plls[i].num_postdivs - 1;
+
+ if (last_idx > highest_id)
+ highest_id = last_idx;
+ public_clk_count += data->plls[i].num_postdivs;
+ }
+ }
+ for (i = 0; i < data->num_muxes; ++i) {
+ if (data->muxes[i].id) {
+ if (data->muxes[i].id > highest_id)
+ highest_id = data->muxes[i].id;
+ public_clk_count++;
+ }
+ }
+ for (i = 0; i < data->num_divs; ++i) {
+ if (data->divs[i].id) {
+ if (data->divs[i].id > highest_id)
+ highest_id = data->divs[i].id;
+ public_clk_count++;
+ }
+ }
+ for (i = 0; i < data->num_gates; ++i) {
+ if (data->gates[i].id) {
+ if (data->gates[i].id > highest_id)
+ highest_id = data->gates[i].id;
+ public_clk_count++;
+ }
+ }
+
+ if (WARN_ON(public_clk_count != highest_id + 1))
+ return -EINVAL;
+
+ clocks = devm_kzalloc(dev, struct_size(clocks, hws, public_clk_count), GFP_KERNEL);
+ if (!clocks)
+ return -ENOMEM;
+ clocks->num = public_clk_count;
+
+ for (i = 0; i < data->num_inputs_enable; ++i) {
+ clk = devm_clk_get_enabled(dev, data->inputs_enable[i]);
+ if (IS_ERR(clk)) {
+ return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n",
+ data->inputs_enable[i]);
+ }
+ }
+ for (i = 0; i < data->num_inputs; ++i) {
+ clk = devm_clk_get(dev, data->inputs[i]);
+ if (IS_ERR(clk)) {
+ return dev_err_probe(dev, PTR_ERR(clk), "Input clk %s failure\n",
+ data->inputs[i]);
+ }
+ }
+
+ res = zx_clk_register_plls(dev, map, data->plls, data->num_plls, clocks);
+ if (res)
+ return res;
+
+ res = zx_clk_register_muxes(dev, map, data->muxes, data->num_muxes, clocks);
+ if (res)
+ return res;
+
+ res = zx_clk_register_dividers(dev, map, data->divs, data->num_divs, clocks);
+ if (res)
+ return res;
+
+ res = zx_clk_register_gates(dev, map, data->gates, data->num_gates, clocks);
+ if (res)
+ return res;
+
+ /* This is to catch holes in the tables rather than registration errors. The count vs
+ * highest ID should catch most static issues. This check here will trigger if an ID is
+ * reused by accident.
+ */
+ for (i = 1; i < public_clk_count; i++) {
+ if (WARN(!clocks->hws[i], "Clock %u not registered\n", i))
+ return -EINVAL;
+ }
+
+ res = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clocks);
+ if (res)
+ return res;
+
+ adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
+ if (!adev)
+ return -ENOMEM;
+
+ adev->name = data->reset_auxdev_name;
+ adev->dev.parent = dev;
+ adev->dev.release = zx_adev_release;
+ adev->dev.of_node = dev->of_node;
+
+ res = auxiliary_device_init(adev);
+ if (res)
+ return dev_err_probe(dev, res, "Failed to init aux dev %s\n", adev->name);
+
+ res = auxiliary_device_add(adev);
+ if (res) {
+ auxiliary_device_uninit(adev);
+ return dev_err_probe(dev, res, "Failed to add aux dev %s\n", adev->name);
+ }
+
+ return devm_add_action_or_reset(dev, zx_adev_unregister, adev);
+}
+EXPORT_SYMBOL_NS_GPL(zx_clk_probe, "ZTE_CLK");
+
+MODULE_AUTHOR("Stefan Dösinger <stefandoesinger@gmail.com>");
+MODULE_DESCRIPTION("ZTE common clock driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/zte/clk-zx.h b/drivers/clk/zte/clk-zx.h
new file mode 100644
index 000000000000..b39bbed2d420
--- /dev/null
+++ b/drivers/clk/zte/clk-zx.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2026 Stefan Dösinger
+ */
+
+#ifndef __DRV_CLK_ZX_H
+#define __DRV_CLK_ZX_H
+
+#include <linux/platform_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+struct zx_pll_desc {
+ unsigned int id;
+ const char *name;
+ const char * const *parents;
+ unsigned int num_parents;
+ unsigned long rate;
+ const unsigned int *postdivs;
+ unsigned int num_postdivs;
+ u16 reg;
+};
+
+struct zx_mux_desc {
+ unsigned int id;
+ const char *name;
+ const char * const *parents;
+ unsigned int num_parents;
+ u16 reg;
+ u8 shift, size;
+};
+
+struct zx_div_desc {
+ unsigned int id;
+ const char *name, *parent;
+ u16 reg;
+ u8 shift, size;
+};
+
+struct zx_gate_desc {
+ unsigned int id;
+ const char *name, *parent;
+ unsigned long flags;
+ u16 reg;
+ u8 shift;
+};
+
+int zx_clk_register_plls(struct device *dev, struct regmap *regmap,
+ const struct zx_pll_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks);
+int zx_clk_register_muxes(struct device *dev, struct regmap *regmap,
+ const struct zx_mux_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks);
+int zx_clk_register_dividers(struct device *dev, struct regmap *regmap,
+ const struct zx_div_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks);
+int zx_clk_register_gates(struct device *dev, struct regmap *regmap,
+ const struct zx_gate_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks);
+
+struct zx_clk_data {
+ const char * const *inputs_enable;
+ unsigned int num_inputs_enable;
+ const char * const *inputs;
+ unsigned int num_inputs;
+ const struct zx_pll_desc *plls;
+ unsigned int num_plls;
+ const struct zx_mux_desc *muxes;
+ unsigned int num_muxes;
+ const struct zx_div_desc *divs;
+ unsigned int num_divs;
+ const struct zx_gate_desc *gates;
+ unsigned int num_gates;
+ const char *reset_auxdev_name;
+};
+
+int zx_clk_probe(struct platform_device *pdev);
+
+#endif /* __DRV_CLK_ZX_H */
diff --git a/drivers/clk/zte/pll-zx.c b/drivers/clk/zte/pll-zx.c
new file mode 100644
index 000000000000..c0475d5441fb
--- /dev/null
+++ b/drivers/clk/zte/pll-zx.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Stefan Dösinger
+ */
+#include <linux/clk-provider.h>
+#include <linux/rational.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/units.h>
+#include <linux/clk.h>
+
+#include "clk-zx.h"
+
+int zx_clk_register_plls(struct device *dev, struct regmap *regmap,
+ const struct zx_pll_desc *desc, unsigned int num,
+ struct clk_hw_onecell_data *clocks)
+{
+ return -ENODEV;
+}
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v4 05/12] clk: zte: Add zx PLL support infrastructure
From: Stefan Dösinger @ 2026-06-16 20:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com>
I am guessing how much of this is reusable among other zx chips or even
differently named ZTE platforms (if there are any). From reading the old
zx2967 code, I think the PLL code would be reusable there, maybe with
platform specific bitmasks but otherwise the same logic.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
drivers/clk/zte/pll-zx.c | 460 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 459 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zte/pll-zx.c b/drivers/clk/zte/pll-zx.c
index c0475d5441fb..f077b6b56841 100644
--- a/drivers/clk/zte/pll-zx.c
+++ b/drivers/clk/zte/pll-zx.c
@@ -11,9 +11,467 @@
#include "clk-zx.h"
+/* This code has only been tested with zx297520v3 PLLs, but from reading the zx296718 clock code it
+ * looks like PLL registers are similar. ZTE's sources explain the PLL register contents only in a
+ * .cmm file (A Lauterback TRACE32 script) and some unused headers in their U-Boot code dump, which
+ * may not be accurate. When calculating the frequencies from the default PLL configuration the
+ * results match the fixed rate clocks from their clock driver.
+ *
+ * The 26mhz and 32khz clocks can be easily observed with the timers. The 104mhz output can be
+ * observed through the UART. One 122.88 PLL can be observed through the TDM device. All others can
+ * only be indirectly infered, e.g. by comparing CPU speed or SDIO transfer rate between the fixed
+ * 26 MHz oscillator and the provided PLL frequency.
+ *
+ * The formula to calculate the clock is ((ref / refdiv) * fbdiv) / postdiv1 / postdiv2. The masks
+ * are given below. There are a few control flags:
+ *
+ * Bit 31: Disables the PLL, but passes the reference through unmodified. If POSTDIV_OUT_DISABLE
+ * still matters is different between PLLs.
+ * Bit 30: Returns if the PLL is locked
+ * Bit 29: Not named in ZTE's code, but can be set. There is no obvious impact. Lock times are
+ * unchanged, so it doesn't influence or bypass lock detection. It doesn't raise any IRQs or
+ * influence GPIOs.
+ * Bit 27: Given its name it likely disables the Delta-Sigma Modulator, if one exists at all. The
+ * boot ROM sets it on every PLL. Unsetting it marginally decreases the time it takes to
+ * lock to the reference clock (from ~400us to ~300us). Regardless of this bit I could not
+ * make the supposed fractional part in register 2 work.
+ * Bit 24: Bypasses the VCO, but still applies refdiv and postdiv. Doesn't matter if PLL_DISABLE=1.
+ */
+
+#define ZX29_PLL_DISABLE BIT(31)
+#define ZX29_PLL_LOCKED BIT(30)
+#define ZX29_PLL_LOCK_FILTER BIT(29)
+#define ZX29_PLL_DSM_DISABLE BIT(27)
+#define ZX29_PLL_PARENT_MASK GENMASK(26, 25)
+#define ZX29_PLL_PARENT_SHIFT 25
+#define ZX29_PLL_BYPASS BIT(24)
+#define ZX29_PLL_REFDIV_MASK GENMASK(23, 18)
+#define ZX29_PLL_REFDIV_SHIFT 18
+#define ZX29_PLL_FBDIV_MASK GENMASK(17, 6)
+#define ZX29_PLL_FBDIV_SHIFT 6
+#define ZX29_PLL_POSTDIV1_MASK GENMASK(5, 3)
+#define ZX29_PLL_POSTDIV1_SHIFT 3
+#define ZX29_PLL_POSTDIV2_MASK GENMASK(2, 0)
+#define ZX29_PLL_POSTDIV2_SHIFT 0
+
+/* The second register is supposed to have another 24 bit value that gets added to fbdiv but it is
+ * always 0 in the preconfigured values. I could not observe any effect from setting it to something
+ * other than 0, regardless of the DSM disable bit. It is possible that it is only supported by
+ * dpll, which is a possible parent for i2s.
+ *
+ * Bits 28:25 contain more flags:
+ *
+ * Bit 27: Setting ZX29_PLL_DACAP slows down the lock time and obivates the speed gained from
+ * !DSM_DISABLE. No other effect observed.
+ *
+ * Bit 26: ZX29_PLL_4PHASE_OUT_DISABLE is set on some PLLs on boot but not on others. It is set on
+ * boot on mpll and upll, but not gpll, dpll or unknownpll. I am not sure what it does
+ * either. The SDIO devices break if they are fed from gpll with this flag set, but they
+ * work ok if they are fed from mpll without this flag set.
+ *
+ * Bit 25: ZX29_PLL_POSTDIV_OUT_DISABLE seems to disable the PLL output entirely. Whether it is
+ * bypassed by PLL_DISABLE differs between PLLs. gpll still produces an output clock if
+ * PLL_DISABLE = 1 and POSTDIV_DISABLE = 1, but produces no output if PLL_DISABLE = 0 and
+ * POSTDIV_DISABLE = 1. The dpll feeder ("unknownpll") at 0x100 produces no output clock
+ * if both PLL_DISABLE and POSTDIV_DISABLE are set to 1.
+ *
+ * Bit 24: ZX29_PLL_VCO_OUT_DISABLE probably disables the output of the VCO clock without
+ * post-VCO-dividers, but the raw VCO output is not a possible parent of any consumer clock,
+ * so I could not confirm this. It does not disable the VCO entirely - that's what
+ * PLL_DISABLE does.
+ *
+ * A spinlock should not be needed. PLLs don't share their registers with anything else and the
+ * global prepare mutex and enable spinlock should be enough. Beware of conflicts in reg2 between
+ * POSTDIV_OUT_DISABLE and the fractional value in case you find out how fractional dividers work
+ * and add support for them.
+ */
+#define ZX29_PLL_REG2_OFFSET 4
+#define ZX29_PLL_DACAP BIT(27)
+#define ZX29_PLL_4PHASE_OUT_DISABLE BIT(26)
+#define ZX29_PLL_POSTDIV_OUT_DISABLE BIT(25)
+#define ZX29_PLL_VCO_OUT_DISABLE BIT(24)
+
+/* The VCO's frequency range is limited. The stock settings run the VCO between 960 and 1248 MHz.
+ * Ad-hoc testing with gpll suggests that at least this PLL remains stable down to about 7 MHz and
+ * up to 2 GHz and produces a clock that can be used by the SDIO controller. Attempting to run the
+ * mpll VCO at 624 MHz and setting postdiv1 = postdiv2 = 1 - which should result in the same output
+ * frequency - or running it at 1872 MHz with an effective post divider of 3 crashes the CPU. Most
+ * likely the PLLs become unstable outside their core range and the SDIO controller is much more
+ * forgiving than CPU and DRAM are.
+ */
+#define ZX29_PLL_VCO_MAX_FREQ (1300*HZ_PER_MHZ)
+#define ZX29_PLL_VCO_MIN_FREQ (900*HZ_PER_MHZ)
+
+struct zx29_clk_pll {
+ struct clk_hw hw;
+ struct device *dev;
+ struct regmap *map;
+ unsigned long init_rate;
+ u16 reg;
+};
+
+static inline struct zx29_clk_pll *to_zx29_clk_pll(struct clk_hw *hw)
+{
+ return container_of(hw, struct zx29_clk_pll, hw);
+}
+
+static int zx29_pll_is_prepared(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ int res;
+
+ res = regmap_test_bits(pll->map, pll->reg, ZX29_PLL_DISABLE);
+ if (res < 0)
+ return res;
+
+ return !res;
+}
+
+static int zx29_pll_prepare(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ u32 val;
+ int res;
+
+ res = regmap_clear_bits(pll->map, pll->reg, ZX29_PLL_DISABLE);
+ if (res < 0)
+ return res;
+
+ /* Lock duration is usually between 300us to 500us */
+ res = regmap_read_poll_timeout(pll->map, pll->reg, val, val & ZX29_PLL_LOCKED, 50, 2000);
+ dev_dbg(pll->dev, "%s: Enable result %u val 0x%08x\n", clk_hw_get_name(&pll->hw), res, val);
+ return res;
+}
+
+static void zx29_pll_unprepare(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+
+ regmap_set_bits(pll->map, pll->reg, ZX29_PLL_DISABLE);
+}
+
+static int zx29_pll_is_enabled(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ int res;
+
+ res = regmap_test_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET,
+ ZX29_PLL_POSTDIV_OUT_DISABLE);
+ if (res < 0)
+ return res;
+
+ return !res;
+}
+
+static int zx29_pll_enable(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+
+ return regmap_clear_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET,
+ ZX29_PLL_POSTDIV_OUT_DISABLE);
+}
+
+static void zx29_pll_disable(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+
+ regmap_set_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET,
+ ZX29_PLL_POSTDIV_OUT_DISABLE);
+}
+
+static unsigned long zx29_pll_get_rate(const struct zx29_clk_pll *pll, unsigned long parent_rate,
+ u32 setting)
+{
+ unsigned long refdiv, fbdiv, postdiv1, postdiv2, freq;
+ const char *name = clk_hw_get_name(&pll->hw);
+ u64 vco;
+
+ refdiv = (setting & ZX29_PLL_REFDIV_MASK) >> ZX29_PLL_REFDIV_SHIFT;
+ fbdiv = (setting & ZX29_PLL_FBDIV_MASK) >> ZX29_PLL_FBDIV_SHIFT;
+ postdiv1 = (setting & ZX29_PLL_POSTDIV1_MASK) >> ZX29_PLL_POSTDIV1_SHIFT;
+ postdiv2 = (setting & ZX29_PLL_POSTDIV2_MASK) >> ZX29_PLL_POSTDIV2_SHIFT;
+ dev_dbg(pll->dev, "%s: reference clock %lu HZ, PLL setting 0x%08x\n",
+ name, parent_rate, setting);
+
+ if (!refdiv || !postdiv1 || !postdiv2) {
+ dev_err(pll->dev, "%s: divide by zero (%lu, %lu, %lu)\n", name, refdiv, postdiv1,
+ postdiv2);
+ return 0;
+ }
+
+ vco = div_u64((u64)parent_rate * fbdiv, refdiv);
+ freq = div_u64(div_u64(vco, postdiv1), postdiv2);
+ dev_dbg(pll->dev, "%s: refdiv %lu fbdiv %lu\n", name, refdiv, fbdiv);
+ dev_dbg(pll->dev, "%s: postdiv1 %lu postdiv2 %lu\n", name, postdiv1, postdiv2);
+
+ dev_dbg(pll->dev, "%s: %lu MHZ\n", name, freq / HZ_PER_MHZ);
+
+ return freq;
+}
+
+static unsigned long zx29_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ u32 val;
+ int res;
+
+ res = regmap_read(pll->map, pll->reg, &val);
+ if (res < 0)
+ return res;
+
+ return zx29_pll_get_rate(pll, parent_rate, val);
+}
+
+static u32 zx29_pll_calc_values(const struct zx29_clk_pll *pll, unsigned long parent_rate,
+ unsigned long rate)
+{
+ const unsigned int postdiv1_max = (1 << hweight32(ZX29_PLL_POSTDIV1_MASK)) - 1;
+ const unsigned int postdiv2_max = (1 << hweight32(ZX29_PLL_POSTDIV2_MASK)) - 1;
+ unsigned long fbdiv, refdiv, best_fbdiv = 0, best_refdiv = 0;
+ u32 postdiv1 = 0, postdiv2 = 0, i, j, setting;
+ const char *name = clk_hw_get_name(&pll->hw);
+ long best = LONG_MAX;
+
+ /* This code produces the same VCO settings that the boot loader and stock firmware use for
+ * the standard frequencies. It has seen only very little manual testing beyond that.
+ *
+ * The goal is to find a VCO setting that gets us as close as possible to the desired output
+ * rate, while being within the VCO's operating limits and achievable with the input value
+ * range. It is iterating over possible post-VCO diver values (1-7)*(1-7) to look for valid
+ * VCO target frequencies and then looks for refdiv and fbdiv values to achieve the VCO
+ * frequency from the reference frequency.
+ */
+ for (j = 1; j <= postdiv2_max; j++) {
+ for (i = 1; i <= postdiv1_max; i++) {
+ u64 vco = (u64)rate * i * j;
+ long out;
+
+ if (vco > ZX29_PLL_VCO_MAX_FREQ || vco < ZX29_PLL_VCO_MIN_FREQ)
+ continue;
+
+ rational_best_approximation(vco, parent_rate,
+ (1 << hweight32(ZX29_PLL_FBDIV_MASK)) - 1,
+ (1 << hweight32(ZX29_PLL_REFDIV_MASK)) - 1,
+ &fbdiv, &refdiv);
+ setting = fbdiv << ZX29_PLL_FBDIV_SHIFT;
+ setting |= refdiv << ZX29_PLL_REFDIV_SHIFT;
+ setting |= i << ZX29_PLL_POSTDIV1_SHIFT;
+ setting |= j << ZX29_PLL_POSTDIV2_SHIFT;
+ out = zx29_pll_get_rate(pll, parent_rate, setting);
+
+ if (abs(out - rate) > best)
+ continue;
+
+ if (abs(out - rate) < best) {
+ postdiv1 = i;
+ postdiv2 = j;
+ best_fbdiv = fbdiv;
+ best_refdiv = refdiv;
+ best = abs(out - rate);
+
+ if (!best)
+ goto search_done;
+ }
+ }
+ }
+search_done:
+
+ if (!postdiv1) {
+ dev_err(pll->dev, "Did not find a setting for %lu Hz, parent %lu Hz\n",
+ rate, parent_rate);
+ return 0;
+ }
+
+ dev_dbg(pll->dev, "%s: parent rate %lu\n", name, parent_rate);
+ dev_dbg(pll->dev, "%s: found VCO dividers %u and %u\n", name, postdiv1, postdiv2);
+ dev_dbg(pll->dev, "%s: VCO target rate %lu\n", name, rate * postdiv1 * postdiv2);
+
+ dev_dbg(pll->dev, "%s: Got fbdiv = %lu refdiv = %lu\n", name, best_fbdiv, best_refdiv);
+
+ setting = best_fbdiv << ZX29_PLL_FBDIV_SHIFT;
+ setting |= best_refdiv << ZX29_PLL_REFDIV_SHIFT;
+ setting |= postdiv1 << ZX29_PLL_POSTDIV1_SHIFT;
+ setting |= postdiv2 << ZX29_PLL_POSTDIV2_SHIFT;
+ dev_dbg(pll->dev, "%s: Final setting 0x%08x\n", name, setting);
+
+ return setting;
+}
+
+static int zx29_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ unsigned long new_rate, parent_rate = clk_hw_get_rate(clk_hw_get_parent(&pll->hw));
+ u32 setting;
+
+ setting = zx29_pll_calc_values(pll, parent_rate, req->rate);
+ if (!setting)
+ return -EINVAL;
+
+ new_rate = zx29_pll_get_rate(pll, parent_rate, setting);
+ if (new_rate != req->rate) {
+ dev_warn(pll->dev, "Did not find an exact match. Want %lu, got %lu\n",
+ req->rate, new_rate);
+ req->rate = new_rate;
+ }
+
+ return 0;
+}
+
+static int zx29_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ int res = -EINVAL;
+ u32 setting;
+
+ setting = zx29_pll_calc_values(pll, parent_rate, rate);
+ if (zx29_pll_get_rate(pll, parent_rate, setting) == rate) {
+ res = regmap_update_bits(pll->map, pll->reg, 0x00ffffff, setting);
+ dev_info(pll->dev, "%s: Setting rate: 0x%08x\n", clk_hw_get_name(hw), setting);
+ }
+
+ return res;
+}
+
+static u8 zx29_pll_get_parent(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ u32 val;
+ int res;
+
+ res = regmap_read(pll->map, pll->reg, &val);
+ if (res < 0)
+ return 0xff;
+
+ val = (val & ZX29_PLL_PARENT_MASK) >> ZX29_PLL_PARENT_SHIFT;
+ dev_dbg(pll->dev, "%s: Parent 0x%x\n", clk_hw_get_name(hw), val);
+
+ return val;
+}
+
+static int zx29_pll_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ u32 idx_shift = index << ZX29_PLL_PARENT_SHIFT;
+ int res;
+ u32 val;
+
+ res = regmap_update_bits(pll->map, pll->reg, ZX29_PLL_PARENT_MASK, idx_shift);
+ if (res < 0)
+ return res;
+
+ res = regmap_read(pll->map, pll->reg, &val);
+ if (res < 0)
+ return res;
+
+ if ((val & ZX29_PLL_PARENT_MASK) != idx_shift) {
+ dev_err(pll->dev, "Hardware rejected PLL parent %u\n", index);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int zx29_pll_init(struct clk_hw *hw)
+{
+ struct zx29_clk_pll *pll = to_zx29_clk_pll(hw);
+ const char *name = clk_hw_get_name(hw);
+ int res;
+
+ dev_dbg(pll->dev, "%s: initializing\n", name);
+
+ /* Remove the bypass flag so we don't have to bother with it in enable/disable. I have
+ * never seen it set by the earlier boot stages anyhow.
+ */
+ res = regmap_clear_bits(pll->map, pll->reg, ZX29_PLL_BYPASS);
+ if (res < 0)
+ return res;
+
+ if (regmap_test_bits(pll->map, pll->reg, ZX29_PLL_DISABLE) > 0) {
+ if (pll->init_rate) {
+ dev_dbg(pll->dev, "%s: Setting to %lu Hz\n", name, pll->init_rate);
+ res = clk_set_rate(pll->hw.clk, pll->init_rate);
+ if (res) {
+ dev_err(pll->dev, "%s: Failed to set rate.\n", name);
+ return res;
+ }
+ }
+
+ /* Set ZX29_PLL_POSTDIV_OUT_DISABLE for PLLs that have ZX29_PLL_DISABLE for
+ * consistency with .enable and .prepare. This ensures that .prepare doesn't
+ * inadvertedly enable PLLs without .enable being called.
+ */
+ res = regmap_set_bits(pll->map, pll->reg + ZX29_PLL_REG2_OFFSET,
+ ZX29_PLL_POSTDIV_OUT_DISABLE);
+ if (res < 0)
+ return res;
+ }
+
+ return 0;
+}
+
+const struct clk_ops zx29_pll_ops = {
+ .init = zx29_pll_init,
+ .is_prepared = zx29_pll_is_prepared,
+ .prepare = zx29_pll_prepare,
+ .unprepare = zx29_pll_unprepare,
+ .is_enabled = zx29_pll_is_enabled,
+ .enable = zx29_pll_enable,
+ .disable = zx29_pll_disable,
+ .recalc_rate = zx29_pll_recalc_rate,
+ .determine_rate = zx29_pll_determine_rate,
+ .get_parent = zx29_pll_get_parent,
+ .set_parent = zx29_pll_set_parent,
+ .set_rate = zx29_pll_set_rate,
+};
+
int zx_clk_register_plls(struct device *dev, struct regmap *regmap,
const struct zx_pll_desc *desc, unsigned int num,
struct clk_hw_onecell_data *clocks)
{
- return -ENODEV;
+ struct zx29_clk_pll *pll;
+ unsigned int i, f;
+ struct clk_hw *hw;
+ char plldiv[32];
+ int res;
+
+ for (i = 0; i < num; ++i) {
+ struct clk_init_data init = {};
+
+ pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return -ENOMEM;
+
+ init.name = desc[i].name;
+ init.ops = &zx29_pll_ops;
+ init.parent_names = desc[i].parents;
+ init.num_parents = desc[i].num_parents;
+ pll->hw.init = &init;
+ pll->map = regmap;
+ pll->reg = desc[i].reg;
+ pll->init_rate = desc[i].rate;
+
+ res = devm_clk_hw_register(dev, &pll->hw);
+ if (res)
+ return res;
+ if (desc[i].id && desc[i].postdivs && desc[i].postdivs[0] == 1)
+ clocks->hws[desc[i].id] = &pll->hw;
+
+ for (f = 0; f < desc[i].num_postdivs; ++f) {
+ if (desc[i].postdivs[f] == 1)
+ continue;
+
+ snprintf(plldiv, sizeof(plldiv), "%s_d%u", desc[i].name,
+ desc[i].postdivs[f]);
+ hw = devm_clk_hw_register_fixed_factor(dev, plldiv, desc[i].name,
+ 0, 1, desc[i].postdivs[f]);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ dev_dbg(pll->dev, "%s: %lu hz\n", clk_hw_get_name(hw), clk_hw_get_rate(hw));
+
+ if (desc[i].id)
+ clocks->hws[desc[i].id + f] = hw;
+ }
+ }
+
+ return 0;
}
--
2.53.0
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